1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Type.h"
23 #include "llvm/ADT/STLExtras.h"
27 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28 const TargetInstrInfo &tii)
29 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30 Subtarget(st), TII(tii) {
33 void SparcRegisterInfo::
34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
35 unsigned SrcReg, int FI,
36 const TargetRegisterClass *RC) const {
37 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
38 if (RC == SP::IntRegsRegisterClass)
39 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
41 else if (RC == SP::FPRegsRegisterClass)
42 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
44 else if (RC == SP::DFPRegsRegisterClass)
45 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
48 assert(0 && "Can't store this register to stack slot");
51 void SparcRegisterInfo::
52 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
53 unsigned DestReg, int FI,
54 const TargetRegisterClass *RC) const {
55 if (RC == SP::IntRegsRegisterClass)
56 BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
57 else if (RC == SP::FPRegsRegisterClass)
58 BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
59 else if (RC == SP::DFPRegsRegisterClass)
60 BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
62 assert(0 && "Can't load this register from stack slot");
65 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
66 MachineBasicBlock::iterator I,
67 unsigned DestReg, unsigned SrcReg,
68 const TargetRegisterClass *RC) const {
69 if (RC == SP::IntRegsRegisterClass)
70 BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
71 else if (RC == SP::FPRegsRegisterClass)
72 BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
73 else if (RC == SP::DFPRegsRegisterClass)
74 BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
77 assert (0 && "Can't copy this register");
80 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
84 MachineInstr *NewMI = NULL;
85 switch (MI->getOpcode()) {
87 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
88 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
89 if (OpNum == 0) // COPY -> STORE
90 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
91 .addReg(MI->getOperand(2).getReg());
93 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
94 .addFrameIndex(FI).addImm(0);
101 if (OpNum == 0) // COPY -> STORE
102 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
103 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
105 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
106 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
111 NewMI->copyKillDeadInfo(MI);
115 const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
116 static const unsigned CalleeSaveRegs[] = { 0 };
117 return CalleeSaveRegs;
120 const TargetRegisterClass* const*
121 SparcRegisterInfo::getCalleeSaveRegClasses() const {
122 static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
123 return CalleeSaveRegClasses;
127 void SparcRegisterInfo::
128 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
129 MachineBasicBlock::iterator I) const {
130 MachineInstr &MI = *I;
131 int Size = MI.getOperand(0).getImmedValue();
132 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
135 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
140 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
142 MachineInstr &MI = *II;
143 while (!MI.getOperand(i).isFrameIndex()) {
145 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
148 int FrameIndex = MI.getOperand(i).getFrameIndex();
150 // Addressable stack objects are accessed using neg. offsets from %fp
151 MachineFunction &MF = *MI.getParent()->getParent();
152 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
153 MI.getOperand(i+1).getImmedValue();
155 // Replace frame index with a frame pointer reference.
156 if (Offset >= -4096 && Offset <= 4095) {
157 // If the offset is small enough to fit in the immediate field, directly
159 MI.getOperand(i).ChangeToRegister(SP::I6, false);
160 MI.getOperand(i+1).ChangeToImmediate(Offset);
162 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
163 // scavenge a register here instead of reserving G1 all of the time.
164 unsigned OffHi = (unsigned)Offset >> 10U;
165 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
167 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
169 // Insert: G1+%lo(offset) into the user.
170 MI.getOperand(i).ChangeToRegister(SP::G1, false);
171 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
175 void SparcRegisterInfo::
176 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
178 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
179 MachineBasicBlock &MBB = MF.front();
180 MachineFrameInfo *MFI = MF.getFrameInfo();
182 // Get the number of bytes to allocate from the FrameInfo
183 int NumBytes = (int) MFI->getStackSize();
185 // Emit the correct save instruction based on the number of bytes in
186 // the frame. Minimum stack frame size according to V8 ABI is:
187 // 16 words for register window spill
188 // 1 word for address of returned aggregate-value
189 // + 6 words for passing parameters on the stack
191 // 23 words * 4 bytes per word = 92 bytes
193 // Round up to next doubleword boundary -- a double-word boundary
194 // is required by the ABI.
195 NumBytes = (NumBytes + 7) & ~7;
196 NumBytes = -NumBytes;
198 if (NumBytes >= -4096) {
199 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
200 SP::O6).addImm(NumBytes).addReg(SP::O6);
202 MachineBasicBlock::iterator InsertPt = MBB.begin();
203 // Emit this the hard way. This clobbers G1 which we always know is
205 unsigned OffHi = (unsigned)NumBytes >> 10U;
206 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
208 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
209 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
210 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
211 .addReg(SP::O6).addReg(SP::G1);
215 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
216 MachineBasicBlock &MBB) const {
217 MachineBasicBlock::iterator MBBI = prior(MBB.end());
218 assert(MBBI->getOpcode() == SP::RETL &&
219 "Can only put epilog before 'retl' instruction!");
220 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
224 unsigned SparcRegisterInfo::getRARegister() const {
225 assert(0 && "What is the return address register");
229 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
230 assert(0 && "What is the frame register");
234 #include "SparcGenRegisterInfo.inc"