1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Type.h"
23 #include "llvm/ADT/STLExtras.h"
26 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
27 const TargetInstrInfo &tii)
28 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
29 Subtarget(st), TII(tii) {
32 void SparcRegisterInfo::
33 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
34 unsigned SrcReg, int FI,
35 const TargetRegisterClass *RC) const {
36 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
37 if (RC == SP::IntRegsRegisterClass)
38 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
40 else if (RC == SP::FPRegsRegisterClass)
41 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
43 else if (RC == SP::DFPRegsRegisterClass)
44 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
47 assert(0 && "Can't store this register to stack slot");
50 void SparcRegisterInfo::
51 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
52 unsigned DestReg, int FI,
53 const TargetRegisterClass *RC) const {
54 if (RC == SP::IntRegsRegisterClass)
55 BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
56 else if (RC == SP::FPRegsRegisterClass)
57 BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
58 else if (RC == SP::DFPRegsRegisterClass)
59 BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
61 assert(0 && "Can't load this register from stack slot");
64 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator I,
66 unsigned DestReg, unsigned SrcReg,
67 const TargetRegisterClass *RC) const {
68 if (RC == SP::IntRegsRegisterClass)
69 BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
70 else if (RC == SP::FPRegsRegisterClass)
71 BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
72 else if (RC == SP::DFPRegsRegisterClass)
73 BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
76 assert (0 && "Can't copy this register");
79 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
83 MachineInstr *NewMI = NULL;
84 switch (MI->getOpcode()) {
86 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
87 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
88 if (OpNum == 0) // COPY -> STORE
89 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
90 .addReg(MI->getOperand(2).getReg());
92 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
93 .addFrameIndex(FI).addImm(0);
100 if (OpNum == 0) // COPY -> STORE
101 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
102 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
104 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
105 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
110 NewMI->copyKillDeadInfo(MI);
114 const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
115 static const unsigned CalleeSavedRegs[] = { 0 };
116 return CalleeSavedRegs;
119 const TargetRegisterClass* const*
120 SparcRegisterInfo::getCalleeSavedRegClasses() const {
121 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
122 return CalleeSavedRegClasses;
125 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
129 void SparcRegisterInfo::
130 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
131 MachineBasicBlock::iterator I) const {
132 MachineInstr &MI = *I;
133 int Size = MI.getOperand(0).getImmedValue();
134 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
137 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
142 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
144 MachineInstr &MI = *II;
145 while (!MI.getOperand(i).isFrameIndex()) {
147 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
150 int FrameIndex = MI.getOperand(i).getFrameIndex();
152 // Addressable stack objects are accessed using neg. offsets from %fp
153 MachineFunction &MF = *MI.getParent()->getParent();
154 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
155 MI.getOperand(i+1).getImmedValue();
157 // Replace frame index with a frame pointer reference.
158 if (Offset >= -4096 && Offset <= 4095) {
159 // If the offset is small enough to fit in the immediate field, directly
161 MI.getOperand(i).ChangeToRegister(SP::I6, false);
162 MI.getOperand(i+1).ChangeToImmediate(Offset);
164 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
165 // scavenge a register here instead of reserving G1 all of the time.
166 unsigned OffHi = (unsigned)Offset >> 10U;
167 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
169 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
171 // Insert: G1+%lo(offset) into the user.
172 MI.getOperand(i).ChangeToRegister(SP::G1, false);
173 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
177 void SparcRegisterInfo::
178 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
180 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
181 MachineBasicBlock &MBB = MF.front();
182 MachineFrameInfo *MFI = MF.getFrameInfo();
184 // Get the number of bytes to allocate from the FrameInfo
185 int NumBytes = (int) MFI->getStackSize();
187 // Emit the correct save instruction based on the number of bytes in
188 // the frame. Minimum stack frame size according to V8 ABI is:
189 // 16 words for register window spill
190 // 1 word for address of returned aggregate-value
191 // + 6 words for passing parameters on the stack
193 // 23 words * 4 bytes per word = 92 bytes
195 // Round up to next doubleword boundary -- a double-word boundary
196 // is required by the ABI.
197 NumBytes = (NumBytes + 7) & ~7;
198 NumBytes = -NumBytes;
200 if (NumBytes >= -4096) {
201 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
202 SP::O6).addImm(NumBytes).addReg(SP::O6);
204 MachineBasicBlock::iterator InsertPt = MBB.begin();
205 // Emit this the hard way. This clobbers G1 which we always know is
207 unsigned OffHi = (unsigned)NumBytes >> 10U;
208 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
210 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
211 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
212 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
213 .addReg(SP::O6).addReg(SP::G1);
217 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
218 MachineBasicBlock &MBB) const {
219 MachineBasicBlock::iterator MBBI = prior(MBB.end());
220 assert(MBBI->getOpcode() == SP::RETL &&
221 "Can only put epilog before 'retl' instruction!");
222 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
226 unsigned SparcRegisterInfo::getRARegister() const {
227 assert(0 && "What is the return address register");
231 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
232 assert(0 && "What is the frame register");
236 #include "SparcGenRegisterInfo.inc"