1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Type.h"
22 #include "llvm/ADT/STLExtras.h"
26 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
27 const TargetInstrInfo &tii)
28 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
29 Subtarget(st), TII(tii) {
32 void SparcRegisterInfo::
33 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
34 unsigned SrcReg, int FI,
35 const TargetRegisterClass *RC) const {
36 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
37 if (RC == SP::IntRegsRegisterClass)
38 BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
39 else if (RC == SP::FPRegsRegisterClass)
40 BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
41 else if (RC == SP::DFPRegsRegisterClass)
42 BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
44 assert(0 && "Can't store this register to stack slot");
47 void SparcRegisterInfo::
48 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
49 unsigned DestReg, int FI,
50 const TargetRegisterClass *RC) const {
51 if (RC == SP::IntRegsRegisterClass)
52 BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
53 else if (RC == SP::FPRegsRegisterClass)
54 BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
55 else if (RC == SP::DFPRegsRegisterClass)
56 BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
58 assert(0 && "Can't load this register from stack slot");
61 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator I,
63 unsigned DestReg, unsigned SrcReg,
64 const TargetRegisterClass *RC) const {
65 if (RC == SP::IntRegsRegisterClass)
66 BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
67 else if (RC == SP::FPRegsRegisterClass)
68 BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
69 else if (RC == SP::DFPRegsRegisterClass)
70 BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
71 1, DestReg).addReg(SrcReg);
73 assert (0 && "Can't copy this register");
76 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
80 MachineInstr *NewMI = NULL;
81 switch (MI->getOpcode()) {
83 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
84 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
85 if (OpNum == 0) // COPY -> STORE
86 NewMI = BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
87 .addReg(MI->getOperand(2).getReg());
89 NewMI = BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg())
90 .addFrameIndex(FI).addImm(0);
97 if (OpNum == 0) // COPY -> STORE
98 NewMI = BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
99 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
101 NewMI = BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
102 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
107 NewMI->copyKillDeadInfo(MI);
111 const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
112 static const unsigned CalleeSaveRegs[] = { 0 };
113 return CalleeSaveRegs;
116 const TargetRegisterClass* const*
117 SparcRegisterInfo::getCalleeSaveRegClasses() const {
118 static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
119 return CalleeSaveRegClasses;
123 void SparcRegisterInfo::
124 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator I) const {
126 MachineInstr &MI = *I;
127 int Size = MI.getOperand(0).getImmedValue();
128 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
131 BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
136 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
138 MachineInstr &MI = *II;
139 while (!MI.getOperand(i).isFrameIndex()) {
141 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
144 int FrameIndex = MI.getOperand(i).getFrameIndex();
146 // Addressable stack objects are accessed using neg. offsets from %fp
147 MachineFunction &MF = *MI.getParent()->getParent();
148 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
149 MI.getOperand(i+1).getImmedValue();
151 // Replace frame index with a frame pointer reference.
152 if (Offset >= -4096 && Offset <= 4095) {
153 // If the offset is small enough to fit in the immediate field, directly
155 MI.getOperand(i).ChangeToRegister(SP::I6, false);
156 MI.getOperand(i+1).ChangeToImmediate(Offset);
158 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
159 // scavenge a register here instead of reserving G1 all of the time.
160 unsigned OffHi = (unsigned)Offset >> 10U;
161 BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
163 BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
164 SP::G1).addReg(SP::G1).addReg(SP::I6);
165 // Insert: G1+%lo(offset) into the user.
166 MI.getOperand(i).ChangeToRegister(SP::G1, false);
167 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
171 void SparcRegisterInfo::
172 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
174 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
175 MachineBasicBlock &MBB = MF.front();
176 MachineFrameInfo *MFI = MF.getFrameInfo();
178 // Get the number of bytes to allocate from the FrameInfo
179 int NumBytes = (int) MFI->getStackSize();
181 // Emit the correct save instruction based on the number of bytes in
182 // the frame. Minimum stack frame size according to V8 ABI is:
183 // 16 words for register window spill
184 // 1 word for address of returned aggregate-value
185 // + 6 words for passing parameters on the stack
187 // 23 words * 4 bytes per word = 92 bytes
189 // Round up to next doubleword boundary -- a double-word boundary
190 // is required by the ABI.
191 NumBytes = (NumBytes + 7) & ~7;
192 NumBytes = -NumBytes;
194 if (NumBytes >= -4096) {
195 BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
196 SP::O6).addImm(NumBytes).addReg(SP::O6);
198 MachineBasicBlock::iterator InsertPt = MBB.begin();
199 // Emit this the hard way. This clobbers G1 which we always know is
201 unsigned OffHi = (unsigned)NumBytes >> 10U;
202 BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
204 BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
205 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
206 BuildMI(MBB, InsertPt, SP::SAVErr, 2,
207 SP::O6).addReg(SP::O6).addReg(SP::G1);
211 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
212 MachineBasicBlock &MBB) const {
213 MachineBasicBlock::iterator MBBI = prior(MBB.end());
214 assert(MBBI->getOpcode() == SP::RETL &&
215 "Can only put epilog before 'retl' instruction!");
216 BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
219 unsigned SparcRegisterInfo::getRARegister() const {
220 assert(0 && "What is the return address register");
224 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
225 assert(0 && "What is the frame register");
229 #include "SparcGenRegisterInfo.inc"