1 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV8 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8RegisterInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Type.h"
20 #include "Support/STLExtras.h"
23 SparcV8RegisterInfo::SparcV8RegisterInfo()
24 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
25 V8::ADJCALLSTACKUP) {}
27 int SparcV8RegisterInfo::storeRegToStackSlot(
28 MachineBasicBlock &MBB,
29 MachineBasicBlock::iterator MBBI,
30 unsigned SrcReg, int FrameIdx,
31 const TargetRegisterClass *RC) const
33 assert (RC == SparcV8::IntRegsRegisterClass
34 && "Can only store 32-bit values to stack slots");
36 BuildMI (V8::STrm, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg);
41 int SparcV8RegisterInfo::loadRegFromStackSlot(
42 MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator MBBI,
44 unsigned DestReg, int FrameIdx,
45 const TargetRegisterClass *RC) const
47 assert (RC == SparcV8::IntRegsRegisterClass
48 && "Can only load 32-bit registers from stack slots");
50 BuildMI (V8::LDmr, 2).addReg (DestReg).addFrameIndex (FrameIdx).addSImm (0);
55 int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI,
57 unsigned DestReg, unsigned SrcReg,
58 const TargetRegisterClass *RC) const {
59 assert (RC == SparcV8::IntRegsRegisterClass
60 && "Can only copy 32-bit registers");
62 BuildMI (V8::ORrr, 3, DestReg).addReg (V8::G0).addReg (SrcReg));
66 void SparcV8RegisterInfo::
67 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator I) const {
70 << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n"
71 << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n";
76 SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
77 MachineBasicBlock::iterator II) const {
79 MachineInstr &MI = *II;
80 while (!MI.getOperand(i).isFrameIndex()) {
82 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
85 int FrameIndex = MI.getOperand(i).getFrameIndex();
87 // Replace frame index with a frame pointer reference
88 MI.SetMachineOperandReg (i, V8::FP);
90 // Addressable stack objects are accessed using neg. offsets from %fp
91 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
92 MI.getOperand(i+1).getImmedValue();
94 MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
97 void SparcV8RegisterInfo::
98 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
100 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
101 MachineBasicBlock &MBB = MF.front();
102 MachineFrameInfo *MFI = MF.getFrameInfo();
104 // Get the number of bytes to allocate from the FrameInfo
105 int NumBytes = (int) MFI->getStackSize() + 4;
107 // Emit the correct save instruction based on the number of bytes in the frame.
108 // Minimum stack frame size according to V8 ABI is:
109 // 16 words for register window spill
110 // 1 word for address of returned aggregate-value
111 // + 6 words for passing parameters on the stack
113 // 23 words * 4 bytes per word = 92 bytes
115 NumBytes = (NumBytes + 3) & ~3; // Round up to next word boundary
116 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
117 V8::SP).addImm(-NumBytes).addReg(V8::SP);
120 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
121 MachineBasicBlock &MBB) const {
122 MachineBasicBlock::iterator MBBI = prior(MBB.end());
123 assert(MBBI->getOpcode() == V8::RETL &&
124 "Can only put epilog before 'retl' instruction!");
125 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
128 #include "SparcV8GenRegisterInfo.inc"
130 const TargetRegisterClass*
131 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
132 switch (Ty->getPrimitiveID()) {
133 case Type::FloatTyID: return &FPRegsInstance;
134 case Type::DoubleTyID: return &DFPRegsInstance;
136 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
137 default: assert(0 && "Invalid type to getClass!");
139 case Type::SByteTyID:
140 case Type::UByteTyID:
141 case Type::ShortTyID:
142 case Type::UShortTyID:
145 case Type::PointerTyID: return &IntRegsInstance;