1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Type.h"
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/STLExtras.h"
27 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28 const TargetInstrInfo &tii)
29 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30 Subtarget(st), TII(tii) {
33 void SparcRegisterInfo::
34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
35 unsigned SrcReg, bool isKill, int FI,
36 const TargetRegisterClass *RC) const {
37 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
38 if (RC == SP::IntRegsRegisterClass)
39 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
40 .addReg(SrcReg, false, false, isKill);
41 else if (RC == SP::FPRegsRegisterClass)
42 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
43 .addReg(SrcReg, false, false, isKill);
44 else if (RC == SP::DFPRegsRegisterClass)
45 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
46 .addReg(SrcReg, false, false, isKill);
48 assert(0 && "Can't store this register to stack slot");
51 void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
53 SmallVectorImpl<MachineOperand> &Addr,
54 const TargetRegisterClass *RC,
55 SmallVectorImpl<MachineInstr*> &NewMIs) const {
57 if (RC == SP::IntRegsRegisterClass)
59 else if (RC == SP::FPRegsRegisterClass)
61 else if (RC == SP::DFPRegsRegisterClass)
64 assert(0 && "Can't load this register");
65 MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
66 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
67 MachineOperand &MO = Addr[i];
69 MIB.addReg(MO.getReg());
70 else if (MO.isImmediate())
71 MIB.addImm(MO.getImm());
74 MIB.addFrameIndex(MO.getIndex());
77 MIB.addReg(SrcReg, false, false, isKill);
78 NewMIs.push_back(MIB);
82 void SparcRegisterInfo::
83 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
84 unsigned DestReg, int FI,
85 const TargetRegisterClass *RC) const {
86 if (RC == SP::IntRegsRegisterClass)
87 BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
88 else if (RC == SP::FPRegsRegisterClass)
89 BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
90 else if (RC == SP::DFPRegsRegisterClass)
91 BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
93 assert(0 && "Can't load this register from stack slot");
96 void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
97 SmallVectorImpl<MachineOperand> &Addr,
98 const TargetRegisterClass *RC,
99 SmallVectorImpl<MachineInstr*> &NewMIs) const {
101 if (RC == SP::IntRegsRegisterClass)
103 else if (RC == SP::FPRegsRegisterClass)
105 else if (RC == SP::DFPRegsRegisterClass)
108 assert(0 && "Can't load this register");
109 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
110 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
111 MachineOperand &MO = Addr[i];
113 MIB.addReg(MO.getReg());
115 MIB.addImm(MO.getImm());
118 MIB.addFrameIndex(MO.getIndex());
121 NewMIs.push_back(MIB);
125 void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
126 MachineBasicBlock::iterator I,
128 const MachineInstr *Orig) const {
129 MachineInstr *MI = Orig->clone();
130 MI->getOperand(0).setReg(DestReg);
134 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
135 SmallVectorImpl<unsigned> &Ops,
137 if (Ops.size() != 1) return NULL;
139 unsigned OpNum = Ops[0];
140 bool isFloat = false;
141 MachineInstr *NewMI = NULL;
142 switch (MI->getOpcode()) {
144 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
145 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
146 if (OpNum == 0) // COPY -> STORE
147 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
148 .addReg(MI->getOperand(2).getReg());
150 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
151 .addFrameIndex(FI).addImm(0);
158 if (OpNum == 0) // COPY -> STORE
159 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
160 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
162 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
163 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
168 NewMI->copyKillDeadInfo(MI);
172 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
174 static const unsigned CalleeSavedRegs[] = { 0 };
175 return CalleeSavedRegs;
178 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
179 BitVector Reserved(getNumRegs());
180 Reserved.set(SP::G2);
181 Reserved.set(SP::G3);
182 Reserved.set(SP::G4);
183 Reserved.set(SP::O6);
184 Reserved.set(SP::I6);
185 Reserved.set(SP::I7);
186 Reserved.set(SP::G0);
187 Reserved.set(SP::G5);
188 Reserved.set(SP::G6);
189 Reserved.set(SP::G7);
194 const TargetRegisterClass* const*
195 SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
196 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
197 return CalleeSavedRegClasses;
200 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
204 void SparcRegisterInfo::
205 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
206 MachineBasicBlock::iterator I) const {
207 MachineInstr &MI = *I;
208 int Size = MI.getOperand(0).getImm();
209 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
212 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
216 void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
217 int SPAdj, RegScavenger *RS) const {
218 assert(SPAdj == 0 && "Unexpected");
221 MachineInstr &MI = *II;
222 while (!MI.getOperand(i).isFrameIndex()) {
224 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
227 int FrameIndex = MI.getOperand(i).getIndex();
229 // Addressable stack objects are accessed using neg. offsets from %fp
230 MachineFunction &MF = *MI.getParent()->getParent();
231 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
232 MI.getOperand(i+1).getImm();
234 // Replace frame index with a frame pointer reference.
235 if (Offset >= -4096 && Offset <= 4095) {
236 // If the offset is small enough to fit in the immediate field, directly
238 MI.getOperand(i).ChangeToRegister(SP::I6, false);
239 MI.getOperand(i+1).ChangeToImmediate(Offset);
241 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
242 // scavenge a register here instead of reserving G1 all of the time.
243 unsigned OffHi = (unsigned)Offset >> 10U;
244 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
246 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
248 // Insert: G1+%lo(offset) into the user.
249 MI.getOperand(i).ChangeToRegister(SP::G1, false);
250 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
254 void SparcRegisterInfo::
255 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
257 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
258 MachineBasicBlock &MBB = MF.front();
259 MachineFrameInfo *MFI = MF.getFrameInfo();
261 // Get the number of bytes to allocate from the FrameInfo
262 int NumBytes = (int) MFI->getStackSize();
264 // Emit the correct save instruction based on the number of bytes in
265 // the frame. Minimum stack frame size according to V8 ABI is:
266 // 16 words for register window spill
267 // 1 word for address of returned aggregate-value
268 // + 6 words for passing parameters on the stack
270 // 23 words * 4 bytes per word = 92 bytes
272 // Round up to next doubleword boundary -- a double-word boundary
273 // is required by the ABI.
274 NumBytes = (NumBytes + 7) & ~7;
275 NumBytes = -NumBytes;
277 if (NumBytes >= -4096) {
278 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
279 SP::O6).addImm(NumBytes).addReg(SP::O6);
281 MachineBasicBlock::iterator InsertPt = MBB.begin();
282 // Emit this the hard way. This clobbers G1 which we always know is
284 unsigned OffHi = (unsigned)NumBytes >> 10U;
285 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
287 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
288 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
289 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
290 .addReg(SP::O6).addReg(SP::G1);
294 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
295 MachineBasicBlock &MBB) const {
296 MachineBasicBlock::iterator MBBI = prior(MBB.end());
297 assert(MBBI->getOpcode() == SP::RETL &&
298 "Can only put epilog before 'retl' instruction!");
299 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
303 unsigned SparcRegisterInfo::getRARegister() const {
304 assert(0 && "What is the return address register");
308 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
309 assert(0 && "What is the frame register");
313 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
314 assert(0 && "What is the exception register");
318 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
319 assert(0 && "What is the exception handler register");
323 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
324 assert(0 && "What is the dwarf register number");
328 #include "SparcGenRegisterInfo.inc"