1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget.is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget.isV9()">;
34 // HasNoV9 - This predicate is true when the target doesn't have V9
35 // instructions. Use of this is just a hack for the isel not having proper
36 // costs for V8 instructions that are more expensive than their V9 ones.
37 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
39 // HasVIS - This is true when the target processor has VIS extensions.
40 def HasVIS : Predicate<"Subtarget.isVIS()">;
42 // HasHardQuad - This is true when the target processor supports quad floating
43 // point instructions.
44 def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">;
46 // UseDeprecatedInsts - This predicate is true when the target processor is a
47 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
48 // to use when appropriate. In either of these cases, the instruction selector
49 // will pick deprecated instructions.
50 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
52 //===----------------------------------------------------------------------===//
53 // Instruction Pattern Stuff
54 //===----------------------------------------------------------------------===//
56 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
58 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
60 def LO10 : SDNodeXForm<imm, [{
61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
65 def HI22 : SDNodeXForm<imm, [{
66 // Transformation function: shift the immediate value down into the low bits.
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
70 def SETHIimm : PatLeaf<(imm), [{
71 return isShiftedUInt<22, 10>(N->getZExtValue());
75 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
76 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
79 def SparcMEMrrAsmOperand : AsmOperandClass {
81 let ParserMethod = "parseMEMrrOperand";
84 def SparcMEMriAsmOperand : AsmOperandClass {
86 let ParserMethod = "parseMEMriOperand";
89 def MEMrr : Operand<iPTR> {
90 let PrintMethod = "printMemOperand";
91 let MIOperandInfo = (ops ptr_rc, ptr_rc);
92 let ParserMatchClass = SparcMEMrrAsmOperand;
94 def MEMri : Operand<iPTR> {
95 let PrintMethod = "printMemOperand";
96 let MIOperandInfo = (ops ptr_rc, i32imm);
97 let ParserMatchClass = SparcMEMriAsmOperand;
100 def TLSSym : Operand<iPTR>;
102 // Branch targets have OtherVT type.
103 def brtarget : Operand<OtherVT> {
104 let EncoderMethod = "getBranchTargetOpValue";
107 def calltarget : Operand<i32> {
108 let EncoderMethod = "getCallTargetOpValue";
111 // Operand for printing out a condition code.
112 let PrintMethod = "printCCOperand" in
113 def CCOp : Operand<i32>;
116 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
118 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
120 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
122 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
124 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
126 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
128 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
130 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
133 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
135 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
137 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
138 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
139 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
140 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
141 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
143 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
144 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
146 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
147 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
148 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
149 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
151 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
152 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
153 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
155 // These are target-independent nodes, but have target-specific formats.
156 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
157 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
160 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
161 [SDNPHasChain, SDNPOutGlue]>;
162 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
165 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
166 def call : SDNode<"SPISD::CALL", SDT_SPCall,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
170 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
171 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
172 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
174 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
175 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
177 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
178 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
179 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
183 def getPCX : Operand<i32> {
184 let PrintMethod = "printGetPCX";
187 //===----------------------------------------------------------------------===//
188 // SPARC Flag Conditions
189 //===----------------------------------------------------------------------===//
191 // Note that these values must be kept in sync with the CCOp::CondCode enum
193 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
194 def ICC_NE : ICC_VAL< 9>; // Not Equal
195 def ICC_E : ICC_VAL< 1>; // Equal
196 def ICC_G : ICC_VAL<10>; // Greater
197 def ICC_LE : ICC_VAL< 2>; // Less or Equal
198 def ICC_GE : ICC_VAL<11>; // Greater or Equal
199 def ICC_L : ICC_VAL< 3>; // Less
200 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
201 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
202 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
203 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
204 def ICC_POS : ICC_VAL<14>; // Positive
205 def ICC_NEG : ICC_VAL< 6>; // Negative
206 def ICC_VC : ICC_VAL<15>; // Overflow Clear
207 def ICC_VS : ICC_VAL< 7>; // Overflow Set
209 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
210 def FCC_U : FCC_VAL<23>; // Unordered
211 def FCC_G : FCC_VAL<22>; // Greater
212 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
213 def FCC_L : FCC_VAL<20>; // Less
214 def FCC_UL : FCC_VAL<19>; // Unordered or Less
215 def FCC_LG : FCC_VAL<18>; // Less or Greater
216 def FCC_NE : FCC_VAL<17>; // Not Equal
217 def FCC_E : FCC_VAL<25>; // Equal
218 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
219 def FCC_GE : FCC_VAL<25>; // Greater or Equal
220 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
221 def FCC_LE : FCC_VAL<27>; // Less or Equal
222 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
223 def FCC_O : FCC_VAL<29>; // Ordered
225 //===----------------------------------------------------------------------===//
226 // Instruction Class Templates
227 //===----------------------------------------------------------------------===//
229 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
230 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
231 RegisterClass RC, ValueType Ty, Operand immOp> {
232 def rr : F3_1<2, Op3Val,
233 (outs RC:$dst), (ins RC:$b, RC:$c),
234 !strconcat(OpcStr, " $b, $c, $dst"),
235 [(set Ty:$dst, (OpNode Ty:$b, Ty:$c))]>;
236 def ri : F3_2<2, Op3Val,
237 (outs RC:$dst), (ins RC:$b, immOp:$c),
238 !strconcat(OpcStr, " $b, $c, $dst"),
239 [(set Ty:$dst, (OpNode Ty:$b, (Ty simm13:$c)))]>;
242 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
244 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
245 def rr : F3_1<2, Op3Val,
246 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
247 !strconcat(OpcStr, " $b, $c, $dst"), []>;
248 def ri : F3_2<2, Op3Val,
249 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
250 !strconcat(OpcStr, " $b, $c, $dst"), []>;
253 //===----------------------------------------------------------------------===//
255 //===----------------------------------------------------------------------===//
257 // Pseudo instructions.
258 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
259 : InstSP<outs, ins, asmstr, pattern> {
260 let isCodeGenOnly = 1;
266 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
269 let Defs = [O6], Uses = [O6] in {
270 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
271 "!ADJCALLSTACKDOWN $amt",
272 [(callseq_start timm:$amt)]>;
273 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
274 "!ADJCALLSTACKUP $amt1",
275 [(callseq_end timm:$amt1, timm:$amt2)]>;
278 let hasSideEffects = 1, mayStore = 1 in {
279 let rd = 0, rs1 = 0, rs2 = 0 in
280 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
282 [(flushw)]>, Requires<[HasV9]>;
283 let rd = 0, rs1 = 1, simm13 = 3 in
284 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
290 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
293 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
294 // instruction selection into a branch sequence. This has to handle all
295 // permutations of selection between i32/f32/f64 on ICC and FCC.
296 // Expanded after instruction selection.
297 let Uses = [ICC], usesCustomInserter = 1 in {
298 def SELECT_CC_Int_ICC
299 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
300 "; SELECT_CC_Int_ICC PSEUDO!",
301 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
303 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
304 "; SELECT_CC_FP_ICC PSEUDO!",
305 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
307 def SELECT_CC_DFP_ICC
308 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
309 "; SELECT_CC_DFP_ICC PSEUDO!",
310 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
312 def SELECT_CC_QFP_ICC
313 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
314 "; SELECT_CC_QFP_ICC PSEUDO!",
315 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
318 let usesCustomInserter = 1, Uses = [FCC] in {
320 def SELECT_CC_Int_FCC
321 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
322 "; SELECT_CC_Int_FCC PSEUDO!",
323 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
326 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
327 "; SELECT_CC_FP_FCC PSEUDO!",
328 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
329 def SELECT_CC_DFP_FCC
330 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
331 "; SELECT_CC_DFP_FCC PSEUDO!",
332 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
333 def SELECT_CC_QFP_FCC
334 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
335 "; SELECT_CC_QFP_FCC PSEUDO!",
336 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
340 // Section A.3 - Synthetic Instructions, p. 85
341 // special cases of JMPL:
342 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
343 let rd = 0, rs1 = 15 in
344 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
345 "jmp %o7+$val", [(retflag simm13:$val)]>;
347 let rd = 0, rs1 = 31 in
348 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
352 // Section B.1 - Load Integer Instructions, p. 90
353 def LDSBrr : F3_1<3, 0b001001,
354 (outs IntRegs:$dst), (ins MEMrr:$addr),
355 "ldsb [$addr], $dst",
356 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
357 def LDSBri : F3_2<3, 0b001001,
358 (outs IntRegs:$dst), (ins MEMri:$addr),
359 "ldsb [$addr], $dst",
360 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
361 def LDSHrr : F3_1<3, 0b001010,
362 (outs IntRegs:$dst), (ins MEMrr:$addr),
363 "ldsh [$addr], $dst",
364 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
365 def LDSHri : F3_2<3, 0b001010,
366 (outs IntRegs:$dst), (ins MEMri:$addr),
367 "ldsh [$addr], $dst",
368 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
369 def LDUBrr : F3_1<3, 0b000001,
370 (outs IntRegs:$dst), (ins MEMrr:$addr),
371 "ldub [$addr], $dst",
372 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
373 def LDUBri : F3_2<3, 0b000001,
374 (outs IntRegs:$dst), (ins MEMri:$addr),
375 "ldub [$addr], $dst",
376 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
377 def LDUHrr : F3_1<3, 0b000010,
378 (outs IntRegs:$dst), (ins MEMrr:$addr),
379 "lduh [$addr], $dst",
380 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
381 def LDUHri : F3_2<3, 0b000010,
382 (outs IntRegs:$dst), (ins MEMri:$addr),
383 "lduh [$addr], $dst",
384 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
385 def LDrr : F3_1<3, 0b000000,
386 (outs IntRegs:$dst), (ins MEMrr:$addr),
388 [(set i32:$dst, (load ADDRrr:$addr))]>;
389 def LDri : F3_2<3, 0b000000,
390 (outs IntRegs:$dst), (ins MEMri:$addr),
392 [(set i32:$dst, (load ADDRri:$addr))]>;
394 // Section B.2 - Load Floating-point Instructions, p. 92
395 def LDFrr : F3_1<3, 0b100000,
396 (outs FPRegs:$dst), (ins MEMrr:$addr),
398 [(set f32:$dst, (load ADDRrr:$addr))]>;
399 def LDFri : F3_2<3, 0b100000,
400 (outs FPRegs:$dst), (ins MEMri:$addr),
402 [(set f32:$dst, (load ADDRri:$addr))]>;
403 def LDDFrr : F3_1<3, 0b100011,
404 (outs DFPRegs:$dst), (ins MEMrr:$addr),
406 [(set f64:$dst, (load ADDRrr:$addr))]>;
407 def LDDFri : F3_2<3, 0b100011,
408 (outs DFPRegs:$dst), (ins MEMri:$addr),
410 [(set f64:$dst, (load ADDRri:$addr))]>;
411 def LDQFrr : F3_1<3, 0b100010,
412 (outs QFPRegs:$dst), (ins MEMrr:$addr),
414 [(set f128:$dst, (load ADDRrr:$addr))]>,
415 Requires<[HasV9, HasHardQuad]>;
416 def LDQFri : F3_2<3, 0b100010,
417 (outs QFPRegs:$dst), (ins MEMri:$addr),
419 [(set f128:$dst, (load ADDRri:$addr))]>,
420 Requires<[HasV9, HasHardQuad]>;
422 // Section B.4 - Store Integer Instructions, p. 95
423 def STBrr : F3_1<3, 0b000101,
424 (outs), (ins MEMrr:$addr, IntRegs:$rd),
426 [(truncstorei8 i32:$rd, ADDRrr:$addr)]>;
427 def STBri : F3_2<3, 0b000101,
428 (outs), (ins MEMri:$addr, IntRegs:$rd),
430 [(truncstorei8 i32:$rd, ADDRri:$addr)]>;
431 def STHrr : F3_1<3, 0b000110,
432 (outs), (ins MEMrr:$addr, IntRegs:$rd),
434 [(truncstorei16 i32:$rd, ADDRrr:$addr)]>;
435 def STHri : F3_2<3, 0b000110,
436 (outs), (ins MEMri:$addr, IntRegs:$rd),
438 [(truncstorei16 i32:$rd, ADDRri:$addr)]>;
439 def STrr : F3_1<3, 0b000100,
440 (outs), (ins MEMrr:$addr, IntRegs:$rd),
442 [(store i32:$rd, ADDRrr:$addr)]>;
443 def STri : F3_2<3, 0b000100,
444 (outs), (ins MEMri:$addr, IntRegs:$rd),
446 [(store i32:$rd, ADDRri:$addr)]>;
448 // Section B.5 - Store Floating-point Instructions, p. 97
449 def STFrr : F3_1<3, 0b100100,
450 (outs), (ins MEMrr:$addr, FPRegs:$rd),
452 [(store f32:$rd, ADDRrr:$addr)]>;
453 def STFri : F3_2<3, 0b100100,
454 (outs), (ins MEMri:$addr, FPRegs:$rd),
456 [(store f32:$rd, ADDRri:$addr)]>;
457 def STDFrr : F3_1<3, 0b100111,
458 (outs), (ins MEMrr:$addr, DFPRegs:$rd),
460 [(store f64:$rd, ADDRrr:$addr)]>;
461 def STDFri : F3_2<3, 0b100111,
462 (outs), (ins MEMri:$addr, DFPRegs:$rd),
464 [(store f64:$rd, ADDRri:$addr)]>;
465 def STQFrr : F3_1<3, 0b100110,
466 (outs), (ins MEMrr:$addr, QFPRegs:$rd),
468 [(store f128:$rd, ADDRrr:$addr)]>,
469 Requires<[HasV9, HasHardQuad]>;
470 def STQFri : F3_2<3, 0b100110,
471 (outs), (ins MEMri:$addr, QFPRegs:$rd),
473 [(store f128:$rd, ADDRri:$addr)]>,
474 Requires<[HasV9, HasHardQuad]>;
476 // Section B.9 - SETHI Instruction, p. 104
477 def SETHIi: F2_1<0b100,
478 (outs IntRegs:$rd), (ins i32imm:$imm22),
480 [(set i32:$rd, SETHIimm:$imm22)]>;
482 // Section B.10 - NOP Instruction, p. 105
483 // (It's a special case of SETHI)
484 let rd = 0, imm22 = 0 in
485 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
487 // Section B.11 - Logical Instructions, p. 106
488 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
490 def ANDNrr : F3_1<2, 0b000101,
491 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
493 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
494 def ANDNri : F3_2<2, 0b000101,
495 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
496 "andn $b, $c, $dst", []>;
498 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
500 def ORNrr : F3_1<2, 0b000110,
501 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
503 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
504 def ORNri : F3_2<2, 0b000110,
505 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
506 "orn $b, $c, $dst", []>;
507 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
509 def XNORrr : F3_1<2, 0b000111,
510 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
512 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
513 def XNORri : F3_2<2, 0b000111,
514 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
515 "xnor $b, $c, $dst", []>;
517 // Section B.12 - Shift Instructions, p. 107
518 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
519 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
520 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
522 // Section B.13 - Add Instructions, p. 108
523 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
525 // "LEA" forms of add (patterns to make tblgen happy)
526 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
527 def LEA_ADDri : F3_2<2, 0b000000,
528 (outs IntRegs:$dst), (ins MEMri:$addr),
529 "add ${addr:arith}, $dst",
530 [(set iPTR:$dst, ADDRri:$addr)]>;
533 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
535 let Uses = [ICC], Defs = [ICC] in
536 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
538 // Section B.15 - Subtract Instructions, p. 110
539 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, i32imm>;
540 let Uses = [ICC], Defs = [ICC] in
541 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
544 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
546 let Defs = [ICC], rd = 0 in {
547 def CMPrr : F3_1<2, 0b010100,
548 (outs), (ins IntRegs:$b, IntRegs:$c),
550 [(SPcmpicc i32:$b, i32:$c)]>;
551 def CMPri : F3_2<2, 0b010100,
552 (outs), (ins IntRegs:$b, i32imm:$c),
554 [(SPcmpicc i32:$b, (i32 simm13:$c))]>;
557 let Uses = [ICC], Defs = [ICC] in
558 def SUBXCCrr: F3_1<2, 0b011100,
559 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
560 "subxcc $b, $c, $dst", []>;
563 // Section B.18 - Multiply Instructions, p. 113
565 defm UMUL : F3_12np<"umul", 0b001010>;
566 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
569 // Section B.19 - Divide Instructions, p. 115
571 defm UDIV : F3_12np<"udiv", 0b001110>;
572 defm SDIV : F3_12np<"sdiv", 0b001111>;
575 // Section B.20 - SAVE and RESTORE, p. 117
576 defm SAVE : F3_12np<"save" , 0b111100>;
577 defm RESTORE : F3_12np<"restore", 0b111101>;
579 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
581 // unconditional branch class.
582 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
583 : F2_2<0b010, (outs), ins, asmstr, pattern> {
585 let isTerminator = 1;
586 let hasDelaySlot = 1;
591 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
593 // conditional branch class:
594 class BranchSP<dag ins, string asmstr, list<dag> pattern>
595 : F2_2<0b010, (outs), ins, asmstr, pattern> {
597 let isTerminator = 1;
598 let hasDelaySlot = 1;
601 // Indirect branch instructions.
602 let isTerminator = 1, isBarrier = 1,
603 hasDelaySlot = 1, isBranch =1,
604 isIndirectBranch = 1, rd = 0 in {
605 def BINDrr : F3_1<2, 0b111000,
606 (outs), (ins MEMrr:$ptr),
608 [(brind ADDRrr:$ptr)]>;
609 def BINDri : F3_2<2, 0b111000,
610 (outs), (ins MEMri:$ptr),
612 [(brind ADDRri:$ptr)]>;
616 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
618 [(SPbricc bb:$imm22, imm:$cond)]>;
620 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
622 // floating-point conditional branch class:
623 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
624 : F2_2<0b110, (outs), ins, asmstr, pattern> {
626 let isTerminator = 1;
627 let hasDelaySlot = 1;
631 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
633 [(SPbrfcc bb:$imm22, imm:$cond)]>;
636 // Section B.24 - Call and Link Instruction, p. 125
637 // This is the only Format 1 instruction
639 hasDelaySlot = 1, isCall = 1 in {
640 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
644 let Inst{29-0} = disp;
648 def JMPLrr : F3_1<2, 0b111000,
649 (outs), (ins MEMrr:$ptr, variable_ops),
651 [(call ADDRrr:$ptr)]> { let rd = 15; }
652 def JMPLri : F3_2<2, 0b111000,
653 (outs), (ins MEMri:$ptr, variable_ops),
655 [(call ADDRri:$ptr)]> { let rd = 15; }
658 // Section B.28 - Read State Register Instructions
659 let Uses = [Y], rs1 = 0, rs2 = 0 in
660 def RDY : F3_1<2, 0b101000,
661 (outs IntRegs:$dst), (ins),
664 // Section B.29 - Write State Register Instructions
665 let Defs = [Y], rd = 0 in {
666 def WRYrr : F3_1<2, 0b110000,
667 (outs), (ins IntRegs:$b, IntRegs:$c),
668 "wr $b, $c, %y", []>;
669 def WRYri : F3_2<2, 0b110000,
670 (outs), (ins IntRegs:$b, i32imm:$c),
671 "wr $b, $c, %y", []>;
673 // Convert Integer to Floating-point Instructions, p. 141
674 def FITOS : F3_3u<2, 0b110100, 0b011000100,
675 (outs FPRegs:$dst), (ins FPRegs:$src),
677 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
678 def FITOD : F3_3u<2, 0b110100, 0b011001000,
679 (outs DFPRegs:$dst), (ins FPRegs:$src),
681 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
682 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
683 (outs QFPRegs:$dst), (ins FPRegs:$src),
685 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>,
686 Requires<[HasHardQuad]>;
688 // Convert Floating-point to Integer Instructions, p. 142
689 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
690 (outs FPRegs:$dst), (ins FPRegs:$src),
692 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
693 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
694 (outs FPRegs:$dst), (ins DFPRegs:$src),
696 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
697 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
698 (outs FPRegs:$dst), (ins QFPRegs:$src),
700 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>,
701 Requires<[HasHardQuad]>;
703 // Convert between Floating-point Formats Instructions, p. 143
704 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
705 (outs DFPRegs:$dst), (ins FPRegs:$src),
707 [(set f64:$dst, (fextend f32:$src))]>;
708 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
709 (outs QFPRegs:$dst), (ins FPRegs:$src),
711 [(set f128:$dst, (fextend f32:$src))]>,
712 Requires<[HasHardQuad]>;
713 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
714 (outs FPRegs:$dst), (ins DFPRegs:$src),
716 [(set f32:$dst, (fround f64:$src))]>;
717 def FDTOQ : F3_3u<2, 0b110100, 0b01101110,
718 (outs QFPRegs:$dst), (ins DFPRegs:$src),
720 [(set f128:$dst, (fextend f64:$src))]>,
721 Requires<[HasHardQuad]>;
722 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
723 (outs FPRegs:$dst), (ins QFPRegs:$src),
725 [(set f32:$dst, (fround f128:$src))]>,
726 Requires<[HasHardQuad]>;
727 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
728 (outs DFPRegs:$dst), (ins QFPRegs:$src),
730 [(set f64:$dst, (fround f128:$src))]>,
731 Requires<[HasHardQuad]>;
733 // Floating-point Move Instructions, p. 144
734 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
735 (outs FPRegs:$dst), (ins FPRegs:$src),
736 "fmovs $src, $dst", []>;
737 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
738 (outs FPRegs:$dst), (ins FPRegs:$src),
740 [(set f32:$dst, (fneg f32:$src))]>;
741 def FABSS : F3_3u<2, 0b110100, 0b000001001,
742 (outs FPRegs:$dst), (ins FPRegs:$src),
744 [(set f32:$dst, (fabs f32:$src))]>;
747 // Floating-point Square Root Instructions, p.145
748 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
749 (outs FPRegs:$dst), (ins FPRegs:$src),
751 [(set f32:$dst, (fsqrt f32:$src))]>;
752 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
753 (outs DFPRegs:$dst), (ins DFPRegs:$src),
755 [(set f64:$dst, (fsqrt f64:$src))]>;
756 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
757 (outs QFPRegs:$dst), (ins QFPRegs:$src),
759 [(set f128:$dst, (fsqrt f128:$src))]>,
760 Requires<[HasHardQuad]>;
764 // Floating-point Add and Subtract Instructions, p. 146
765 def FADDS : F3_3<2, 0b110100, 0b001000001,
766 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
767 "fadds $src1, $src2, $dst",
768 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
769 def FADDD : F3_3<2, 0b110100, 0b001000010,
770 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
771 "faddd $src1, $src2, $dst",
772 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
773 def FADDQ : F3_3<2, 0b110100, 0b001000011,
774 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
775 "faddq $src1, $src2, $dst",
776 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>,
777 Requires<[HasHardQuad]>;
779 def FSUBS : F3_3<2, 0b110100, 0b001000101,
780 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
781 "fsubs $src1, $src2, $dst",
782 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
783 def FSUBD : F3_3<2, 0b110100, 0b001000110,
784 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
785 "fsubd $src1, $src2, $dst",
786 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
787 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
788 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
789 "fsubq $src1, $src2, $dst",
790 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>,
791 Requires<[HasHardQuad]>;
794 // Floating-point Multiply and Divide Instructions, p. 147
795 def FMULS : F3_3<2, 0b110100, 0b001001001,
796 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
797 "fmuls $src1, $src2, $dst",
798 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
799 def FMULD : F3_3<2, 0b110100, 0b001001010,
800 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
801 "fmuld $src1, $src2, $dst",
802 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
803 def FMULQ : F3_3<2, 0b110100, 0b001001011,
804 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
805 "fmulq $src1, $src2, $dst",
806 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>,
807 Requires<[HasHardQuad]>;
809 def FSMULD : F3_3<2, 0b110100, 0b001101001,
810 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
811 "fsmuld $src1, $src2, $dst",
812 [(set f64:$dst, (fmul (fextend f32:$src1),
813 (fextend f32:$src2)))]>;
814 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
815 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
816 "fdmulq $src1, $src2, $dst",
817 [(set f128:$dst, (fmul (fextend f64:$src1),
818 (fextend f64:$src2)))]>,
819 Requires<[HasHardQuad]>;
821 def FDIVS : F3_3<2, 0b110100, 0b001001101,
822 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
823 "fdivs $src1, $src2, $dst",
824 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
825 def FDIVD : F3_3<2, 0b110100, 0b001001110,
826 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
827 "fdivd $src1, $src2, $dst",
828 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
829 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
830 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
831 "fdivq $src1, $src2, $dst",
832 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>,
833 Requires<[HasHardQuad]>;
835 // Floating-point Compare Instructions, p. 148
836 // Note: the 2nd template arg is different for these guys.
837 // Note 2: the result of a FCMP is not available until the 2nd cycle
838 // after the instr is retired, but there is no interlock in Sparc V8.
839 // This behavior is modeled with a forced noop after the instruction in
842 let Defs = [FCC] in {
843 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
844 (outs), (ins FPRegs:$src1, FPRegs:$src2),
845 "fcmps $src1, $src2",
846 [(SPcmpfcc f32:$src1, f32:$src2)]>;
847 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
848 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
849 "fcmpd $src1, $src2",
850 [(SPcmpfcc f64:$src1, f64:$src2)]>;
851 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
852 (outs), (ins QFPRegs:$src1, QFPRegs:$src2),
853 "fcmpq $src1, $src2",
854 [(SPcmpfcc f128:$src1, f128:$src2)]>,
855 Requires<[HasHardQuad]>;
858 //===----------------------------------------------------------------------===//
859 // Instructions for Thread Local Storage(TLS).
860 //===----------------------------------------------------------------------===//
862 def TLS_ADDrr : F3_1<2, 0b000000,
864 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
865 "add $rs1, $rs2, $rd, $sym",
867 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
870 def TLS_LDrr : F3_1<3, 0b000000,
871 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
872 "ld [$addr], $dst, $sym",
874 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
876 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
877 def TLS_CALL : InstSP<(outs),
878 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
880 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
883 let Inst{29-0} = disp;
886 //===----------------------------------------------------------------------===//
888 //===----------------------------------------------------------------------===//
890 // V9 Conditional Moves.
891 let Predicates = [HasV9], Constraints = "$f = $rd" in {
892 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
893 let Uses = [ICC], cc = 0b100 in {
895 : F4_1<0b101100, (outs IntRegs:$rd),
896 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
897 "mov$cond %icc, $rs2, $rd",
898 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
901 : F4_2<0b101100, (outs IntRegs:$rd),
902 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
903 "mov$cond %icc, $simm11, $rd",
905 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
908 let Uses = [FCC], cc = 0b000 in {
910 : F4_1<0b101100, (outs IntRegs:$rd),
911 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
912 "mov$cond %fcc0, $rs2, $rd",
913 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
915 : F4_2<0b101100, (outs IntRegs:$rd),
916 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
917 "mov$cond %fcc0, $simm11, $rd",
919 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
922 let Uses = [ICC], opf_cc = 0b100 in {
924 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
925 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
926 "fmovs$cond %icc, $rs2, $rd",
927 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
929 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
930 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
931 "fmovd$cond %icc, $rs2, $rd",
932 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
934 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
935 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
936 "fmovd$cond %icc, $rs2, $rd",
937 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
940 let Uses = [FCC], opf_cc = 0b000 in {
942 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
943 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
944 "fmovs$cond %fcc0, $rs2, $rd",
945 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
947 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
948 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
949 "fmovd$cond %fcc0, $rs2, $rd",
950 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
952 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
953 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
954 "fmovd$cond %fcc0, $rs2, $rd",
955 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
960 // Floating-Point Move Instructions, p. 164 of the V9 manual.
961 let Predicates = [HasV9] in {
962 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
963 (outs DFPRegs:$dst), (ins DFPRegs:$src),
964 "fmovd $src, $dst", []>;
965 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
966 (outs QFPRegs:$dst), (ins QFPRegs:$src),
967 "fmovq $src, $dst", []>,
968 Requires<[HasHardQuad]>;
969 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
970 (outs DFPRegs:$dst), (ins DFPRegs:$src),
972 [(set f64:$dst, (fneg f64:$src))]>;
973 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
974 (outs QFPRegs:$dst), (ins QFPRegs:$src),
976 [(set f128:$dst, (fneg f128:$src))]>,
977 Requires<[HasHardQuad]>;
978 def FABSD : F3_3u<2, 0b110100, 0b000001010,
979 (outs DFPRegs:$dst), (ins DFPRegs:$src),
981 [(set f64:$dst, (fabs f64:$src))]>;
982 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
983 (outs QFPRegs:$dst), (ins QFPRegs:$src),
985 [(set f128:$dst, (fabs f128:$src))]>,
986 Requires<[HasHardQuad]>;
989 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
990 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
992 def POPCrr : F3_1<2, 0b101110,
993 (outs IntRegs:$dst), (ins IntRegs:$src),
994 "popc $src, $dst", []>, Requires<[HasV9]>;
995 def : Pat<(ctpop i32:$src),
996 (POPCrr (SRLri $src, 0))>;
999 let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
1000 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
1002 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1003 def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
1004 "membar $simm13", []>;
1006 let Constraints = "$val = $rd" in {
1007 def SWAPrr : F3_1<3, 0b001111,
1008 (outs IntRegs:$rd), (ins IntRegs:$val, MEMrr:$addr),
1009 "swap [$addr], $rd",
1010 [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
1011 def SWAPri : F3_2<3, 0b001111,
1012 (outs IntRegs:$rd), (ins IntRegs:$val, MEMri:$addr),
1013 "swap [$addr], $rd",
1014 [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
1017 let Predicates = [HasV9], Constraints = "$swap = $rd" in
1018 def CASrr: F3_1<3, 0b111100,
1019 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1021 "cas [$rs1], $rs2, $rd",
1023 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1025 //===----------------------------------------------------------------------===//
1026 // Non-Instruction Patterns
1027 //===----------------------------------------------------------------------===//
1029 // Small immediates.
1030 def : Pat<(i32 simm13:$val),
1031 (ORri (i32 G0), imm:$val)>;
1032 // Arbitrary immediates.
1033 def : Pat<(i32 imm:$val),
1034 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1037 // Global addresses, constant pool entries
1038 let Predicates = [Is32Bit] in {
1040 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1041 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1042 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1043 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1045 // GlobalTLS addresses
1046 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1047 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1048 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1049 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1050 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1051 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1054 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1055 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1057 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1058 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1059 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1060 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1061 (ADDri $r, tblockaddress:$in)>;
1065 def : Pat<(call tglobaladdr:$dst),
1066 (CALL tglobaladdr:$dst)>;
1067 def : Pat<(call texternalsym:$dst),
1068 (CALL texternalsym:$dst)>;
1070 // Map integer extload's to zextloads.
1071 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1072 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1073 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1074 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1075 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1076 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1078 // zextload bool -> zextload byte
1079 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1080 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1082 // store 0, addr -> store %g0, addr
1083 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1084 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1086 // store bar for all atomic_fence in V8.
1087 let Predicates = [HasNoV9] in
1088 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1090 // atomic_load_32 addr -> load addr
1091 def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1092 def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1094 // atomic_store_32 val, addr -> store val, addr
1095 def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1096 def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1099 include "SparcInstr64Bit.td"