1 //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
25 #define GET_INSTRINFO_CTOR
26 #define GET_INSTRINFO_MC_DESC
27 #include "SparcGenInstrInfo.inc"
31 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
32 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
33 RI(ST, *this), Subtarget(ST) {
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot. If
39 /// not, return 0. This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
41 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
42 int &FrameIndex) const {
43 if (MI->getOpcode() == SP::LDri ||
44 MI->getOpcode() == SP::LDFri ||
45 MI->getOpcode() == SP::LDDFri) {
46 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
47 MI->getOperand(2).getImm() == 0) {
48 FrameIndex = MI->getOperand(1).getIndex();
49 return MI->getOperand(0).getReg();
55 /// isStoreToStackSlot - If the specified machine instruction is a direct
56 /// store to a stack slot, return the virtual or physical register number of
57 /// the source reg along with the FrameIndex of the loaded stack slot. If
58 /// not, return 0. This predicate must return 0 if the instruction has
59 /// any side effects other than storing to the stack slot.
60 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
61 int &FrameIndex) const {
62 if (MI->getOpcode() == SP::STri ||
63 MI->getOpcode() == SP::STFri ||
64 MI->getOpcode() == SP::STDFri) {
65 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
66 MI->getOperand(1).getImm() == 0) {
67 FrameIndex = MI->getOperand(0).getIndex();
68 return MI->getOperand(2).getReg();
74 static bool IsIntegerCC(unsigned CC)
76 return (CC <= SPCC::ICC_VC);
80 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
83 default: llvm_unreachable("Unknown condition code");
84 case SPCC::ICC_NE: return SPCC::ICC_E;
85 case SPCC::ICC_E: return SPCC::ICC_NE;
86 case SPCC::ICC_G: return SPCC::ICC_LE;
87 case SPCC::ICC_LE: return SPCC::ICC_G;
88 case SPCC::ICC_GE: return SPCC::ICC_L;
89 case SPCC::ICC_L: return SPCC::ICC_GE;
90 case SPCC::ICC_GU: return SPCC::ICC_LEU;
91 case SPCC::ICC_LEU: return SPCC::ICC_GU;
92 case SPCC::ICC_CC: return SPCC::ICC_CS;
93 case SPCC::ICC_CS: return SPCC::ICC_CC;
94 case SPCC::ICC_POS: return SPCC::ICC_NEG;
95 case SPCC::ICC_NEG: return SPCC::ICC_POS;
96 case SPCC::ICC_VC: return SPCC::ICC_VS;
97 case SPCC::ICC_VS: return SPCC::ICC_VC;
99 case SPCC::FCC_U: return SPCC::FCC_O;
100 case SPCC::FCC_O: return SPCC::FCC_U;
101 case SPCC::FCC_G: return SPCC::FCC_LE;
102 case SPCC::FCC_LE: return SPCC::FCC_G;
103 case SPCC::FCC_UG: return SPCC::FCC_ULE;
104 case SPCC::FCC_ULE: return SPCC::FCC_UG;
105 case SPCC::FCC_L: return SPCC::FCC_GE;
106 case SPCC::FCC_GE: return SPCC::FCC_L;
107 case SPCC::FCC_UL: return SPCC::FCC_UGE;
108 case SPCC::FCC_UGE: return SPCC::FCC_UL;
109 case SPCC::FCC_LG: return SPCC::FCC_UE;
110 case SPCC::FCC_UE: return SPCC::FCC_LG;
111 case SPCC::FCC_NE: return SPCC::FCC_E;
112 case SPCC::FCC_E: return SPCC::FCC_NE;
117 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
118 MachineBasicBlock *&TBB,
119 MachineBasicBlock *&FBB,
120 SmallVectorImpl<MachineOperand> &Cond,
121 bool AllowModify) const
124 MachineBasicBlock::iterator I = MBB.end();
125 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
126 while (I != MBB.begin()) {
129 if (I->isDebugValue())
132 //When we see a non-terminator, we are done
133 if (!isUnpredicatedTerminator(I))
136 //Terminator is not a branch
137 if (!I->getDesc().isBranch())
140 //Handle Unconditional branches
141 if (I->getOpcode() == SP::BA) {
145 TBB = I->getOperand(0).getMBB();
149 while (llvm::next(I) != MBB.end())
150 llvm::next(I)->eraseFromParent();
155 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
157 I->eraseFromParent();
159 UnCondBrIter = MBB.end();
163 TBB = I->getOperand(0).getMBB();
167 unsigned Opcode = I->getOpcode();
168 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
169 return true; //Unknown Opcode
171 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
174 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
175 if (AllowModify && UnCondBrIter != MBB.end() &&
176 MBB.isLayoutSuccessor(TargetBB)) {
193 BranchCode = GetOppositeBranchCondition(BranchCode);
194 MachineBasicBlock::iterator OldInst = I;
195 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
196 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
197 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
199 MBB.addSuccessor(TargetBB);
200 OldInst->eraseFromParent();
201 UnCondBrIter->eraseFromParent();
203 UnCondBrIter = MBB.end();
208 TBB = I->getOperand(0).getMBB();
209 Cond.push_back(MachineOperand::CreateImm(BranchCode));
212 //FIXME: Handle subsequent conditional branches
213 //For now, we can't handle multiple conditional branches
220 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
221 MachineBasicBlock *FBB,
222 const SmallVectorImpl<MachineOperand> &Cond,
224 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
225 assert((Cond.size() == 1 || Cond.size() == 0) &&
226 "Sparc branch conditions should have one component!");
229 assert(!FBB && "Unconditional branch with multiple successors!");
230 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
235 unsigned CC = Cond[0].getImm();
238 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
240 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
244 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
248 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
250 MachineBasicBlock::iterator I = MBB.end();
252 while (I != MBB.begin()) {
255 if (I->isDebugValue())
258 if (I->getOpcode() != SP::BA
259 && I->getOpcode() != SP::BCOND
260 && I->getOpcode() != SP::FBCOND)
261 break; // Not a branch
263 I->eraseFromParent();
270 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
271 MachineBasicBlock::iterator I, DebugLoc DL,
272 unsigned DestReg, unsigned SrcReg,
273 bool KillSrc) const {
274 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
275 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
276 .addReg(SrcReg, getKillRegState(KillSrc));
277 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
278 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
279 .addReg(SrcReg, getKillRegState(KillSrc));
280 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
281 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
282 .addReg(SrcReg, getKillRegState(KillSrc));
284 llvm_unreachable("Impossible reg-to-reg copy");
287 void SparcInstrInfo::
288 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
289 unsigned SrcReg, bool isKill, int FI,
290 const TargetRegisterClass *RC,
291 const TargetRegisterInfo *TRI) const {
293 if (I != MBB.end()) DL = I->getDebugLoc();
295 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
296 if (RC == SP::IntRegsRegisterClass)
297 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
298 .addReg(SrcReg, getKillRegState(isKill));
299 else if (RC == SP::FPRegsRegisterClass)
300 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
301 .addReg(SrcReg, getKillRegState(isKill));
302 else if (RC == SP::DFPRegsRegisterClass)
303 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
304 .addReg(SrcReg, getKillRegState(isKill));
306 llvm_unreachable("Can't store this register to stack slot");
309 void SparcInstrInfo::
310 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
311 unsigned DestReg, int FI,
312 const TargetRegisterClass *RC,
313 const TargetRegisterInfo *TRI) const {
315 if (I != MBB.end()) DL = I->getDebugLoc();
317 if (RC == SP::IntRegsRegisterClass)
318 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
319 else if (RC == SP::FPRegsRegisterClass)
320 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
321 else if (RC == SP::DFPRegsRegisterClass)
322 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
324 llvm_unreachable("Can't load this register from stack slot");
327 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
329 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
330 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
331 if (GlobalBaseReg != 0)
332 return GlobalBaseReg;
334 // Insert the set of GlobalBaseReg into the first MBB of the function
335 MachineBasicBlock &FirstMBB = MF->front();
336 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
337 MachineRegisterInfo &RegInfo = MF->getRegInfo();
339 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
344 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
345 SparcFI->setGlobalBaseReg(GlobalBaseReg);
346 return GlobalBaseReg;
349 MCInstrInfo *createSparcMCInstrInfo() {
350 MCInstrInfo *X = new MCInstrInfo();
351 InitSparcMCInstrInfo(X);
355 extern "C" void LLVMInitializeSparcMCInstrInfo() {
356 TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo);