lib/Target/Sparc/SparcISelLowering.h

   1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef SPARC_ISELLOWERING_H
  16 #define SPARC_ISELLOWERING_H
  17
  18 #include "Sparc.h"
  19 #include "llvm/Target/TargetLowering.h"
  20
  21 namespace llvm {
  22   class SparcSubtarget;
  23
  24   namespace SPISD {
  25     enum {
  26       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  27       CMPICC,      // Compare two GPR operands, set icc+xcc.
  28       CMPFCC,      // Compare two FP operands, set fcc.
  29       BRICC,       // Branch to dest on icc condition
  30       BRXCC,       // Branch to dest on xcc condition (64-bit only).
  31       BRFCC,       // Branch to dest on fcc condition
  32       SELECT_ICC,  // Select between two values using the current ICC flags.
  33       SELECT_FCC,  // Select between two values using the current FCC flags.
  34
  35       Hi, Lo,      // Hi/Lo operations, typically on a global address.
  36
  37       FTOI,        // FP to Int within a FP register.
  38       ITOF,        // Int to FP within a FP register.
  39
  40       CALL,        // A call instruction.
  41       RET_FLAG,    // Return with a flag operand.
  42       GLOBAL_BASE_REG, // Global base reg for PIC
  43       FLUSHW       // FLUSH register windows to stack
  44     };
  45   }
  46
  47   class SparcTargetLowering : public TargetLowering {
  48     const SparcSubtarget *Subtarget;
  49   public:
  50     SparcTargetLowering(TargetMachine &TM);
  51     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  52
  53     /// computeMaskedBitsForTargetNode - Determine which of the bits specified
  54     /// in Mask are known to be either zero or one and return them in the
  55     /// KnownZero/KnownOne bitsets.
  56     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
  57                                                 APInt &KnownZero,
  58                                                 APInt &KnownOne,
  59                                                 const SelectionDAG &DAG,
  60                                                 unsigned Depth = 0) const;
  61
  62     virtual MachineBasicBlock *
  63       EmitInstrWithCustomInserter(MachineInstr *MI,
  64                                   MachineBasicBlock *MBB) const;
  65
  66     virtual const char *getTargetNodeName(unsigned Opcode) const;
  67
  68     ConstraintType getConstraintType(const std::string &Constraint) const;
  69     std::pair<unsigned, const TargetRegisterClass*>
  70     getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
  71
  72     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
  73
  74     virtual SDValue
  75       LowerFormalArguments(SDValue Chain,
  76                            CallingConv::ID CallConv,
  77                            bool isVarArg,
  78                            const SmallVectorImpl<ISD::InputArg> &Ins,
  79                            DebugLoc dl, SelectionDAG &DAG,
  80                            SmallVectorImpl<SDValue> &InVals) const;
  81     SDValue LowerFormalArguments_32(SDValue Chain,
  82                                     CallingConv::ID CallConv,
  83                                     bool isVarArg,
  84                                     const SmallVectorImpl<ISD::InputArg> &Ins,
  85                                     DebugLoc dl, SelectionDAG &DAG,
  86                                     SmallVectorImpl<SDValue> &InVals) const;
  87     SDValue LowerFormalArguments_64(SDValue Chain,
  88                                     CallingConv::ID CallConv,
  89                                     bool isVarArg,
  90                                     const SmallVectorImpl<ISD::InputArg> &Ins,
  91                                     DebugLoc dl, SelectionDAG &DAG,
  92                                     SmallVectorImpl<SDValue> &InVals) const;
  93
  94     virtual SDValue
  95       LowerCall(TargetLowering::CallLoweringInfo &CLI,
  96                 SmallVectorImpl<SDValue> &InVals) const;
  97
  98     virtual SDValue
  99       LowerReturn(SDValue Chain,
 100                   CallingConv::ID CallConv, bool isVarArg,
 101                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 102                   const SmallVectorImpl<SDValue> &OutVals,
 103                   DebugLoc dl, SelectionDAG &DAG) const;
 104
 105     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 106     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 107
 108     unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
 109   };
 110 } // end namespace llvm
 111
 112 #endif    // SPARC_ISELLOWERING_H