1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcFrameLowering.h"
15 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Target/TargetOptions.h"
31 DisableLeafProc("disable-sparc-leaf-proc",
33 cl::desc("Disable Sparc leaf procedure optimization."),
36 SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
37 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
38 ST.is64Bit() ? 16 : 8, 0, ST.is64Bit() ? 16 : 8) {}
40 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
41 MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MBBI,
45 unsigned ADDri) const {
47 DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
48 const SparcInstrInfo &TII =
49 *static_cast<const SparcInstrInfo *>(
50 MF.getTarget().getSubtargetImpl()->getInstrInfo());
52 if (NumBytes >= -4096 && NumBytes < 4096) {
53 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
54 .addReg(SP::O6).addImm(NumBytes);
58 // Emit this the hard way. This clobbers G1 which we always know is
61 // Emit nonnegative numbers with sethi + or.
62 // sethi %hi(NumBytes), %g1
63 // or %g1, %lo(NumBytes), %g1
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 .addImm(HI22(NumBytes));
67 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
68 .addReg(SP::G1).addImm(LO10(NumBytes));
69 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
70 .addReg(SP::O6).addReg(SP::G1);
74 // Emit negative numbers with sethi + xor.
75 // sethi %hix(NumBytes), %g1
76 // xor %g1, %lox(NumBytes), %g1
78 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 .addImm(HIX22(NumBytes));
80 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
81 .addReg(SP::G1).addImm(LOX10(NumBytes));
82 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
83 .addReg(SP::O6).addReg(SP::G1);
86 void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
87 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
89 MachineBasicBlock &MBB = MF.front();
90 MachineFrameInfo *MFI = MF.getFrameInfo();
91 const SparcInstrInfo &TII =
92 *static_cast<const SparcInstrInfo *>(
93 MF.getTarget().getSubtargetImpl()->getInstrInfo());
94 MachineBasicBlock::iterator MBBI = MBB.begin();
95 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
97 // Get the number of bytes to allocate from the FrameInfo
98 int NumBytes = (int) MFI->getStackSize();
100 unsigned SAVEri = SP::SAVEri;
101 unsigned SAVErr = SP::SAVErr;
102 if (FuncInfo->isLeafProc()) {
109 -MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize(
111 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);
113 MachineModuleInfo &MMI = MF.getMMI();
114 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
115 unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
117 // Emit ".cfi_def_cfa_register 30".
119 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
120 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
121 .addCFIIndex(CFIIndex);
123 // Emit ".cfi_window_save".
124 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
125 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
126 .addCFIIndex(CFIIndex);
128 unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
129 unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
130 // Emit ".cfi_register 15, 31".
131 CFIIndex = MMI.addFrameInst(
132 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
133 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
134 .addCFIIndex(CFIIndex);
137 void SparcFrameLowering::
138 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
139 MachineBasicBlock::iterator I) const {
140 if (!hasReservedCallFrame(MF)) {
141 MachineInstr &MI = *I;
142 int Size = MI.getOperand(0).getImm();
143 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
147 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
153 void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
154 MachineBasicBlock &MBB) const {
155 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
156 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
157 const SparcInstrInfo &TII =
158 *static_cast<const SparcInstrInfo *>(
159 MF.getTarget().getSubtargetImpl()->getInstrInfo());
160 DebugLoc dl = MBBI->getDebugLoc();
161 assert(MBBI->getOpcode() == SP::RETL &&
162 "Can only put epilog before 'retl' instruction!");
163 if (!FuncInfo->isLeafProc()) {
164 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
168 MachineFrameInfo *MFI = MF.getFrameInfo();
170 int NumBytes = (int) MFI->getStackSize();
174 NumBytes = MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize(
176 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
179 bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
180 // Reserve call frame if there are no variable sized objects on the stack.
181 return !MF.getFrameInfo()->hasVarSizedObjects();
184 // hasFP - Return true if the specified function should have a dedicated frame
185 // pointer register. This is true if the function has variable sized allocas or
186 // if frame pointer elimination is disabled.
187 bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
188 const MachineFrameInfo *MFI = MF.getFrameInfo();
189 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
190 MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
194 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
197 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
198 if (MRI->isPhysRegUsed(reg))
201 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
202 if (MRI->isPhysRegUsed(reg))
208 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
211 MachineRegisterInfo &MRI = MF.getRegInfo();
212 MachineFrameInfo *MFI = MF.getFrameInfo();
214 return !(MFI->hasCalls() // has calls
215 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
216 || MRI.isPhysRegUsed(SP::O6) // %SP is used
217 || hasFP(MF)); // need %FP
220 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
222 MachineRegisterInfo &MRI = MF.getRegInfo();
224 // Remap %i[0-7] to %o[0-7].
225 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
226 if (!MRI.isPhysRegUsed(reg))
228 unsigned mapped_reg = (reg - SP::I0 + SP::O0);
229 assert(!MRI.isPhysRegUsed(mapped_reg));
231 // Replace I register with O register.
232 MRI.replaceRegWith(reg, mapped_reg);
234 // Mark the reg unused.
235 MRI.setPhysRegUnused(reg);
238 // Rewrite MBB's Live-ins.
239 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
241 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
242 if (!MBB->isLiveIn(reg))
244 MBB->removeLiveIn(reg);
245 MBB->addLiveIn(reg - SP::I0 + SP::O0);
249 assert(verifyLeafProcRegUse(&MRI));
251 MF.verify(0, "After LeafProc Remapping");
255 void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
256 (MachineFunction &MF, RegScavenger *RS) const {
258 if (!DisableLeafProc && isLeafProc(MF)) {
259 SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
260 MFI->setLeafProc(true);
262 remapRegsForLeafProc(MF);