1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Sparc Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/Support/MemoryObject.h"
20 #include "llvm/Support/TargetRegistry.h"
24 #define DEBUG_TYPE "sparc-disassembler"
26 typedef MCDisassembler::DecodeStatus DecodeStatus;
30 /// A disassembler class for Sparc.
31 class SparcDisassembler : public MCDisassembler {
33 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
34 : MCDisassembler(STI, Ctx) {}
35 virtual ~SparcDisassembler() {}
37 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
38 const MemoryObject &Region, uint64_t Address,
40 raw_ostream &CStream) const override;
46 extern Target TheSparcTarget, TheSparcV9Target;
49 static MCDisassembler *createSparcDisassembler(
51 const MCSubtargetInfo &STI,
53 return new SparcDisassembler(STI, Ctx);
57 extern "C" void LLVMInitializeSparcDisassembler() {
58 // Register the disassembler.
59 TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
60 createSparcDisassembler);
61 TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
62 createSparcDisassembler);
67 static const unsigned IntRegDecoderTable[] = {
68 SP::G0, SP::G1, SP::G2, SP::G3,
69 SP::G4, SP::G5, SP::G6, SP::G7,
70 SP::O0, SP::O1, SP::O2, SP::O3,
71 SP::O4, SP::O5, SP::O6, SP::O7,
72 SP::L0, SP::L1, SP::L2, SP::L3,
73 SP::L4, SP::L5, SP::L6, SP::L7,
74 SP::I0, SP::I1, SP::I2, SP::I3,
75 SP::I4, SP::I5, SP::I6, SP::I7 };
77 static const unsigned FPRegDecoderTable[] = {
78 SP::F0, SP::F1, SP::F2, SP::F3,
79 SP::F4, SP::F5, SP::F6, SP::F7,
80 SP::F8, SP::F9, SP::F10, SP::F11,
81 SP::F12, SP::F13, SP::F14, SP::F15,
82 SP::F16, SP::F17, SP::F18, SP::F19,
83 SP::F20, SP::F21, SP::F22, SP::F23,
84 SP::F24, SP::F25, SP::F26, SP::F27,
85 SP::F28, SP::F29, SP::F30, SP::F31 };
87 static const unsigned DFPRegDecoderTable[] = {
88 SP::D0, SP::D16, SP::D1, SP::D17,
89 SP::D2, SP::D18, SP::D3, SP::D19,
90 SP::D4, SP::D20, SP::D5, SP::D21,
91 SP::D6, SP::D22, SP::D7, SP::D23,
92 SP::D8, SP::D24, SP::D9, SP::D25,
93 SP::D10, SP::D26, SP::D11, SP::D27,
94 SP::D12, SP::D28, SP::D13, SP::D29,
95 SP::D14, SP::D30, SP::D15, SP::D31 };
97 static const unsigned QFPRegDecoderTable[] = {
98 SP::Q0, SP::Q8, ~0U, ~0U,
99 SP::Q1, SP::Q9, ~0U, ~0U,
100 SP::Q2, SP::Q10, ~0U, ~0U,
101 SP::Q3, SP::Q11, ~0U, ~0U,
102 SP::Q4, SP::Q12, ~0U, ~0U,
103 SP::Q5, SP::Q13, ~0U, ~0U,
104 SP::Q6, SP::Q14, ~0U, ~0U,
105 SP::Q7, SP::Q15, ~0U, ~0U } ;
107 static const unsigned FCCRegDecoderTable[] = {
108 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
110 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
113 const void *Decoder) {
115 return MCDisassembler::Fail;
116 unsigned Reg = IntRegDecoderTable[RegNo];
117 Inst.addOperand(MCOperand::CreateReg(Reg));
118 return MCDisassembler::Success;
121 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
124 const void *Decoder) {
126 return MCDisassembler::Fail;
127 unsigned Reg = IntRegDecoderTable[RegNo];
128 Inst.addOperand(MCOperand::CreateReg(Reg));
129 return MCDisassembler::Success;
133 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
136 const void *Decoder) {
138 return MCDisassembler::Fail;
139 unsigned Reg = FPRegDecoderTable[RegNo];
140 Inst.addOperand(MCOperand::CreateReg(Reg));
141 return MCDisassembler::Success;
145 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
148 const void *Decoder) {
150 return MCDisassembler::Fail;
151 unsigned Reg = DFPRegDecoderTable[RegNo];
152 Inst.addOperand(MCOperand::CreateReg(Reg));
153 return MCDisassembler::Success;
157 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
160 const void *Decoder) {
162 return MCDisassembler::Fail;
164 unsigned Reg = QFPRegDecoderTable[RegNo];
166 return MCDisassembler::Fail;
167 Inst.addOperand(MCOperand::CreateReg(Reg));
168 return MCDisassembler::Success;
171 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
173 const void *Decoder) {
175 return MCDisassembler::Fail;
176 Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
177 return MCDisassembler::Success;
181 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
182 const void *Decoder);
183 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
184 const void *Decoder);
185 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
186 const void *Decoder);
187 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
188 const void *Decoder);
189 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
190 uint64_t Address, const void *Decoder);
191 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
192 uint64_t Address, const void *Decoder);
193 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
194 uint64_t Address, const void *Decoder);
195 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
196 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
202 const void *Decoder);
203 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
204 const void *Decoder);
205 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
206 const void *Decoder);
208 #include "SparcGenDisassemblerTables.inc"
210 /// Read four bytes from the MemoryObject and return 32 bit word.
211 static DecodeStatus readInstruction32(const MemoryObject &Region,
212 uint64_t Address, uint64_t &Size,
216 // We want to read exactly 4 Bytes of data.
217 if (Region.readBytes(Address, 4, Bytes) == -1) {
219 return MCDisassembler::Fail;
222 // Encoded as a big-endian 32-bit word in the stream.
224 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
226 return MCDisassembler::Success;
229 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
230 const MemoryObject &Region,
232 raw_ostream &VStream,
233 raw_ostream &CStream) const {
236 DecodeStatus Result = readInstruction32(Region, Address, Size, Insn);
237 if (Result == MCDisassembler::Fail)
238 return MCDisassembler::Fail;
241 // Calling the auto-generated decoder function.
243 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
245 if (Result != MCDisassembler::Fail) {
250 return MCDisassembler::Fail;
254 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
255 const void *Decoder);
257 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
259 bool isLoad, DecodeFunc DecodeRD) {
260 unsigned rd = fieldFromInstruction(insn, 25, 5);
261 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
262 bool isImm = fieldFromInstruction(insn, 13, 1);
266 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
268 rs2 = fieldFromInstruction(insn, 0, 5);
272 status = DecodeRD(MI, rd, Address, Decoder);
273 if (status != MCDisassembler::Success)
278 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
279 if (status != MCDisassembler::Success)
284 MI.addOperand(MCOperand::CreateImm(simm13));
286 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
287 if (status != MCDisassembler::Success)
292 status = DecodeRD(MI, rd, Address, Decoder);
293 if (status != MCDisassembler::Success)
296 return MCDisassembler::Success;
299 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
300 const void *Decoder) {
301 return DecodeMem(Inst, insn, Address, Decoder, true,
302 DecodeIntRegsRegisterClass);
305 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
306 const void *Decoder) {
307 return DecodeMem(Inst, insn, Address, Decoder, true,
308 DecodeFPRegsRegisterClass);
311 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
312 const void *Decoder) {
313 return DecodeMem(Inst, insn, Address, Decoder, true,
314 DecodeDFPRegsRegisterClass);
317 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
318 const void *Decoder) {
319 return DecodeMem(Inst, insn, Address, Decoder, true,
320 DecodeQFPRegsRegisterClass);
323 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
324 uint64_t Address, const void *Decoder) {
325 return DecodeMem(Inst, insn, Address, Decoder, false,
326 DecodeIntRegsRegisterClass);
329 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
330 const void *Decoder) {
331 return DecodeMem(Inst, insn, Address, Decoder, false,
332 DecodeFPRegsRegisterClass);
335 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
336 uint64_t Address, const void *Decoder) {
337 return DecodeMem(Inst, insn, Address, Decoder, false,
338 DecodeDFPRegsRegisterClass);
341 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
342 uint64_t Address, const void *Decoder) {
343 return DecodeMem(Inst, insn, Address, Decoder, false,
344 DecodeQFPRegsRegisterClass);
347 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
348 uint64_t Address, uint64_t Offset,
349 uint64_t Width, MCInst &MI,
350 const void *Decoder) {
351 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
352 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
356 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
357 uint64_t Address, const void *Decoder) {
358 unsigned tgt = fieldFromInstruction(insn, 0, 30);
360 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
362 MI.addOperand(MCOperand::CreateImm(tgt));
363 return MCDisassembler::Success;
366 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
367 uint64_t Address, const void *Decoder) {
368 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
369 MI.addOperand(MCOperand::CreateImm(tgt));
370 return MCDisassembler::Success;
373 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
374 const void *Decoder) {
376 unsigned rd = fieldFromInstruction(insn, 25, 5);
377 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
378 unsigned isImm = fieldFromInstruction(insn, 13, 1);
382 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
384 rs2 = fieldFromInstruction(insn, 0, 5);
387 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
388 if (status != MCDisassembler::Success)
392 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
393 if (status != MCDisassembler::Success)
396 // Decode RS1 | SIMM13.
398 MI.addOperand(MCOperand::CreateImm(simm13));
400 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
401 if (status != MCDisassembler::Success)
404 return MCDisassembler::Success;
407 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
408 const void *Decoder) {
410 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
411 unsigned isImm = fieldFromInstruction(insn, 13, 1);
415 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
417 rs2 = fieldFromInstruction(insn, 0, 5);
420 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
421 if (status != MCDisassembler::Success)
424 // Decode RS2 | SIMM13.
426 MI.addOperand(MCOperand::CreateImm(simm13));
428 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
429 if (status != MCDisassembler::Success)
432 return MCDisassembler::Success;
435 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
436 const void *Decoder) {
438 unsigned rd = fieldFromInstruction(insn, 25, 5);
439 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
440 unsigned isImm = fieldFromInstruction(insn, 13, 1);
444 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
446 rs2 = fieldFromInstruction(insn, 0, 5);
449 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
450 if (status != MCDisassembler::Success)
454 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
455 if (status != MCDisassembler::Success)
458 // Decode RS1 | SIMM13.
460 MI.addOperand(MCOperand::CreateImm(simm13));
462 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
463 if (status != MCDisassembler::Success)
466 return MCDisassembler::Success;