1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCTargetAsmParser.h"
19 #include "llvm/Support/TargetRegistry.h"
23 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
24 // namespace. But SPARC backend uses "SP" as its namespace.
33 class SparcAsmParser : public MCTargetAsmParser {
38 /// @name Auto-generated Match Functions
41 #define GET_ASSEMBLER_HEADER
42 #include "SparcGenAsmMatcher.inc"
46 // public interface of the MCTargetAsmParser.
47 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
48 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
49 MCStreamer &Out, unsigned &ErrorInfo,
50 bool MatchingInlineAsm);
51 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
52 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
54 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
55 bool ParseDirective(AsmToken DirectiveID);
57 virtual unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
60 // Custom parse functions for Sparc specific operands.
62 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
65 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
69 parseSparcAsmOperand(SparcOperand *&Operand);
71 // returns true if Tok is matched to a register and returns register in RegNo.
72 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
75 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
76 bool parseDirectiveWord(unsigned Size, SMLoc L);
78 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
80 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
81 const MCInstrInfo &MII)
82 : MCTargetAsmParser(), STI(sti), Parser(parser) {
83 // Initialize the set of available features.
84 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
89 static unsigned IntRegs[32] = {
90 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
91 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
92 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
93 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
94 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
95 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
96 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
97 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
99 static unsigned FloatRegs[32] = {
100 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
101 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
102 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
103 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
104 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
105 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
106 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
107 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
109 static unsigned DoubleRegs[32] = {
110 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
111 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
112 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
113 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
114 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
115 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
116 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
117 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
119 static unsigned QuadFPRegs[32] = {
120 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
121 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
122 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
123 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
126 /// SparcOperand - Instances of this class represent a parsed Sparc machine
128 class SparcOperand : public MCParsedAsmOperand {
148 SMLoc StartLoc, EndLoc;
150 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
179 bool isToken() const { return Kind == k_Token; }
180 bool isReg() const { return Kind == k_Register; }
181 bool isImm() const { return Kind == k_Immediate; }
182 bool isMem() const { return isMEMrr() || isMEMri(); }
183 bool isMEMrr() const { return Kind == k_MemoryReg; }
184 bool isMEMri() const { return Kind == k_MemoryImm; }
186 bool isFloatReg() const {
187 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
190 bool isFloatOrDoubleReg() const {
191 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
192 || Reg.Kind == rk_DoubleReg));
196 StringRef getToken() const {
197 assert(Kind == k_Token && "Invalid access!");
198 return StringRef(Tok.Data, Tok.Length);
201 unsigned getReg() const {
202 assert((Kind == k_Register) && "Invalid access!");
206 const MCExpr *getImm() const {
207 assert((Kind == k_Immediate) && "Invalid access!");
211 unsigned getMemBase() const {
212 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
216 unsigned getMemOffsetReg() const {
217 assert((Kind == k_MemoryReg) && "Invalid access!");
218 return Mem.OffsetReg;
221 const MCExpr *getMemOff() const {
222 assert((Kind == k_MemoryImm) && "Invalid access!");
226 /// getStartLoc - Get the location of the first token of this operand.
227 SMLoc getStartLoc() const {
230 /// getEndLoc - Get the location of the last token of this operand.
231 SMLoc getEndLoc() const {
235 virtual void print(raw_ostream &OS) const {
237 case k_Token: OS << "Token: " << getToken() << "\n"; break;
238 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
239 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
240 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
241 << getMemOffsetReg() << "\n"; break;
242 case k_MemoryImm: assert(getMemOff() != 0);
243 OS << "Mem: " << getMemBase()
244 << "+" << *getMemOff()
249 void addRegOperands(MCInst &Inst, unsigned N) const {
250 assert(N == 1 && "Invalid number of operands!");
251 Inst.addOperand(MCOperand::CreateReg(getReg()));
254 void addImmOperands(MCInst &Inst, unsigned N) const {
255 assert(N == 1 && "Invalid number of operands!");
256 const MCExpr *Expr = getImm();
260 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
261 // Add as immediate when possible. Null MCExpr = 0.
263 Inst.addOperand(MCOperand::CreateImm(0));
264 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
265 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
267 Inst.addOperand(MCOperand::CreateExpr(Expr));
270 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
271 assert(N == 2 && "Invalid number of operands!");
273 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
275 assert(getMemOffsetReg() != 0 && "Invalid offset");
276 Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
279 void addMEMriOperands(MCInst &Inst, unsigned N) const {
280 assert(N == 2 && "Invalid number of operands!");
282 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
284 const MCExpr *Expr = getMemOff();
288 static SparcOperand *CreateToken(StringRef Str, SMLoc S) {
289 SparcOperand *Op = new SparcOperand(k_Token);
290 Op->Tok.Data = Str.data();
291 Op->Tok.Length = Str.size();
297 static SparcOperand *CreateReg(unsigned RegNum,
300 SparcOperand *Op = new SparcOperand(k_Register);
301 Op->Reg.RegNum = RegNum;
302 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
308 static SparcOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
309 SparcOperand *Op = new SparcOperand(k_Immediate);
316 static SparcOperand *MorphToDoubleReg(SparcOperand *Op) {
317 unsigned Reg = Op->getReg();
318 assert(Op->Reg.Kind == rk_FloatReg);
319 unsigned regIdx = Reg - Sparc::F0;
320 if (regIdx % 2 || regIdx > 31)
322 Op->Reg.RegNum = DoubleRegs[regIdx / 2];
323 Op->Reg.Kind = rk_DoubleReg;
327 static SparcOperand *MorphToQuadReg(SparcOperand *Op) {
328 unsigned Reg = Op->getReg();
330 switch (Op->Reg.Kind) {
331 default: assert(0 && "Unexpected register kind!");
333 regIdx = Reg - Sparc::F0;
334 if (regIdx % 4 || regIdx > 31)
336 Reg = QuadFPRegs[regIdx / 4];
339 regIdx = Reg - Sparc::D0;
340 if (regIdx % 2 || regIdx > 31)
342 Reg = QuadFPRegs[regIdx / 2];
345 Op->Reg.RegNum = Reg;
346 Op->Reg.Kind = rk_QuadReg;
350 static SparcOperand *MorphToMEMrr(unsigned Base, SparcOperand *Op) {
351 unsigned offsetReg = Op->getReg();
352 Op->Kind = k_MemoryReg;
354 Op->Mem.OffsetReg = offsetReg;
359 static SparcOperand *CreateMEMri(unsigned Base,
362 SparcOperand *Op = new SparcOperand(k_MemoryImm);
364 Op->Mem.OffsetReg = 0;
371 static SparcOperand *MorphToMEMri(unsigned Base, SparcOperand *Op) {
372 const MCExpr *Imm = Op->getImm();
373 Op->Kind = k_MemoryImm;
375 Op->Mem.OffsetReg = 0;
383 bool SparcAsmParser::
384 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
385 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
386 MCStreamer &Out, unsigned &ErrorInfo,
387 bool MatchingInlineAsm) {
389 SmallVector<MCInst, 8> Instructions;
390 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
392 switch (MatchResult) {
396 case Match_Success: {
398 Out.EmitInstruction(Inst, STI);
402 case Match_MissingFeature:
404 "instruction requires a CPU feature not currently enabled");
406 case Match_InvalidOperand: {
407 SMLoc ErrorLoc = IDLoc;
408 if (ErrorInfo != ~0U) {
409 if (ErrorInfo >= Operands.size())
410 return Error(IDLoc, "too few operands for instruction");
412 ErrorLoc = ((SparcOperand*) Operands[ErrorInfo])->getStartLoc();
413 if (ErrorLoc == SMLoc())
417 return Error(ErrorLoc, "invalid operand for instruction");
419 case Match_MnemonicFail:
420 return Error(IDLoc, "invalid instruction");
425 bool SparcAsmParser::
426 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
428 const AsmToken &Tok = Parser.getTok();
429 StartLoc = Tok.getLoc();
430 EndLoc = Tok.getEndLoc();
432 if (getLexer().getKind() != AsmToken::Percent)
435 unsigned regKind = SparcOperand::rk_None;
436 if (matchRegisterName(Tok, RegNo, regKind)) {
441 return Error(StartLoc, "invalid register name");
444 bool SparcAsmParser::
445 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
447 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
449 // Check if we have valid mnemonic.
450 if (!mnemonicIsValid(Name, 0)) {
451 Parser.eatToEndOfStatement();
452 return Error(NameLoc, "Unknown instruction");
454 // First operand in MCInst is instruction mnemonic.
455 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
457 if (getLexer().isNot(AsmToken::EndOfStatement)) {
458 // Read the first operand.
459 if (parseOperand(Operands, Name) != MatchOperand_Success) {
460 SMLoc Loc = getLexer().getLoc();
461 Parser.eatToEndOfStatement();
462 return Error(Loc, "unexpected token");
465 while (getLexer().is(AsmToken::Comma)) {
466 Parser.Lex(); // Eat the comma.
467 // Parse and remember the operand.
468 if (parseOperand(Operands, Name) != MatchOperand_Success) {
469 SMLoc Loc = getLexer().getLoc();
470 Parser.eatToEndOfStatement();
471 return Error(Loc, "unexpected token");
475 if (getLexer().isNot(AsmToken::EndOfStatement)) {
476 SMLoc Loc = getLexer().getLoc();
477 Parser.eatToEndOfStatement();
478 return Error(Loc, "unexpected token");
480 Parser.Lex(); // Consume the EndOfStatement.
484 bool SparcAsmParser::
485 ParseDirective(AsmToken DirectiveID)
487 StringRef IDVal = DirectiveID.getString();
489 if (IDVal == ".byte")
490 return parseDirectiveWord(1, DirectiveID.getLoc());
492 if (IDVal == ".half")
493 return parseDirectiveWord(2, DirectiveID.getLoc());
495 if (IDVal == ".word")
496 return parseDirectiveWord(4, DirectiveID.getLoc());
498 if (IDVal == ".nword")
499 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
501 if (is64Bit() && IDVal == ".xword")
502 return parseDirectiveWord(8, DirectiveID.getLoc());
504 if (IDVal == ".register") {
505 // For now, ignore .register directive.
506 Parser.eatToEndOfStatement();
510 // Let the MC layer to handle other directives.
514 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
515 if (getLexer().isNot(AsmToken::EndOfStatement)) {
518 if (getParser().parseExpression(Value))
521 getParser().getStreamer().EmitValue(Value, Size);
523 if (getLexer().is(AsmToken::EndOfStatement))
526 // FIXME: Improve diagnostic.
527 if (getLexer().isNot(AsmToken::Comma))
528 return Error(L, "unexpected token in directive");
536 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
537 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
541 unsigned BaseReg = 0;
543 if (ParseRegister(BaseReg, S, E)) {
544 return MatchOperand_NoMatch;
547 switch (getLexer().getKind()) {
548 default: return MatchOperand_NoMatch;
550 case AsmToken::Comma:
551 case AsmToken::RBrac:
552 case AsmToken::EndOfStatement:
553 Operands.push_back(SparcOperand::CreateMEMri(BaseReg, 0, S, E));
554 return MatchOperand_Success;
556 case AsmToken:: Plus:
557 Parser.Lex(); // Eat the '+'
559 case AsmToken::Minus:
563 SparcOperand *Offset = 0;
564 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
565 if (ResTy != MatchOperand_Success || !Offset)
566 return MatchOperand_NoMatch;
568 Offset = (Offset->isImm()
569 ? SparcOperand::MorphToMEMri(BaseReg, Offset)
570 : SparcOperand::MorphToMEMrr(BaseReg, Offset));
572 Operands.push_back(Offset);
573 return MatchOperand_Success;
576 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
577 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
581 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
583 // If there wasn't a custom match, try the generic matcher below. Otherwise,
584 // there was a match, but an error occurred, in which case, just return that
585 // the operand parsing failed.
586 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
589 if (getLexer().is(AsmToken::LBrac)) {
591 Operands.push_back(SparcOperand::CreateToken("[",
592 Parser.getTok().getLoc()));
593 Parser.Lex(); // Eat the [
595 if (Mnemonic == "cas" || Mnemonic == "casx") {
596 SMLoc S = Parser.getTok().getLoc();
597 if (getLexer().getKind() != AsmToken::Percent)
598 return MatchOperand_NoMatch;
599 Parser.Lex(); // eat %
601 unsigned RegNo, RegKind;
602 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
603 return MatchOperand_NoMatch;
605 Parser.Lex(); // Eat the identifier token.
606 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
607 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
608 ResTy = MatchOperand_Success;
610 ResTy = parseMEMOperand(Operands);
613 if (ResTy != MatchOperand_Success)
616 if (!getLexer().is(AsmToken::RBrac))
617 return MatchOperand_ParseFail;
619 Operands.push_back(SparcOperand::CreateToken("]",
620 Parser.getTok().getLoc()));
621 Parser.Lex(); // Eat the ]
622 return MatchOperand_Success;
625 SparcOperand *Op = 0;
626 ResTy = parseSparcAsmOperand(Op);
627 if (ResTy != MatchOperand_Success || !Op)
628 return MatchOperand_ParseFail;
630 // Push the parsed operand into the list of operands
631 Operands.push_back(Op);
633 return MatchOperand_Success;
636 SparcAsmParser::OperandMatchResultTy
637 SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op)
640 SMLoc S = Parser.getTok().getLoc();
641 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
645 switch (getLexer().getKind()) {
648 case AsmToken::Percent:
649 Parser.Lex(); // Eat the '%'.
652 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
653 StringRef name = Parser.getTok().getString();
654 Parser.Lex(); // Eat the identifier token.
655 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
658 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
661 Op = SparcOperand::CreateToken("%y", S);
666 Op = SparcOperand::CreateToken("%xcc", S);
668 Op = SparcOperand::CreateToken("%icc", S);
672 assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
673 Op = SparcOperand::CreateToken("%fcc0", S);
678 if (matchSparcAsmModifiers(EVal, E)) {
679 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
680 Op = SparcOperand::CreateImm(EVal, S, E);
684 case AsmToken::Minus:
685 case AsmToken::Integer:
686 if (!getParser().parseExpression(EVal, E))
687 Op = SparcOperand::CreateImm(EVal, S, E);
690 case AsmToken::Identifier: {
691 StringRef Identifier;
692 if (!getParser().parseIdentifier(Identifier)) {
693 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
694 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
696 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
698 Op = SparcOperand::CreateImm(Res, S, E);
703 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
706 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
712 RegKind = SparcOperand::rk_None;
713 if (Tok.is(AsmToken::Identifier)) {
714 StringRef name = Tok.getString();
717 if (name.equals("fp")) {
719 RegKind = SparcOperand::rk_IntReg;
723 if (name.equals("sp")) {
725 RegKind = SparcOperand::rk_IntReg;
729 if (name.equals("y")) {
731 RegKind = SparcOperand::rk_Y;
735 if (name.equals("icc")) {
737 RegKind = SparcOperand::rk_CCReg;
741 if (name.equals("xcc")) {
742 // FIXME:: check 64bit.
744 RegKind = SparcOperand::rk_CCReg;
749 if (name.substr(0, 3).equals_lower("fcc")
750 && !name.substr(3).getAsInteger(10, intVal)
752 // FIXME: check 64bit and handle %fcc1 - %fcc3
754 RegKind = SparcOperand::rk_CCReg;
759 if (name.substr(0, 1).equals_lower("g")
760 && !name.substr(1).getAsInteger(10, intVal)
762 RegNo = IntRegs[intVal];
763 RegKind = SparcOperand::rk_IntReg;
767 if (name.substr(0, 1).equals_lower("o")
768 && !name.substr(1).getAsInteger(10, intVal)
770 RegNo = IntRegs[8 + intVal];
771 RegKind = SparcOperand::rk_IntReg;
774 if (name.substr(0, 1).equals_lower("l")
775 && !name.substr(1).getAsInteger(10, intVal)
777 RegNo = IntRegs[16 + intVal];
778 RegKind = SparcOperand::rk_IntReg;
781 if (name.substr(0, 1).equals_lower("i")
782 && !name.substr(1).getAsInteger(10, intVal)
784 RegNo = IntRegs[24 + intVal];
785 RegKind = SparcOperand::rk_IntReg;
789 if (name.substr(0, 1).equals_lower("f")
790 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
791 RegNo = FloatRegs[intVal];
792 RegKind = SparcOperand::rk_FloatReg;
796 if (name.substr(0, 1).equals_lower("f")
797 && !name.substr(1, 2).getAsInteger(10, intVal)
798 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
800 RegNo = DoubleRegs[intVal/2];
801 RegKind = SparcOperand::rk_DoubleReg;
806 if (name.substr(0, 1).equals_lower("r")
807 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
808 RegNo = IntRegs[intVal];
809 RegKind = SparcOperand::rk_IntReg;
817 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
820 AsmToken Tok = Parser.getTok();
821 if (!Tok.is(AsmToken::Identifier))
824 StringRef name = Tok.getString();
826 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
828 if (VK == SparcMCExpr::VK_Sparc_None)
831 Parser.Lex(); // Eat the identifier.
832 if (Parser.getTok().getKind() != AsmToken::LParen)
835 Parser.Lex(); // Eat the LParen token.
836 const MCExpr *subExpr;
837 if (Parser.parseParenExpression(subExpr, EndLoc))
839 EVal = SparcMCExpr::Create(VK, subExpr, getContext());
844 extern "C" void LLVMInitializeSparcAsmParser() {
845 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
846 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
849 #define GET_REGISTER_MATCHER
850 #define GET_MATCHER_IMPLEMENTATION
851 #include "SparcGenAsmMatcher.inc"
855 unsigned SparcAsmParser::
856 validateTargetOperandClass(MCParsedAsmOperand *GOp,
859 SparcOperand *Op = (SparcOperand*)GOp;
860 if (Op->isFloatOrDoubleReg()) {
864 if (!Op->isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
865 return MCTargetAsmParser::Match_Success;
868 if (SparcOperand::MorphToQuadReg(Op))
869 return MCTargetAsmParser::Match_Success;
873 return Match_InvalidOperand;