1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def gds : Operand <i1> {
268 let PrintMethod = "printGDS";
270 def glc : Operand <i1> {
271 let PrintMethod = "printGLC";
273 def slc : Operand <i1> {
274 let PrintMethod = "printSLC";
276 def tfe : Operand <i1> {
277 let PrintMethod = "printTFE";
280 def omod : Operand <i32> {
281 let PrintMethod = "printOModSI";
284 def ClampMod : Operand <i1> {
285 let PrintMethod = "printClampSI";
288 } // End OperandType = "OPERAND_IMMEDIATE"
290 def VOPDstS64 : VOPDstOperand <SReg_64>;
292 //===----------------------------------------------------------------------===//
294 //===----------------------------------------------------------------------===//
296 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
297 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
299 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
300 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
301 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
302 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
303 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
304 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
306 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
307 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
308 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
309 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
311 //===----------------------------------------------------------------------===//
312 // SI assembler operands
313 //===----------------------------------------------------------------------===//
333 //===----------------------------------------------------------------------===//
335 // SI Instruction multiclass helpers.
337 // Instructions with _32 take 32-bit operands.
338 // Instructions with _64 take 64-bit operands.
340 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
341 // encoding is the standard encoding, but instruction that make use of
342 // any of the instruction modifiers must use the 64-bit encoding.
344 // Instructions with _e32 use the 32-bit encoding.
345 // Instructions with _e64 use the 64-bit encoding.
347 //===----------------------------------------------------------------------===//
349 class SIMCInstr <string pseudo, int subtarget> {
350 string PseudoInstr = pseudo;
351 int Subtarget = subtarget;
354 //===----------------------------------------------------------------------===//
356 //===----------------------------------------------------------------------===//
358 class EXPCommon : InstSI<
360 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
361 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
362 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
371 let isPseudo = 1, isCodeGenOnly = 1 in {
372 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
375 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
377 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
380 //===----------------------------------------------------------------------===//
382 //===----------------------------------------------------------------------===//
384 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
385 SOP1 <outs, ins, "", pattern>,
386 SIMCInstr<opName, SISubtarget.NONE> {
388 let isCodeGenOnly = 1;
391 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
392 SOP1 <outs, ins, asm, []>,
394 SIMCInstr<opName, SISubtarget.SI>;
396 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
397 SOP1 <outs, ins, asm, []>,
399 SIMCInstr<opName, SISubtarget.VI>;
401 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
404 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
406 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
408 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
412 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
413 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
414 opName#" $dst, $src0", pattern
417 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
418 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
419 opName#" $dst, $src0", pattern
422 // no input, 64-bit output.
423 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
424 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
426 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
431 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
437 // 64-bit input, no output
438 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
439 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
441 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
446 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
452 // 64-bit input, 32-bit output.
453 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
454 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
455 opName#" $dst, $src0", pattern
458 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
459 SOP2<outs, ins, "", pattern>,
460 SIMCInstr<opName, SISubtarget.NONE> {
462 let isCodeGenOnly = 1;
465 // Pseudo instructions have no encodings, but adding this field here allows
467 // let sdst = xxx in {
468 // for multiclasses that include both real and pseudo instructions.
469 field bits<7> sdst = 0;
472 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
473 SOP2<outs, ins, asm, []>,
475 SIMCInstr<opName, SISubtarget.SI>;
477 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
478 SOP2<outs, ins, asm, []>,
480 SIMCInstr<opName, SISubtarget.VI>;
482 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
483 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
484 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
486 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
487 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
488 opName#" $dst, $src0, $src1 [$scc]">;
490 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
491 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
492 opName#" $dst, $src0, $src1 [$scc]">;
495 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
498 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
500 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
502 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
506 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
507 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
508 opName#" $dst, $src0, $src1", pattern
511 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
512 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
513 opName#" $dst, $src0, $src1", pattern
516 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
517 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
518 opName#" $dst, $src0, $src1", pattern
521 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
522 string opName, PatLeaf cond> : SOPC <
523 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
524 opName#" $src0, $src1", []>;
526 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
527 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
529 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
530 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
532 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
533 SOPK <outs, ins, "", pattern>,
534 SIMCInstr<opName, SISubtarget.NONE> {
536 let isCodeGenOnly = 1;
539 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
540 SOPK <outs, ins, asm, []>,
542 SIMCInstr<opName, SISubtarget.SI>;
544 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
545 SOPK <outs, ins, asm, []>,
547 SIMCInstr<opName, SISubtarget.VI>;
549 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
550 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
553 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
554 opName#" $dst, $src0">;
556 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
557 opName#" $dst, $src0">;
560 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
561 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
562 (ins SReg_32:$src0, u16imm:$src1), pattern>;
564 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
565 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
567 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
568 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
571 //===----------------------------------------------------------------------===//
573 //===----------------------------------------------------------------------===//
575 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
576 SMRD <outs, ins, "", pattern>,
577 SIMCInstr<opName, SISubtarget.NONE> {
579 let isCodeGenOnly = 1;
582 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
584 SMRD <outs, ins, asm, []>,
586 SIMCInstr<opName, SISubtarget.SI>;
588 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
590 SMRD <outs, ins, asm, []>,
592 SIMCInstr<opName, SISubtarget.VI>;
594 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
595 string asm, list<dag> pattern> {
597 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
599 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
601 // glc is only applicable to scalar stores, which are not yet
604 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
608 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
609 RegisterClass dstClass> {
611 op, opName#"_IMM", 1, (outs dstClass:$dst),
612 (ins baseClass:$sbase, u32imm:$offset),
613 opName#" $dst, $sbase, $offset", []
616 defm _SGPR : SMRD_m <
617 op, opName#"_SGPR", 0, (outs dstClass:$dst),
618 (ins baseClass:$sbase, SReg_32:$soff),
619 opName#" $dst, $sbase, $soff", []
623 //===----------------------------------------------------------------------===//
624 // Vector ALU classes
625 //===----------------------------------------------------------------------===//
627 // This must always be right before the operand being input modified.
628 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
629 let PrintMethod = "printOperandAndMods";
631 def InputModsNoDefault : Operand <i32> {
632 let PrintMethod = "printOperandAndMods";
635 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
637 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
638 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
642 // Returns the register class to use for the destination of VOP[123C]
643 // instructions for the given VT.
644 class getVALUDstForVT<ValueType VT> {
645 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
646 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
647 VOPDstOperand<SReg_64>)); // else VT == i1
650 // Returns the register class to use for source 0 of VOP[12C]
651 // instructions for the given VT.
652 class getVOPSrc0ForVT<ValueType VT> {
653 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
656 // Returns the register class to use for source 1 of VOP[12C] for the
658 class getVOPSrc1ForVT<ValueType VT> {
659 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
662 // Returns the register class to use for sources of VOP3 instructions for the
664 class getVOP3SrcForVT<ValueType VT> {
665 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
668 // Returns 1 if the source arguments have modifiers, 0 if they do not.
669 class hasModifiers<ValueType SrcVT> {
670 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
671 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
674 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
675 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
676 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
677 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
681 // Returns the input arguments for VOP3 instructions for the given SrcVT.
682 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
683 RegisterOperand Src2RC, int NumSrcArgs,
687 !if (!eq(NumSrcArgs, 1),
688 !if (!eq(HasModifiers, 1),
689 // VOP1 with modifiers
690 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
691 ClampMod:$clamp, omod:$omod)
693 // VOP1 without modifiers
696 !if (!eq(NumSrcArgs, 2),
697 !if (!eq(HasModifiers, 1),
698 // VOP 2 with modifiers
699 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
700 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
701 ClampMod:$clamp, omod:$omod)
703 // VOP2 without modifiers
704 (ins Src0RC:$src0, Src1RC:$src1)
706 /* NumSrcArgs == 3 */,
707 !if (!eq(HasModifiers, 1),
708 // VOP3 with modifiers
709 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
710 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
711 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
712 ClampMod:$clamp, omod:$omod)
714 // VOP3 without modifiers
715 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
719 // Returns the assembly string for the inputs and outputs of a VOP[12C]
720 // instruction. This does not add the _e32 suffix, so it can be reused
722 class getAsm32 <int NumSrcArgs> {
723 string src1 = ", $src1";
724 string src2 = ", $src2";
725 string ret = "$dst, $src0"#
726 !if(!eq(NumSrcArgs, 1), "", src1)#
727 !if(!eq(NumSrcArgs, 3), src2, "");
730 // Returns the assembly string for the inputs and outputs of a VOP3
732 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
733 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
734 string src1 = !if(!eq(NumSrcArgs, 1), "",
735 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
736 " $src1_modifiers,"));
737 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
739 !if(!eq(HasModifiers, 0),
740 getAsm32<NumSrcArgs>.ret,
741 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
745 class VOPProfile <list<ValueType> _ArgVT> {
747 field list<ValueType> ArgVT = _ArgVT;
749 field ValueType DstVT = ArgVT[0];
750 field ValueType Src0VT = ArgVT[1];
751 field ValueType Src1VT = ArgVT[2];
752 field ValueType Src2VT = ArgVT[3];
753 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
754 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
755 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
756 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
757 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
758 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
760 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
761 field bit HasModifiers = hasModifiers<Src0VT>.ret;
763 field dag Outs = (outs DstRC:$dst);
765 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
766 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
769 field string Asm32 = getAsm32<NumSrcArgs>.ret;
770 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
773 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
774 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
775 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
776 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
777 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
778 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
779 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
780 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
781 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
783 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
784 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
785 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
786 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
787 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
788 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
789 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
790 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
791 let Src0RC32 = VCSrc_32;
794 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
795 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
796 let Asm64 = "$dst, $src0_modifiers, $src1";
799 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
800 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
801 let Asm64 = "$dst, $src0_modifiers, $src1";
804 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
805 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
806 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
807 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
808 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
809 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
810 let Asm64 = "$dst, $src0, $src1, $src2";
813 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
814 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
815 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
816 field string Asm = "$dst, $src0, $vsrc1, $src2";
818 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
819 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
820 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
823 class VOP <string opName> {
824 string OpName = opName;
827 class VOP2_REV <string revOp, bit isOrig> {
828 string RevOp = revOp;
832 class AtomicNoRet <string noRetOp, bit isRet> {
833 string NoRetOp = noRetOp;
837 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
838 VOP1Common <outs, ins, "", pattern>,
840 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
842 let isCodeGenOnly = 1;
848 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
850 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
852 def _si : VOP1<op.SI, outs, ins, asm, []>,
853 SIMCInstr <opName#"_e32", SISubtarget.SI>;
854 def _vi : VOP1<op.VI, outs, ins, asm, []>,
855 SIMCInstr <opName#"_e32", SISubtarget.VI>;
858 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
860 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
862 def _si : VOP1<op.SI, outs, ins, asm, []>,
863 SIMCInstr <opName#"_e32", SISubtarget.SI>;
864 // No VI instruction. This class is for SI only.
867 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
868 VOP2Common <outs, ins, "", pattern>,
870 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
872 let isCodeGenOnly = 1;
875 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
876 string opName, string revOp> {
877 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
878 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
880 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
881 SIMCInstr <opName#"_e32", SISubtarget.SI>;
884 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
885 string opName, string revOp> {
886 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
887 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
889 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
890 SIMCInstr <opName#"_e32", SISubtarget.SI>;
891 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
892 SIMCInstr <opName#"_e32", SISubtarget.VI>;
895 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
897 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
898 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
899 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
900 bits<2> omod = !if(HasModifiers, ?, 0);
901 bits<1> clamp = !if(HasModifiers, ?, 0);
902 bits<9> src1 = !if(HasSrc1, ?, 0);
903 bits<9> src2 = !if(HasSrc2, ?, 0);
906 class VOP3DisableModFields <bit HasSrc0Mods,
909 bit HasOutputMods = 0> {
910 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
911 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
912 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
913 bits<2> omod = !if(HasOutputMods, ?, 0);
914 bits<1> clamp = !if(HasOutputMods, ?, 0);
917 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
918 VOP3Common <outs, ins, "", pattern>,
920 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
922 let isCodeGenOnly = 1;
925 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
926 VOP3Common <outs, ins, asm, []>,
928 SIMCInstr<opName#"_e64", SISubtarget.SI>;
930 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
931 VOP3Common <outs, ins, asm, []>,
933 SIMCInstr <opName#"_e64", SISubtarget.VI>;
935 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
936 VOP3Common <outs, ins, asm, []>,
938 SIMCInstr<opName#"_e64", SISubtarget.SI>;
940 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
941 VOP3Common <outs, ins, asm, []>,
943 SIMCInstr <opName#"_e64", SISubtarget.VI>;
945 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
946 string opName, int NumSrcArgs, bit HasMods = 1> {
948 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
950 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
951 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
952 !if(!eq(NumSrcArgs, 2), 0, 1),
954 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
955 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
956 !if(!eq(NumSrcArgs, 2), 0, 1),
960 // VOP3_m without source modifiers
961 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
962 string opName, int NumSrcArgs, bit HasMods = 1> {
964 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
966 let src0_modifiers = 0,
971 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
972 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
976 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
977 list<dag> pattern, string opName, bit HasMods = 1> {
979 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
981 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
982 VOP3DisableFields<0, 0, HasMods>;
984 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
985 VOP3DisableFields<0, 0, HasMods>;
988 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
989 list<dag> pattern, string opName, bit HasMods = 1> {
991 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
993 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
994 VOP3DisableFields<0, 0, HasMods>;
995 // No VI instruction. This class is for SI only.
998 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
999 list<dag> pattern, string opName, string revOp,
1000 bit HasMods = 1, bit UseFullOp = 0> {
1002 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1003 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1005 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1006 VOP3DisableFields<1, 0, HasMods>;
1008 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1009 VOP3DisableFields<1, 0, HasMods>;
1012 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1013 list<dag> pattern, string opName, string revOp,
1014 bit HasMods = 1, bit UseFullOp = 0> {
1016 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1017 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1019 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1020 VOP3DisableFields<1, 0, HasMods>;
1022 // No VI instruction. This class is for SI only.
1025 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1026 // option of implicit vcc use?
1027 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1028 list<dag> pattern, string opName, string revOp,
1029 bit HasMods = 1, bit UseFullOp = 0> {
1030 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1031 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1033 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1034 // can write it into any SGPR. We currently don't use the carry out,
1035 // so for now hardcode it to VCC as well.
1036 let sdst = SIOperand.VCC, Defs = [VCC] in {
1037 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1038 VOP3DisableFields<1, 0, HasMods>;
1040 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1041 VOP3DisableFields<1, 0, HasMods>;
1042 } // End sdst = SIOperand.VCC, Defs = [VCC]
1045 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1046 list<dag> pattern, string opName, string revOp,
1047 bit HasMods = 1, bit UseFullOp = 0> {
1048 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1051 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1052 VOP3DisableFields<1, 1, HasMods>;
1054 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1055 VOP3DisableFields<1, 1, HasMods>;
1058 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1059 list<dag> pattern, string opName,
1060 bit HasMods, bit defExec> {
1062 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1064 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1065 VOP3DisableFields<1, 0, HasMods> {
1066 let Defs = !if(defExec, [EXEC], []);
1069 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1070 VOP3DisableFields<1, 0, HasMods> {
1071 let Defs = !if(defExec, [EXEC], []);
1075 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1076 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1077 string asm, list<dag> pattern = []> {
1078 let isPseudo = 1, isCodeGenOnly = 1 in {
1079 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1080 SIMCInstr<opName, SISubtarget.NONE>;
1083 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1084 SIMCInstr <opName, SISubtarget.SI>;
1086 def _vi : VOP3Common <outs, ins, asm, []>,
1088 VOP3DisableFields <1, 0, 0>,
1089 SIMCInstr <opName, SISubtarget.VI>;
1092 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1093 dag ins32, string asm32, list<dag> pat32,
1094 dag ins64, string asm64, list<dag> pat64,
1097 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1099 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1102 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1103 SDPatternOperator node = null_frag> : VOP1_Helper <
1105 P.Ins32, P.Asm32, [],
1108 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1109 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1110 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1114 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1115 SDPatternOperator node = null_frag> {
1117 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1119 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1121 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1122 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1123 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1124 opName, P.HasModifiers>;
1127 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1128 dag ins32, string asm32, list<dag> pat32,
1129 dag ins64, string asm64, list<dag> pat64,
1130 string revOp, bit HasMods> {
1131 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1133 defm _e64 : VOP3_2_m <op,
1134 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1138 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1139 SDPatternOperator node = null_frag,
1140 string revOp = opName> : VOP2_Helper <
1142 P.Ins32, P.Asm32, [],
1146 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1147 i1:$clamp, i32:$omod)),
1148 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1149 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1150 revOp, P.HasModifiers
1153 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1154 SDPatternOperator node = null_frag,
1155 string revOp = opName> {
1156 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1158 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1161 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1162 i1:$clamp, i32:$omod)),
1163 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1164 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1165 opName, revOp, P.HasModifiers>;
1168 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1169 dag ins32, string asm32, list<dag> pat32,
1170 dag ins64, string asm64, list<dag> pat64,
1171 string revOp, bit HasMods> {
1173 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1175 defm _e64 : VOP3b_2_m <op,
1176 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1180 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1181 SDPatternOperator node = null_frag,
1182 string revOp = opName> : VOP2b_Helper <
1184 P.Ins32, P.Asm32, [],
1188 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1189 i1:$clamp, i32:$omod)),
1190 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1191 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1192 revOp, P.HasModifiers
1195 // A VOP2 instruction that is VOP3-only on VI.
1196 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1197 dag ins32, string asm32, list<dag> pat32,
1198 dag ins64, string asm64, list<dag> pat64,
1199 string revOp, bit HasMods> {
1200 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1202 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1206 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1207 SDPatternOperator node = null_frag,
1208 string revOp = opName>
1211 P.Ins32, P.Asm32, [],
1215 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1216 i1:$clamp, i32:$omod)),
1217 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1218 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1219 revOp, P.HasModifiers
1222 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1224 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1226 let isCodeGenOnly = 0 in {
1227 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1228 !strconcat(opName, VOP_MADK.Asm), []>,
1229 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1232 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1233 !strconcat(opName, VOP_MADK.Asm), []>,
1234 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1236 } // End isCodeGenOnly = 0
1239 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1240 VOPCCommon <ins, "", pattern>,
1242 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1244 let isCodeGenOnly = 1;
1247 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1248 string opName, bit DefExec> {
1249 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1251 def _si : VOPC<op.SI, ins, asm, []>,
1252 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1253 let Defs = !if(DefExec, [EXEC], []);
1256 def _vi : VOPC<op.VI, ins, asm, []>,
1257 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1258 let Defs = !if(DefExec, [EXEC], []);
1262 multiclass VOPC_Helper <vopc op, string opName,
1263 dag ins32, string asm32, list<dag> pat32,
1264 dag out64, dag ins64, string asm64, list<dag> pat64,
1265 bit HasMods, bit DefExec> {
1266 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1268 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1269 opName, HasMods, DefExec>;
1272 // Special case for class instructions which only have modifiers on
1273 // the 1st source operand.
1274 multiclass VOPC_Class_Helper <vopc op, string opName,
1275 dag ins32, string asm32, list<dag> pat32,
1276 dag out64, dag ins64, string asm64, list<dag> pat64,
1277 bit HasMods, bit DefExec> {
1278 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1280 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1281 opName, HasMods, DefExec>,
1282 VOP3DisableModFields<1, 0, 0>;
1285 multiclass VOPCInst <vopc op, string opName,
1286 VOPProfile P, PatLeaf cond = COND_NULL,
1287 bit DefExec = 0> : VOPC_Helper <
1289 P.Ins32, P.Asm32, [],
1290 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1293 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1294 i1:$clamp, i32:$omod)),
1295 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1297 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1298 P.HasModifiers, DefExec
1301 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1302 bit DefExec = 0> : VOPC_Class_Helper <
1304 P.Ins32, P.Asm32, [],
1305 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1308 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1309 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1310 P.HasModifiers, DefExec
1314 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1315 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1317 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1318 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1320 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1321 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1323 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1324 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1327 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1328 PatLeaf cond = COND_NULL>
1329 : VOPCInst <op, opName, P, cond, 1>;
1331 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1332 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1334 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1335 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1337 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1338 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1340 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1341 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1343 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1344 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1345 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1348 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1349 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1351 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1352 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1354 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1355 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1357 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1358 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1360 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1361 SDPatternOperator node = null_frag> : VOP3_Helper <
1362 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1363 !if(!eq(P.NumSrcArgs, 3),
1366 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1367 i1:$clamp, i32:$omod)),
1368 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1369 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1370 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1372 !if(!eq(P.NumSrcArgs, 2),
1375 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1376 i1:$clamp, i32:$omod)),
1377 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1378 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1379 /* P.NumSrcArgs == 1 */,
1382 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1383 i1:$clamp, i32:$omod))))],
1384 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1385 P.NumSrcArgs, P.HasModifiers
1388 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1389 // only VOP instruction that implicitly reads VCC.
1390 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1392 SDPatternOperator node = null_frag> : VOP3_Helper <
1394 (outs P.DstRC.RegClass:$dst),
1395 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1396 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1397 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1400 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1402 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1403 i1:$clamp, i32:$omod)),
1404 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1405 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1410 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1411 string opName, list<dag> pattern> :
1413 op, (outs vrc:$vdst, SReg_64:$sdst),
1414 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1415 InputModsNoDefault:$src1_modifiers, arc:$src1,
1416 InputModsNoDefault:$src2_modifiers, arc:$src2,
1417 ClampMod:$clamp, omod:$omod),
1418 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1419 opName, opName, 1, 1
1422 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1423 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1425 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1426 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1429 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1430 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1431 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1432 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1433 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1434 i32:$src1_modifiers, P.Src1VT:$src1,
1435 i32:$src2_modifiers, P.Src2VT:$src2,
1439 //===----------------------------------------------------------------------===//
1440 // Interpolation opcodes
1441 //===----------------------------------------------------------------------===//
1443 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1444 VINTRPCommon <outs, ins, "", pattern>,
1445 SIMCInstr<opName, SISubtarget.NONE> {
1447 let isCodeGenOnly = 1;
1450 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1452 VINTRPCommon <outs, ins, asm, []>,
1454 SIMCInstr<opName, SISubtarget.SI>;
1456 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1458 VINTRPCommon <outs, ins, asm, []>,
1460 SIMCInstr<opName, SISubtarget.VI>;
1462 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1463 string disableEncoding = "", string constraints = "",
1464 list<dag> pattern = []> {
1465 let DisableEncoding = disableEncoding,
1466 Constraints = constraints in {
1467 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1469 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1471 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1475 //===----------------------------------------------------------------------===//
1476 // Vector I/O classes
1477 //===----------------------------------------------------------------------===//
1479 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1480 DS <outs, ins, "", pattern>,
1481 SIMCInstr <opName, SISubtarget.NONE> {
1483 let isCodeGenOnly = 1;
1486 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1487 DS <outs, ins, asm, []>,
1489 SIMCInstr <opName, SISubtarget.SI>;
1491 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1492 DS <outs, ins, asm, []>,
1494 SIMCInstr <opName, SISubtarget.VI>;
1496 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1497 DS_Real_si <op,opName, outs, ins, asm> {
1499 // Single load interpret the 2 i8imm operands as a single i16 offset.
1501 let offset0 = offset{7-0};
1502 let offset1 = offset{15-8};
1505 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1506 DS_Real_vi <op, opName, outs, ins, asm> {
1508 // Single load interpret the 2 i8imm operands as a single i16 offset.
1510 let offset0 = offset{7-0};
1511 let offset1 = offset{15-8};
1514 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1515 dag outs = (outs rc:$vdst),
1516 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1517 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1519 def "" : DS_Pseudo <opName, outs, ins, []>;
1521 let data0 = 0, data1 = 0 in {
1522 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1523 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1527 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1528 dag outs = (outs rc:$vdst),
1529 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1530 gds:$gds, M0Reg:$m0),
1531 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1533 def "" : DS_Pseudo <opName, outs, ins, []>;
1535 let data0 = 0, data1 = 0 in {
1536 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1537 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1541 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1543 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1545 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1547 def "" : DS_Pseudo <opName, outs, ins, []>,
1548 AtomicNoRet<opName, 0>;
1550 let data1 = 0, vdst = 0 in {
1551 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1552 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1556 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1558 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1559 ds_offset0:$offset0, ds_offset1:$offset1, gds:$gds, M0Reg:$m0),
1560 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1562 def "" : DS_Pseudo <opName, outs, ins, []>;
1565 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1566 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1570 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1571 string noRetOp = "",
1572 dag outs = (outs rc:$vdst),
1573 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1575 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1577 def "" : DS_Pseudo <opName, outs, ins, []>,
1578 AtomicNoRet<noRetOp, 1>;
1581 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1582 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1586 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1587 string noRetOp = "", dag ins,
1588 dag outs = (outs rc:$vdst),
1589 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1591 def "" : DS_Pseudo <opName, outs, ins, []>,
1592 AtomicNoRet<noRetOp, 1>;
1594 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1595 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1598 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1599 string noRetOp = "", RegisterClass src = rc> :
1600 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1601 (ins VGPR_32:$addr, src:$data0, src:$data1,
1602 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1605 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1606 string noRetOp = opName,
1608 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1609 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1610 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1612 def "" : DS_Pseudo <opName, outs, ins, []>,
1613 AtomicNoRet<noRetOp, 0>;
1616 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1617 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1621 multiclass DS_0A_RET <bits<8> op, string opName,
1622 dag outs = (outs VGPR_32:$vdst),
1623 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1624 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1626 let mayLoad = 1, mayStore = 1 in {
1627 def "" : DS_Pseudo <opName, outs, ins, []>;
1629 let addr = 0, data0 = 0, data1 = 0 in {
1630 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1631 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1632 } // end addr = 0, data0 = 0, data1 = 0
1633 } // end mayLoad = 1, mayStore = 1
1636 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1637 dag outs = (outs VGPR_32:$vdst),
1638 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1639 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1641 def "" : DS_Pseudo <opName, outs, ins, []>;
1643 let data0 = 0, data1 = 0, gds = 1 in {
1644 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1645 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1646 } // end data0 = 0, data1 = 0, gds = 1
1649 multiclass DS_1A_GDS <bits<8> op, string opName,
1651 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
1652 string asm = opName#" $addr gds"> {
1654 def "" : DS_Pseudo <opName, outs, ins, []>;
1656 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1657 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1658 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1659 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1662 multiclass DS_1A <bits<8> op, string opName,
1664 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0, gds:$gds),
1665 string asm = opName#" $addr"#"$offset"#"$gds"> {
1667 let mayLoad = 1, mayStore = 1 in {
1668 def "" : DS_Pseudo <opName, outs, ins, []>;
1670 let vdst = 0, data0 = 0, data1 = 0 in {
1671 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1672 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1673 } // let vdst = 0, data0 = 0, data1 = 0
1674 } // end mayLoad = 1, mayStore = 1
1677 //===----------------------------------------------------------------------===//
1679 //===----------------------------------------------------------------------===//
1681 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1682 MTBUF <outs, ins, "", pattern>,
1683 SIMCInstr<opName, SISubtarget.NONE> {
1685 let isCodeGenOnly = 1;
1688 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1690 MTBUF <outs, ins, asm, []>,
1692 SIMCInstr<opName, SISubtarget.SI>;
1694 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1695 MTBUF <outs, ins, asm, []>,
1697 SIMCInstr <opName, SISubtarget.VI>;
1699 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1700 list<dag> pattern> {
1702 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1704 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1706 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1710 let mayStore = 1, mayLoad = 0 in {
1712 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1713 RegisterClass regClass> : MTBUF_m <
1715 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1716 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1717 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1718 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1719 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1722 } // mayStore = 1, mayLoad = 0
1724 let mayLoad = 1, mayStore = 0 in {
1726 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1727 RegisterClass regClass> : MTBUF_m <
1728 op, opName, (outs regClass:$dst),
1729 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1730 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1731 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1732 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1733 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1736 } // mayLoad = 1, mayStore = 0
1738 //===----------------------------------------------------------------------===//
1740 //===----------------------------------------------------------------------===//
1742 class mubuf <bits<7> si, bits<7> vi = si> {
1743 field bits<7> SI = si;
1744 field bits<7> VI = vi;
1747 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1748 bit IsAddr64 = is_addr64;
1749 string OpName = NAME # suffix;
1752 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1753 MUBUF <outs, ins, "", pattern>,
1754 SIMCInstr<opName, SISubtarget.NONE> {
1756 let isCodeGenOnly = 1;
1758 // dummy fields, so that we can use let statements around multiclasses
1768 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1770 MUBUF <outs, ins, asm, []>,
1772 SIMCInstr<opName, SISubtarget.SI> {
1776 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1778 MUBUF <outs, ins, asm, []>,
1780 SIMCInstr<opName, SISubtarget.VI> {
1784 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1785 list<dag> pattern> {
1787 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1788 MUBUFAddr64Table <0>;
1791 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1794 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1797 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1798 dag ins, string asm, list<dag> pattern> {
1800 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1801 MUBUFAddr64Table <1>;
1804 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1807 // There is no VI version. If the pseudo is selected, it should be lowered
1808 // for VI appropriately.
1811 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1812 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1816 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1817 string asm, list<dag> pattern, bit is_return> {
1819 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1820 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1821 AtomicNoRet<NAME#"_OFFSET", is_return>;
1823 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1825 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1828 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1832 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1833 string asm, list<dag> pattern, bit is_return> {
1835 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1836 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1837 AtomicNoRet<NAME#"_ADDR64", is_return>;
1839 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1840 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1843 // There is no VI version. If the pseudo is selected, it should be lowered
1844 // for VI appropriately.
1847 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1848 ValueType vt, SDPatternOperator atomic> {
1850 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1852 // No return variants
1855 defm _ADDR64 : MUBUFAtomicAddr64_m <
1856 op, name#"_addr64", (outs),
1857 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1858 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1859 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1862 defm _OFFSET : MUBUFAtomicOffset_m <
1863 op, name#"_offset", (outs),
1864 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
1866 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1870 // Variant that return values
1871 let glc = 1, Constraints = "$vdata = $vdata_in",
1872 DisableEncoding = "$vdata_in" in {
1874 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1875 op, name#"_rtn_addr64", (outs rc:$vdata),
1876 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1877 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1878 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1880 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1881 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1884 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1885 op, name#"_rtn_offset", (outs rc:$vdata),
1886 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
1887 mbuf_offset:$offset, slc:$slc),
1888 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1890 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1891 i1:$slc), vt:$vdata_in))], 1
1896 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1899 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1900 ValueType load_vt = i32,
1901 SDPatternOperator ld = null_frag> {
1903 let mayLoad = 1, mayStore = 0 in {
1904 let offen = 0, idxen = 0, vaddr = 0 in {
1905 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1906 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
1907 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1908 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1909 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1910 i32:$soffset, i16:$offset,
1911 i1:$glc, i1:$slc, i1:$tfe)))]>;
1914 let offen = 1, idxen = 0 in {
1915 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1916 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
1917 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1919 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1922 let offen = 0, idxen = 1 in {
1923 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1924 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
1925 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1926 slc:$slc, tfe:$tfe),
1927 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1930 let offen = 1, idxen = 1 in {
1931 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1932 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
1933 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1934 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1937 let offen = 0, idxen = 0 in {
1938 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1939 (ins VReg_64:$vaddr, SReg_128:$srsrc,
1940 SCSrc_32:$soffset, mbuf_offset:$offset,
1941 glc:$glc, slc:$slc, tfe:$tfe),
1942 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
1943 "$glc"#"$slc"#"$tfe",
1944 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1945 i64:$vaddr, i32:$soffset,
1946 i16:$offset, i1:$glc, i1:$slc,
1952 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1953 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
1954 let mayLoad = 0, mayStore = 1 in {
1955 defm : MUBUF_m <op, name, (outs),
1956 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
1957 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1959 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1960 "$glc"#"$slc"#"$tfe", []>;
1962 let offen = 0, idxen = 0, vaddr = 0 in {
1963 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1964 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
1965 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1966 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1967 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1968 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1969 } // offen = 0, idxen = 0, vaddr = 0
1971 let offen = 1, idxen = 0 in {
1972 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1973 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
1974 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1975 slc:$slc, tfe:$tfe),
1976 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1977 "$glc"#"$slc"#"$tfe", []>;
1978 } // end offen = 1, idxen = 0
1980 let offen = 0, idxen = 1 in {
1981 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
1982 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
1983 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1984 slc:$slc, tfe:$tfe),
1985 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1988 let offen = 1, idxen = 1 in {
1989 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
1990 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
1991 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1992 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1995 let offen = 0, idxen = 0 in {
1996 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1997 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
1999 mbuf_offset:$offset, glc:$glc, slc:$slc,
2001 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2002 "$offset"#"$glc"#"$slc"#"$tfe",
2003 [(st store_vt:$vdata,
2004 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2005 i32:$soffset, i16:$offset,
2006 i1:$glc, i1:$slc, i1:$tfe))]>;
2008 } // End mayLoad = 0, mayStore = 1
2011 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2012 FLAT <op, (outs regClass:$vdst),
2013 (ins VReg_64:$addr),
2014 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2022 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2023 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2024 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2037 class MIMG_Mask <string op, int channels> {
2039 int Channels = channels;
2042 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2043 RegisterClass dst_rc,
2044 RegisterClass src_rc> : MIMG <
2046 (outs dst_rc:$vdata),
2047 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2048 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2050 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2051 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2056 let hasPostISelHook = 1;
2059 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2060 RegisterClass dst_rc,
2062 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2063 MIMG_Mask<asm#"_V1", channels>;
2064 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2065 MIMG_Mask<asm#"_V2", channels>;
2066 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2067 MIMG_Mask<asm#"_V4", channels>;
2070 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2071 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2072 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2073 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2074 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2077 class MIMG_Sampler_Helper <bits<7> op, string asm,
2078 RegisterClass dst_rc,
2079 RegisterClass src_rc, int wqm> : MIMG <
2081 (outs dst_rc:$vdata),
2082 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2083 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2084 SReg_256:$srsrc, SReg_128:$ssamp),
2085 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2086 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2090 let hasPostISelHook = 1;
2094 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2095 RegisterClass dst_rc,
2096 int channels, int wqm> {
2097 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2098 MIMG_Mask<asm#"_V1", channels>;
2099 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2100 MIMG_Mask<asm#"_V2", channels>;
2101 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2102 MIMG_Mask<asm#"_V4", channels>;
2103 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2104 MIMG_Mask<asm#"_V8", channels>;
2105 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2106 MIMG_Mask<asm#"_V16", channels>;
2109 multiclass MIMG_Sampler <bits<7> op, string asm> {
2110 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2111 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2112 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2113 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2116 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2117 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2118 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2119 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2120 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2123 class MIMG_Gather_Helper <bits<7> op, string asm,
2124 RegisterClass dst_rc,
2125 RegisterClass src_rc, int wqm> : MIMG <
2127 (outs dst_rc:$vdata),
2128 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2129 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2130 SReg_256:$srsrc, SReg_128:$ssamp),
2131 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2132 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2137 // DMASK was repurposed for GATHER4. 4 components are always
2138 // returned and DMASK works like a swizzle - it selects
2139 // the component to fetch. The only useful DMASK values are
2140 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2141 // (red,red,red,red) etc.) The ISA document doesn't mention
2143 // Therefore, disable all code which updates DMASK by setting these two:
2145 let hasPostISelHook = 0;
2149 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2150 RegisterClass dst_rc,
2151 int channels, int wqm> {
2152 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2153 MIMG_Mask<asm#"_V1", channels>;
2154 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2155 MIMG_Mask<asm#"_V2", channels>;
2156 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2157 MIMG_Mask<asm#"_V4", channels>;
2158 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2159 MIMG_Mask<asm#"_V8", channels>;
2160 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2161 MIMG_Mask<asm#"_V16", channels>;
2164 multiclass MIMG_Gather <bits<7> op, string asm> {
2165 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2166 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2167 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2168 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2171 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2172 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2173 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2174 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2175 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2178 //===----------------------------------------------------------------------===//
2179 // Vector instruction mappings
2180 //===----------------------------------------------------------------------===//
2182 // Maps an opcode in e32 form to its e64 equivalent
2183 def getVOPe64 : InstrMapping {
2184 let FilterClass = "VOP";
2185 let RowFields = ["OpName"];
2186 let ColFields = ["Size"];
2188 let ValueCols = [["8"]];
2191 // Maps an opcode in e64 form to its e32 equivalent
2192 def getVOPe32 : InstrMapping {
2193 let FilterClass = "VOP";
2194 let RowFields = ["OpName"];
2195 let ColFields = ["Size"];
2197 let ValueCols = [["4"]];
2200 // Maps an original opcode to its commuted version
2201 def getCommuteRev : InstrMapping {
2202 let FilterClass = "VOP2_REV";
2203 let RowFields = ["RevOp"];
2204 let ColFields = ["IsOrig"];
2206 let ValueCols = [["0"]];
2209 def getMaskedMIMGOp : InstrMapping {
2210 let FilterClass = "MIMG_Mask";
2211 let RowFields = ["Op"];
2212 let ColFields = ["Channels"];
2214 let ValueCols = [["1"], ["2"], ["3"] ];
2217 // Maps an commuted opcode to its original version
2218 def getCommuteOrig : InstrMapping {
2219 let FilterClass = "VOP2_REV";
2220 let RowFields = ["RevOp"];
2221 let ColFields = ["IsOrig"];
2223 let ValueCols = [["1"]];
2226 def getMCOpcodeGen : InstrMapping {
2227 let FilterClass = "SIMCInstr";
2228 let RowFields = ["PseudoInstr"];
2229 let ColFields = ["Subtarget"];
2230 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2231 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2234 def getAddr64Inst : InstrMapping {
2235 let FilterClass = "MUBUFAddr64Table";
2236 let RowFields = ["OpName"];
2237 let ColFields = ["IsAddr64"];
2239 let ValueCols = [["1"]];
2242 // Maps an atomic opcode to its version with a return value.
2243 def getAtomicRetOp : InstrMapping {
2244 let FilterClass = "AtomicNoRet";
2245 let RowFields = ["NoRetOp"];
2246 let ColFields = ["IsRet"];
2248 let ValueCols = [["1"]];
2251 // Maps an atomic opcode to its returnless version.
2252 def getAtomicNoRetOp : InstrMapping {
2253 let FilterClass = "AtomicNoRet";
2254 let RowFields = ["NoRetOp"];
2255 let ColFields = ["IsRet"];
2257 let ValueCols = [["0"]];
2260 include "SIInstructions.td"
2261 include "CIInstructions.td"
2262 include "VIInstructions.td"