1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
14 class vopc <bits<8> si> : vop {
15 field bits<8> SI = si;
17 field bits<9> SI3 = {0, si{7-0}};
20 class vop1 <bits<8> si> : vop {
21 field bits<8> SI = si;
23 field bits<9> SI3 = {1, 1, si{6-0}};
26 class vop2 <bits<6> si> : vop {
27 field bits<6> SI = si;
29 field bits<9> SI3 = {1, 0, 0, si{5-0}};
32 class vop3 <bits<9> si> : vop {
33 field bits<9> SI3 = si;
36 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
37 // in AMDGPUMCInstLower.h
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
47 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
48 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
49 [SDNPMayLoad, SDNPMemOperand]
52 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
54 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
55 SDTCisVT<1, iAny>, // vdata(VGPR)
56 SDTCisVT<2, i32>, // num_channels(imm)
57 SDTCisVT<3, i32>, // vaddr(VGPR)
58 SDTCisVT<4, i32>, // soffset(SGPR)
59 SDTCisVT<5, i32>, // inst_offset(imm)
60 SDTCisVT<6, i32>, // dfmt(imm)
61 SDTCisVT<7, i32>, // nfmt(imm)
62 SDTCisVT<8, i32>, // offen(imm)
63 SDTCisVT<9, i32>, // idxen(imm)
64 SDTCisVT<10, i32>, // glc(imm)
65 SDTCisVT<11, i32>, // slc(imm)
66 SDTCisVT<12, i32> // tfe(imm)
68 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
71 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
72 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
76 class SDSample<string opcode> : SDNode <opcode,
77 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
78 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
81 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
82 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
83 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
84 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
86 def SIconstdata_ptr : SDNode<
87 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
90 // Transformation function, extract the lower 32bit of a 64bit immediate
91 def LO32 : SDNodeXForm<imm, [{
92 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
95 def LO32f : SDNodeXForm<fpimm, [{
96 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
97 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
100 // Transformation function, extract the upper 32bit of a 64bit immediate
101 def HI32 : SDNodeXForm<imm, [{
102 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
105 def HI32f : SDNodeXForm<fpimm, [{
106 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
107 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
110 def IMM8bitDWORD : PatLeaf <(imm),
111 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
114 def as_dword_i32imm : SDNodeXForm<imm, [{
115 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
118 def as_i1imm : SDNodeXForm<imm, [{
119 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
122 def as_i8imm : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
126 def as_i16imm : SDNodeXForm<imm, [{
127 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
130 def as_i32imm: SDNodeXForm<imm, [{
131 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
134 def IMM8bit : PatLeaf <(imm),
135 [{return isUInt<8>(N->getZExtValue());}]
138 def IMM12bit : PatLeaf <(imm),
139 [{return isUInt<12>(N->getZExtValue());}]
142 def IMM16bit : PatLeaf <(imm),
143 [{return isUInt<16>(N->getZExtValue());}]
146 def IMM32bit : PatLeaf <(imm),
147 [{return isUInt<32>(N->getZExtValue());}]
150 def mubuf_vaddr_offset : PatFrag<
151 (ops node:$ptr, node:$offset, node:$imm_offset),
152 (add (add node:$ptr, node:$offset), node:$imm_offset)
155 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
156 return isInlineImmediate(N);
159 class SGPRImm <dag frag> : PatLeaf<frag, [{
160 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
161 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
164 const SIRegisterInfo *SIRI =
165 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
166 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
168 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
175 //===----------------------------------------------------------------------===//
177 //===----------------------------------------------------------------------===//
179 def FRAMEri32 : Operand<iPTR> {
180 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
183 def sopp_brtarget : Operand<OtherVT> {
184 let EncoderMethod = "getSOPPBrEncoding";
185 let OperandType = "OPERAND_PCREL";
188 include "SIInstrFormats.td"
190 let OperandType = "OPERAND_IMMEDIATE" in {
192 def offen : Operand<i1> {
193 let PrintMethod = "printOffen";
195 def idxen : Operand<i1> {
196 let PrintMethod = "printIdxen";
198 def addr64 : Operand<i1> {
199 let PrintMethod = "printAddr64";
201 def mbuf_offset : Operand<i16> {
202 let PrintMethod = "printMBUFOffset";
204 def ds_offset : Operand<i16> {
205 let PrintMethod = "printDSOffset";
207 def ds_offset0 : Operand<i8> {
208 let PrintMethod = "printDSOffset0";
210 def ds_offset1 : Operand<i8> {
211 let PrintMethod = "printDSOffset1";
213 def glc : Operand <i1> {
214 let PrintMethod = "printGLC";
216 def slc : Operand <i1> {
217 let PrintMethod = "printSLC";
219 def tfe : Operand <i1> {
220 let PrintMethod = "printTFE";
223 def omod : Operand <i32> {
224 let PrintMethod = "printOModSI";
227 def ClampMod : Operand <i1> {
228 let PrintMethod = "printClampSI";
231 } // End OperandType = "OPERAND_IMMEDIATE"
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
237 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
238 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
240 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
241 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
242 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
243 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
244 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
245 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
247 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
248 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
249 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
251 //===----------------------------------------------------------------------===//
252 // SI assembler operands
253 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
275 // SI Instruction multiclass helpers.
277 // Instructions with _32 take 32-bit operands.
278 // Instructions with _64 take 64-bit operands.
280 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
281 // encoding is the standard encoding, but instruction that make use of
282 // any of the instruction modifiers must use the 64-bit encoding.
284 // Instructions with _e32 use the 32-bit encoding.
285 // Instructions with _e64 use the 64-bit encoding.
287 //===----------------------------------------------------------------------===//
289 class SIMCInstr <string pseudo, int subtarget> {
290 string PseudoInstr = pseudo;
291 int Subtarget = subtarget;
294 //===----------------------------------------------------------------------===//
296 //===----------------------------------------------------------------------===//
298 class EXPCommon : InstSI<
300 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
301 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
302 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
311 let isPseudo = 1 in {
312 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
315 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
318 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
322 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
323 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
324 opName#" $dst, $src0", pattern
327 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
328 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
329 opName#" $dst, $src0", pattern
332 // 64-bit input, 32-bit output.
333 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
334 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
335 opName#" $dst, $src0", pattern
338 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
339 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
340 opName#" $dst, $src0, $src1", pattern
343 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
344 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
345 opName#" $dst, $src0, $src1", pattern
348 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
349 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
350 opName#" $dst, $src0, $src1", pattern
354 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
355 string opName, PatLeaf cond> : SOPC <
356 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
357 opName#" $dst, $src0, $src1", []>;
359 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
360 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
362 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
363 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
365 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
366 op, (outs SReg_32:$dst), (ins i16imm:$src0),
367 opName#" $dst, $src0", pattern
370 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
371 op, (outs SReg_64:$dst), (ins i16imm:$src0),
372 opName#" $dst, $src0", pattern
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SMRD <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
385 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
387 SMRD <outs, ins, asm, []>,
389 SIMCInstr<opName, SISubtarget.SI>;
391 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
392 string asm, list<dag> pattern> {
394 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
396 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
400 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
401 RegisterClass dstClass> {
403 op, opName#"_IMM", 1, (outs dstClass:$dst),
404 (ins baseClass:$sbase, u32imm:$offset),
405 opName#" $dst, $sbase, $offset", []
408 defm _SGPR : SMRD_m <
409 op, opName#"_SGPR", 0, (outs dstClass:$dst),
410 (ins baseClass:$sbase, SReg_32:$soff),
411 opName#" $dst, $sbase, $soff", []
415 //===----------------------------------------------------------------------===//
416 // Vector ALU classes
417 //===----------------------------------------------------------------------===//
419 // This must always be right before the operand being input modified.
420 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
421 let PrintMethod = "printOperandAndMods";
423 def InputModsNoDefault : Operand <i32> {
424 let PrintMethod = "printOperandAndMods";
427 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
429 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
430 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
434 // Returns the register class to use for the destination of VOP[123C]
435 // instructions for the given VT.
436 class getVALUDstForVT<ValueType VT> {
437 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
440 // Returns the register class to use for source 0 of VOP[12C]
441 // instructions for the given VT.
442 class getVOPSrc0ForVT<ValueType VT> {
443 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
446 // Returns the register class to use for source 1 of VOP[12C] for the
448 class getVOPSrc1ForVT<ValueType VT> {
449 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
452 // Returns the register classes for the source arguments of a VOP[12C]
453 // instruction for the given SrcVTs.
454 class getInRC32 <list<ValueType> SrcVT> {
455 list<RegisterClass> ret = [
456 getVOPSrc0ForVT<SrcVT[0]>.ret,
457 getVOPSrc1ForVT<SrcVT[1]>.ret
461 // Returns the register class to use for sources of VOP3 instructions for the
463 class getVOP3SrcForVT<ValueType VT> {
464 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
467 // Returns the register classes for the source arguments of a VOP3
468 // instruction for the given SrcVTs.
469 class getInRC64 <list<ValueType> SrcVT> {
470 list<RegisterClass> ret = [
471 getVOP3SrcForVT<SrcVT[0]>.ret,
472 getVOP3SrcForVT<SrcVT[1]>.ret,
473 getVOP3SrcForVT<SrcVT[2]>.ret
477 // Returns 1 if the source arguments have modifiers, 0 if they do not.
478 class hasModifiers<ValueType SrcVT> {
479 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
480 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
483 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
484 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
485 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
486 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
490 // Returns the input arguments for VOP3 instructions for the given SrcVT.
491 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
492 RegisterClass Src2RC, int NumSrcArgs,
496 !if (!eq(NumSrcArgs, 1),
497 !if (!eq(HasModifiers, 1),
498 // VOP1 with modifiers
499 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
500 ClampMod:$clamp, omod:$omod)
502 // VOP1 without modifiers
505 !if (!eq(NumSrcArgs, 2),
506 !if (!eq(HasModifiers, 1),
507 // VOP 2 with modifiers
508 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
509 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
510 ClampMod:$clamp, omod:$omod)
512 // VOP2 without modifiers
513 (ins Src0RC:$src0, Src1RC:$src1)
515 /* NumSrcArgs == 3 */,
516 !if (!eq(HasModifiers, 1),
517 // VOP3 with modifiers
518 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
519 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
520 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
521 ClampMod:$clamp, omod:$omod)
523 // VOP3 without modifiers
524 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
528 // Returns the assembly string for the inputs and outputs of a VOP[12C]
529 // instruction. This does not add the _e32 suffix, so it can be reused
531 class getAsm32 <int NumSrcArgs> {
532 string src1 = ", $src1";
533 string src2 = ", $src2";
534 string ret = " $dst, $src0"#
535 !if(!eq(NumSrcArgs, 1), "", src1)#
536 !if(!eq(NumSrcArgs, 3), src2, "");
539 // Returns the assembly string for the inputs and outputs of a VOP3
541 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
542 string src0 = "$src0_modifiers,";
543 string src1 = !if(!eq(NumSrcArgs, 1), "",
544 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
545 " $src1_modifiers,"));
546 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
548 !if(!eq(HasModifiers, 0),
549 getAsm32<NumSrcArgs>.ret,
550 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
554 class VOPProfile <list<ValueType> _ArgVT> {
556 field list<ValueType> ArgVT = _ArgVT;
558 field ValueType DstVT = ArgVT[0];
559 field ValueType Src0VT = ArgVT[1];
560 field ValueType Src1VT = ArgVT[2];
561 field ValueType Src2VT = ArgVT[3];
562 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
563 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
564 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
565 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
566 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
567 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
569 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
570 field bit HasModifiers = hasModifiers<Src0VT>.ret;
572 field dag Outs = (outs DstRC:$dst);
574 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
575 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
578 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
579 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
582 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
583 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
584 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
585 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
586 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
587 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
588 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
589 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
590 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
592 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
593 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
594 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
595 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
596 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
597 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
598 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
599 let Src0RC32 = VCSrc_32;
601 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
602 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
604 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
605 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
606 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
607 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
610 class VOP <string opName> {
611 string OpName = opName;
614 class VOP2_REV <string revOp, bit isOrig> {
615 string RevOp = revOp;
619 class AtomicNoRet <string noRetOp, bit isRet> {
620 string NoRetOp = noRetOp;
624 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
625 VOP1Common <outs, ins, "", pattern>,
626 SIMCInstr<opName, SISubtarget.NONE> {
630 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
632 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
634 def _si : VOP1<op.SI, outs, ins, asm, []>,
635 SIMCInstr <opName, SISubtarget.SI>;
638 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
640 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
641 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
642 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
643 bits<2> omod = !if(HasModifiers, ?, 0);
644 bits<1> clamp = !if(HasModifiers, ?, 0);
645 bits<9> src1 = !if(HasSrc1, ?, 0);
646 bits<9> src2 = !if(HasSrc2, ?, 0);
649 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
650 VOP3Common <outs, ins, "", pattern>,
652 SIMCInstr<opName, SISubtarget.NONE> {
656 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
657 VOP3 <op, outs, ins, asm, []>,
658 SIMCInstr<opName, SISubtarget.SI>;
660 multiclass VOP3_m <vop3 op, dag outs, dag ins, string asm, list<dag> pattern,
661 string opName, int NumSrcArgs, bit HasMods = 1> {
663 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
665 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
666 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
667 !if(!eq(NumSrcArgs, 2), 0, 1),
672 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
673 list<dag> pattern, string opName, bit HasMods = 1> {
675 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
677 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
678 VOP3DisableFields<0, 0, HasMods>;
681 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
682 list<dag> pattern, string opName, string revOp,
683 bit HasMods = 1, bit UseFullOp = 0> {
685 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
686 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
688 def _si : VOP3_Real_si <op.SI3,
689 outs, ins, asm, opName>,
690 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
691 VOP3DisableFields<1, 0, HasMods>;
694 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
695 list<dag> pattern, string opName, string revOp,
696 bit HasMods = 1, bit UseFullOp = 0> {
697 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
698 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
700 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
701 // can write it into any SGPR. We currently don't use the carry out,
702 // so for now hardcode it to VCC as well.
703 let sdst = SIOperand.VCC, Defs = [VCC] in {
704 def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
705 VOP3DisableFields<1, 0, HasMods>,
706 SIMCInstr<opName, SISubtarget.SI>,
707 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
708 } // End sdst = SIOperand.VCC, Defs = [VCC]
711 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
712 list<dag> pattern, string opName,
713 bit HasMods, bit defExec> {
715 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
717 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
718 VOP3DisableFields<1, 0, HasMods> {
719 let Defs = !if(defExec, [EXEC], []);
723 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
724 dag ins32, string asm32, list<dag> pat32,
725 dag ins64, string asm64, list<dag> pat64,
728 def _e32 : VOP1 <op.SI, outs, ins32, opName#asm32, pat32>, VOP<opName>;
730 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
733 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
734 SDPatternOperator node = null_frag> : VOP1_Helper <
736 P.Ins32, P.Asm32, [],
739 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
740 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
741 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
745 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
746 list<dag> pattern, string revOp> :
747 VOP2 <op, outs, ins, opName#asm, pattern>,
749 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
751 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
752 dag ins32, string asm32, list<dag> pat32,
753 dag ins64, string asm64, list<dag> pat64,
754 string revOp, bit HasMods> {
755 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
757 defm _e64 : VOP3_2_m <op,
758 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
762 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
763 SDPatternOperator node = null_frag,
764 string revOp = opName> : VOP2_Helper <
766 P.Ins32, P.Asm32, [],
770 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
771 i1:$clamp, i32:$omod)),
772 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
773 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
774 revOp, P.HasModifiers
777 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
778 dag ins32, string asm32, list<dag> pat32,
779 dag ins64, string asm64, list<dag> pat64,
780 string revOp, bit HasMods> {
782 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
784 defm _e64 : VOP3b_2_m <op,
785 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
789 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
790 SDPatternOperator node = null_frag,
791 string revOp = opName> : VOP2b_Helper <
793 P.Ins32, P.Asm32, [],
797 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
798 i1:$clamp, i32:$omod)),
799 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
800 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
801 revOp, P.HasModifiers
804 multiclass VOPC_Helper <vopc op, string opName,
805 dag ins32, string asm32, list<dag> pat32,
806 dag out64, dag ins64, string asm64, list<dag> pat64,
807 bit HasMods, bit DefExec> {
808 def _e32 : VOPC <op.SI, ins32, opName#asm32, pat32>, VOP <opName> {
809 let Defs = !if(DefExec, [EXEC], []);
812 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
816 multiclass VOPCInst <vopc op, string opName,
817 VOPProfile P, PatLeaf cond = COND_NULL,
818 bit DefExec = 0> : VOPC_Helper <
820 P.Ins32, P.Asm32, [],
821 (outs SReg_64:$dst), P.Ins64, P.Asm64,
824 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
825 i1:$clamp, i32:$omod)),
826 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
828 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
829 P.HasModifiers, DefExec
832 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
833 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
835 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
836 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
838 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
839 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
841 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
842 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
845 multiclass VOPCX <vopc op, string opName, VOPProfile P,
846 PatLeaf cond = COND_NULL>
847 : VOPCInst <op, opName, P, cond, 1>;
849 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
850 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
852 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
853 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
855 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
856 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
858 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
859 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
861 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
862 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
863 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
866 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
867 SDPatternOperator node = null_frag> : VOP3_Helper <
868 op, opName, P.Outs, P.Ins64, P.Asm64,
869 !if(!eq(P.NumSrcArgs, 3),
872 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
873 i1:$clamp, i32:$omod)),
874 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
875 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
876 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
878 !if(!eq(P.NumSrcArgs, 2),
881 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
882 i1:$clamp, i32:$omod)),
883 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
884 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
885 /* P.NumSrcArgs == 1 */,
888 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
889 i1:$clamp, i32:$omod))))],
890 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
891 P.NumSrcArgs, P.HasModifiers
894 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterClass arc,
895 string opName, list<dag> pattern> :
897 op, (outs vrc:$vdst, SReg_64:$sdst),
898 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
899 InputModsNoDefault:$src1_modifiers, arc:$src1,
900 InputModsNoDefault:$src2_modifiers, arc:$src2,
901 ClampMod:$clamp, omod:$omod),
902 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
906 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
907 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
909 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
910 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
913 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
914 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
915 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
916 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
917 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
918 i32:$src1_modifiers, P.Src1VT:$src1,
919 i32:$src2_modifiers, P.Src2VT:$src2,
923 //===----------------------------------------------------------------------===//
924 // Vector I/O classes
925 //===----------------------------------------------------------------------===//
927 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
928 DS <op, outs, ins, asm, pat> {
931 // Single load interpret the 2 i8imm operands as a single i16 offset.
932 let offset0 = offset{7-0};
933 let offset1 = offset{15-8};
936 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
938 (outs regClass:$vdst),
939 (ins i1imm:$gds, VReg_32:$addr, ds_offset:$offset),
940 asm#" $vdst, $addr"#"$offset"#" [M0]",
948 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
950 (outs regClass:$vdst),
951 (ins i1imm:$gds, VReg_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1),
952 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
960 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
963 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, ds_offset:$offset),
964 asm#" $addr, $data0"#"$offset"#" [M0]",
972 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
975 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
976 ds_offset0:$offset0, ds_offset1:$offset1),
977 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
984 // 1 address, 1 data.
985 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
988 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),
989 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,
990 AtomicNoRet<noRetOp, 1> {
996 let hasPostISelHook = 1; // Adjusted to no return version.
999 // 1 address, 2 data.
1000 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
1003 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),
1004 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1006 AtomicNoRet<noRetOp, 1> {
1010 let hasPostISelHook = 1; // Adjusted to no return version.
1013 // 1 address, 2 data.
1014 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1017 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),
1018 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1020 AtomicNoRet<noRetOp, 0> {
1025 // 1 address, 1 data.
1026 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1029 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),
1030 asm#" $addr, $data0"#"$offset"#" [M0]",
1032 AtomicNoRet<noRetOp, 0> {
1039 //===----------------------------------------------------------------------===//
1041 //===----------------------------------------------------------------------===//
1043 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1044 MTBUF <outs, ins, "", pattern>,
1045 SIMCInstr<opName, SISubtarget.NONE> {
1049 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1051 MTBUF <outs, ins, asm, []>,
1053 SIMCInstr<opName, SISubtarget.SI>;
1055 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1056 list<dag> pattern> {
1058 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1060 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1064 let mayStore = 1, mayLoad = 0 in {
1066 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1067 RegisterClass regClass> : MTBUF_m <
1069 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1070 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1071 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1072 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1073 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1076 } // mayStore = 1, mayLoad = 0
1078 let mayLoad = 1, mayStore = 0 in {
1080 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1081 RegisterClass regClass> : MTBUF_m <
1082 op, opName, (outs regClass:$dst),
1083 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1084 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1085 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1086 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1087 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1090 } // mayLoad = 1, mayStore = 0
1092 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1094 bit IsAddr64 = is_addr64;
1095 string OpName = NAME # suffix;
1098 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1099 : MUBUF <op, outs, ins, asm, pattern> {
1109 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1110 : MUBUF <op, outs, ins, asm, pattern> {
1120 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1121 ValueType vt, SDPatternOperator atomic> {
1123 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1125 // No return variants
1128 def _ADDR64 : MUBUFAtomicAddr64 <
1130 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1131 mbuf_offset:$offset, slc:$slc),
1132 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1133 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1135 def _OFFSET : MUBUFAtomicOffset <
1137 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1138 SSrc_32:$soffset, slc:$slc),
1139 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1140 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1143 // Variant that return values
1144 let glc = 1, Constraints = "$vdata = $vdata_in",
1145 DisableEncoding = "$vdata_in" in {
1147 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1148 op, (outs rc:$vdata),
1149 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1150 mbuf_offset:$offset, slc:$slc),
1151 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1153 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1154 i1:$slc), vt:$vdata_in))]
1155 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1157 def _RTN_OFFSET : MUBUFAtomicOffset <
1158 op, (outs rc:$vdata),
1159 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1160 SSrc_32:$soffset, slc:$slc),
1161 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1163 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1164 i1:$slc), vt:$vdata_in))]
1165 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1169 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1172 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1173 ValueType load_vt = i32,
1174 SDPatternOperator ld = null_frag> {
1176 let lds = 0, mayLoad = 1 in {
1180 let offen = 0, idxen = 0, vaddr = 0 in {
1181 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1182 (ins SReg_128:$srsrc,
1183 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1184 slc:$slc, tfe:$tfe),
1185 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1186 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1187 i32:$soffset, i16:$offset,
1188 i1:$glc, i1:$slc, i1:$tfe)))]>,
1189 MUBUFAddr64Table<0>;
1192 let offen = 1, idxen = 0 in {
1193 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1194 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1195 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1197 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1200 let offen = 0, idxen = 1 in {
1201 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1202 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1203 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1204 slc:$slc, tfe:$tfe),
1205 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1208 let offen = 1, idxen = 1 in {
1209 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1210 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1211 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1212 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1216 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1217 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1218 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1219 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1220 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1221 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1226 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1227 ValueType store_vt, SDPatternOperator st> {
1229 let addr64 = 0, lds = 0 in {
1233 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1234 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1236 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1237 "$glc"#"$slc"#"$tfe",
1241 let offen = 0, idxen = 0, vaddr = 0 in {
1242 def _OFFSET : MUBUF <
1244 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1245 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1246 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1247 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1248 i16:$offset, i1:$glc, i1:$slc,
1250 >, MUBUFAddr64Table<0>;
1251 } // offen = 0, idxen = 0, vaddr = 0
1253 let offen = 1, idxen = 0 in {
1254 def _OFFEN : MUBUF <
1256 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1257 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1258 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1259 "$glc"#"$slc"#"$tfe",
1262 } // end offen = 1, idxen = 0
1264 } // End addr64 = 0, lds = 0
1266 def _ADDR64 : MUBUF <
1268 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1269 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1270 [(st store_vt:$vdata,
1271 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1285 let soffset = 128; // ZERO
1289 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1290 FLAT <op, (outs regClass:$data),
1291 (ins VReg_64:$addr),
1292 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1299 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1300 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1301 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1313 class MIMG_Mask <string op, int channels> {
1315 int Channels = channels;
1318 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1319 RegisterClass dst_rc,
1320 RegisterClass src_rc> : MIMG <
1322 (outs dst_rc:$vdata),
1323 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1324 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1326 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1327 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1332 let hasPostISelHook = 1;
1335 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1336 RegisterClass dst_rc,
1338 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1339 MIMG_Mask<asm#"_V1", channels>;
1340 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1341 MIMG_Mask<asm#"_V2", channels>;
1342 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1343 MIMG_Mask<asm#"_V4", channels>;
1346 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1347 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1348 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1349 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1350 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1353 class MIMG_Sampler_Helper <bits<7> op, string asm,
1354 RegisterClass dst_rc,
1355 RegisterClass src_rc> : MIMG <
1357 (outs dst_rc:$vdata),
1358 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1359 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1360 SReg_256:$srsrc, SReg_128:$ssamp),
1361 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1362 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1366 let hasPostISelHook = 1;
1369 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1370 RegisterClass dst_rc,
1372 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1373 MIMG_Mask<asm#"_V1", channels>;
1374 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1375 MIMG_Mask<asm#"_V2", channels>;
1376 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1377 MIMG_Mask<asm#"_V4", channels>;
1378 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1379 MIMG_Mask<asm#"_V8", channels>;
1380 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1381 MIMG_Mask<asm#"_V16", channels>;
1384 multiclass MIMG_Sampler <bits<7> op, string asm> {
1385 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1386 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1387 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1388 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1391 class MIMG_Gather_Helper <bits<7> op, string asm,
1392 RegisterClass dst_rc,
1393 RegisterClass src_rc> : MIMG <
1395 (outs dst_rc:$vdata),
1396 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1397 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1398 SReg_256:$srsrc, SReg_128:$ssamp),
1399 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1400 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1405 // DMASK was repurposed for GATHER4. 4 components are always
1406 // returned and DMASK works like a swizzle - it selects
1407 // the component to fetch. The only useful DMASK values are
1408 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1409 // (red,red,red,red) etc.) The ISA document doesn't mention
1411 // Therefore, disable all code which updates DMASK by setting these two:
1413 let hasPostISelHook = 0;
1416 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1417 RegisterClass dst_rc,
1419 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1420 MIMG_Mask<asm#"_V1", channels>;
1421 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1422 MIMG_Mask<asm#"_V2", channels>;
1423 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1424 MIMG_Mask<asm#"_V4", channels>;
1425 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1426 MIMG_Mask<asm#"_V8", channels>;
1427 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1428 MIMG_Mask<asm#"_V16", channels>;
1431 multiclass MIMG_Gather <bits<7> op, string asm> {
1432 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1433 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1434 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1435 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1438 //===----------------------------------------------------------------------===//
1439 // Vector instruction mappings
1440 //===----------------------------------------------------------------------===//
1442 // Maps an opcode in e32 form to its e64 equivalent
1443 def getVOPe64 : InstrMapping {
1444 let FilterClass = "VOP";
1445 let RowFields = ["OpName"];
1446 let ColFields = ["Size"];
1448 let ValueCols = [["8"]];
1451 // Maps an opcode in e64 form to its e32 equivalent
1452 def getVOPe32 : InstrMapping {
1453 let FilterClass = "VOP";
1454 let RowFields = ["OpName"];
1455 let ColFields = ["Size"];
1457 let ValueCols = [["4"]];
1460 // Maps an original opcode to its commuted version
1461 def getCommuteRev : InstrMapping {
1462 let FilterClass = "VOP2_REV";
1463 let RowFields = ["RevOp"];
1464 let ColFields = ["IsOrig"];
1466 let ValueCols = [["0"]];
1469 def getMaskedMIMGOp : InstrMapping {
1470 let FilterClass = "MIMG_Mask";
1471 let RowFields = ["Op"];
1472 let ColFields = ["Channels"];
1474 let ValueCols = [["1"], ["2"], ["3"] ];
1477 // Maps an commuted opcode to its original version
1478 def getCommuteOrig : InstrMapping {
1479 let FilterClass = "VOP2_REV";
1480 let RowFields = ["RevOp"];
1481 let ColFields = ["IsOrig"];
1483 let ValueCols = [["1"]];
1486 def isDS : InstrMapping {
1487 let FilterClass = "DS";
1488 let RowFields = ["Inst"];
1489 let ColFields = ["Size"];
1491 let ValueCols = [["8"]];
1494 def getMCOpcode : InstrMapping {
1495 let FilterClass = "SIMCInstr";
1496 let RowFields = ["PseudoInstr"];
1497 let ColFields = ["Subtarget"];
1498 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1499 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1502 def getAddr64Inst : InstrMapping {
1503 let FilterClass = "MUBUFAddr64Table";
1504 let RowFields = ["OpName"];
1505 let ColFields = ["IsAddr64"];
1507 let ValueCols = [["1"]];
1510 // Maps an atomic opcode to its version with a return value.
1511 def getAtomicRetOp : InstrMapping {
1512 let FilterClass = "AtomicNoRet";
1513 let RowFields = ["NoRetOp"];
1514 let ColFields = ["IsRet"];
1516 let ValueCols = [["1"]];
1519 // Maps an atomic opcode to its returnless version.
1520 def getAtomicNoRetOp : InstrMapping {
1521 let FilterClass = "AtomicNoRet";
1522 let RowFields = ["NoRetOp"];
1523 let ColFields = ["IsRet"];
1525 let ValueCols = [["0"]];
1528 include "SIInstructions.td"