1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
14 class vop1 <bits<8> si> : vop {
15 field bits<8> SI = si;
17 field bits<9> SI3 = {1, 1, si{6-0}};
20 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
21 // in AMDGPUMCInstLower.h
27 //===----------------------------------------------------------------------===//
29 //===----------------------------------------------------------------------===//
31 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
32 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
33 [SDNPMayLoad, SDNPMemOperand]
36 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
38 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
39 SDTCisVT<1, iAny>, // vdata(VGPR)
40 SDTCisVT<2, i32>, // num_channels(imm)
41 SDTCisVT<3, i32>, // vaddr(VGPR)
42 SDTCisVT<4, i32>, // soffset(SGPR)
43 SDTCisVT<5, i32>, // inst_offset(imm)
44 SDTCisVT<6, i32>, // dfmt(imm)
45 SDTCisVT<7, i32>, // nfmt(imm)
46 SDTCisVT<8, i32>, // offen(imm)
47 SDTCisVT<9, i32>, // idxen(imm)
48 SDTCisVT<10, i32>, // glc(imm)
49 SDTCisVT<11, i32>, // slc(imm)
50 SDTCisVT<12, i32> // tfe(imm)
52 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
55 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
56 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
60 class SDSample<string opcode> : SDNode <opcode,
61 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
62 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
65 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
66 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
67 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
68 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
70 def SIconstdata_ptr : SDNode<
71 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
74 // Transformation function, extract the lower 32bit of a 64bit immediate
75 def LO32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
79 def LO32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 // Transformation function, extract the upper 32bit of a 64bit immediate
85 def HI32 : SDNodeXForm<imm, [{
86 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
89 def HI32f : SDNodeXForm<fpimm, [{
90 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
91 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
94 def IMM8bitDWORD : PatLeaf <(imm),
95 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
98 def as_dword_i32imm : SDNodeXForm<imm, [{
99 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
102 def as_i1imm : SDNodeXForm<imm, [{
103 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
106 def as_i8imm : SDNodeXForm<imm, [{
107 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
110 def as_i16imm : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
114 def as_i32imm: SDNodeXForm<imm, [{
115 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
118 def IMM8bit : PatLeaf <(imm),
119 [{return isUInt<8>(N->getZExtValue());}]
122 def IMM12bit : PatLeaf <(imm),
123 [{return isUInt<12>(N->getZExtValue());}]
126 def IMM16bit : PatLeaf <(imm),
127 [{return isUInt<16>(N->getZExtValue());}]
130 def IMM32bit : PatLeaf <(imm),
131 [{return isUInt<32>(N->getZExtValue());}]
134 def mubuf_vaddr_offset : PatFrag<
135 (ops node:$ptr, node:$offset, node:$imm_offset),
136 (add (add node:$ptr, node:$offset), node:$imm_offset)
139 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
140 return isInlineImmediate(N);
143 class SGPRImm <dag frag> : PatLeaf<frag, [{
144 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
145 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
148 const SIRegisterInfo *SIRI =
149 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
150 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
152 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
159 //===----------------------------------------------------------------------===//
161 //===----------------------------------------------------------------------===//
163 def FRAMEri32 : Operand<iPTR> {
164 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
167 def sopp_brtarget : Operand<OtherVT> {
168 let EncoderMethod = "getSOPPBrEncoding";
169 let OperandType = "OPERAND_PCREL";
172 include "SIInstrFormats.td"
174 let OperandType = "OPERAND_IMMEDIATE" in {
176 def offen : Operand<i1> {
177 let PrintMethod = "printOffen";
179 def idxen : Operand<i1> {
180 let PrintMethod = "printIdxen";
182 def addr64 : Operand<i1> {
183 let PrintMethod = "printAddr64";
185 def mbuf_offset : Operand<i16> {
186 let PrintMethod = "printMBUFOffset";
188 def glc : Operand <i1> {
189 let PrintMethod = "printGLC";
191 def slc : Operand <i1> {
192 let PrintMethod = "printSLC";
194 def tfe : Operand <i1> {
195 let PrintMethod = "printTFE";
198 def omod : Operand <i32> {
199 let PrintMethod = "printOModSI";
202 def ClampMod : Operand <i1> {
203 let PrintMethod = "printClampSI";
206 } // End OperandType = "OPERAND_IMMEDIATE"
208 //===----------------------------------------------------------------------===//
210 //===----------------------------------------------------------------------===//
212 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
213 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
215 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
216 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
217 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
218 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
219 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
220 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
222 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
223 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
225 //===----------------------------------------------------------------------===//
226 // SI assembler operands
227 //===----------------------------------------------------------------------===//
247 //===----------------------------------------------------------------------===//
249 // SI Instruction multiclass helpers.
251 // Instructions with _32 take 32-bit operands.
252 // Instructions with _64 take 64-bit operands.
254 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
255 // encoding is the standard encoding, but instruction that make use of
256 // any of the instruction modifiers must use the 64-bit encoding.
258 // Instructions with _e32 use the 32-bit encoding.
259 // Instructions with _e64 use the 64-bit encoding.
261 //===----------------------------------------------------------------------===//
263 class SIMCInstr <string pseudo, int subtarget> {
264 string PseudoInstr = pseudo;
265 int Subtarget = subtarget;
268 //===----------------------------------------------------------------------===//
270 //===----------------------------------------------------------------------===//
272 class EXPCommon : InstSI<
274 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
275 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
276 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
285 let isPseudo = 1 in {
286 def "" : EXPCommon, SIMCInstr <"EXP", SISubtarget.NONE> ;
289 def _si : EXPCommon, SIMCInstr <"EXP", SISubtarget.SI>, EXPe;
292 //===----------------------------------------------------------------------===//
294 //===----------------------------------------------------------------------===//
296 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
297 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
298 opName#" $dst, $src0", pattern
301 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
302 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
303 opName#" $dst, $src0", pattern
306 // 64-bit input, 32-bit output.
307 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
308 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
309 opName#" $dst, $src0", pattern
312 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
313 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
314 opName#" $dst, $src0, $src1", pattern
317 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
318 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
319 opName#" $dst, $src0, $src1", pattern
322 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
323 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
324 opName#" $dst, $src0, $src1", pattern
328 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
329 string opName, PatLeaf cond> : SOPC <
330 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
331 opName#" $dst, $src0, $src1", []>;
333 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
334 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
336 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
337 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
339 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
340 op, (outs SReg_32:$dst), (ins i16imm:$src0),
341 opName#" $dst, $src0", pattern
344 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
345 op, (outs SReg_64:$dst), (ins i16imm:$src0),
346 opName#" $dst, $src0", pattern
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
354 SMRD <outs, ins, "", pattern>,
355 SIMCInstr<opName, SISubtarget.NONE> {
359 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
361 SMRD <outs, ins, asm, []>,
363 SIMCInstr<opName, SISubtarget.SI>;
365 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
366 string asm, list<dag> pattern> {
368 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
370 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
374 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
375 RegisterClass dstClass> {
377 op, opName#"_IMM", 1, (outs dstClass:$dst),
378 (ins baseClass:$sbase, u32imm:$offset),
379 opName#" $dst, $sbase, $offset", []
382 defm _SGPR : SMRD_m <
383 op, opName#"_SGPR", 0, (outs dstClass:$dst),
384 (ins baseClass:$sbase, SReg_32:$soff),
385 opName#" $dst, $sbase, $soff", []
389 //===----------------------------------------------------------------------===//
390 // Vector ALU classes
391 //===----------------------------------------------------------------------===//
393 // This must always be right before the operand being input modified.
394 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
395 let PrintMethod = "printOperandAndMods";
397 def InputModsNoDefault : Operand <i32> {
398 let PrintMethod = "printOperandAndMods";
401 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
403 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
404 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
408 // Returns the register class to use for the destination of VOP[123C]
409 // instructions for the given VT.
410 class getVALUDstForVT<ValueType VT> {
411 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
414 // Returns the register class to use for source 0 of VOP[12C]
415 // instructions for the given VT.
416 class getVOPSrc0ForVT<ValueType VT> {
417 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
420 // Returns the register class to use for source 1 of VOP[12C] for the
422 class getVOPSrc1ForVT<ValueType VT> {
423 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
426 // Returns the register classes for the source arguments of a VOP[12C]
427 // instruction for the given SrcVTs.
428 class getInRC32 <list<ValueType> SrcVT> {
429 list<RegisterClass> ret = [
430 getVOPSrc0ForVT<SrcVT[0]>.ret,
431 getVOPSrc1ForVT<SrcVT[1]>.ret
435 // Returns the register class to use for sources of VOP3 instructions for the
437 class getVOP3SrcForVT<ValueType VT> {
438 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
441 // Returns the register classes for the source arguments of a VOP3
442 // instruction for the given SrcVTs.
443 class getInRC64 <list<ValueType> SrcVT> {
444 list<RegisterClass> ret = [
445 getVOP3SrcForVT<SrcVT[0]>.ret,
446 getVOP3SrcForVT<SrcVT[1]>.ret,
447 getVOP3SrcForVT<SrcVT[2]>.ret
451 // Returns 1 if the source arguments have modifiers, 0 if they do not.
452 class hasModifiers<ValueType SrcVT> {
453 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
454 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
457 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
458 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
459 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
460 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
464 // Returns the input arguments for VOP3 instructions for the given SrcVT.
465 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
466 RegisterClass Src2RC, int NumSrcArgs,
470 !if (!eq(NumSrcArgs, 1),
471 !if (!eq(HasModifiers, 1),
472 // VOP1 with modifiers
473 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
474 ClampMod:$clamp, omod:$omod)
476 // VOP1 without modifiers
479 !if (!eq(NumSrcArgs, 2),
480 !if (!eq(HasModifiers, 1),
481 // VOP 2 with modifiers
482 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
483 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
484 ClampMod:$clamp, omod:$omod)
486 // VOP2 without modifiers
487 (ins Src0RC:$src0, Src1RC:$src1)
489 /* NumSrcArgs == 3 */,
490 !if (!eq(HasModifiers, 1),
491 // VOP3 with modifiers
492 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
493 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
494 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
495 ClampMod:$clamp, omod:$omod)
497 // VOP3 without modifiers
498 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
502 // Returns the assembly string for the inputs and outputs of a VOP[12C]
503 // instruction. This does not add the _e32 suffix, so it can be reused
505 class getAsm32 <int NumSrcArgs> {
506 string src1 = ", $src1";
507 string src2 = ", $src2";
508 string ret = " $dst, $src0"#
509 !if(!eq(NumSrcArgs, 1), "", src1)#
510 !if(!eq(NumSrcArgs, 3), src2, "");
513 // Returns the assembly string for the inputs and outputs of a VOP3
515 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
516 string src0 = "$src0_modifiers,";
517 string src1 = !if(!eq(NumSrcArgs, 1), "",
518 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
519 " $src1_modifiers,"));
520 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
522 !if(!eq(HasModifiers, 0),
523 getAsm32<NumSrcArgs>.ret,
524 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
528 class VOPProfile <list<ValueType> _ArgVT> {
530 field list<ValueType> ArgVT = _ArgVT;
532 field ValueType DstVT = ArgVT[0];
533 field ValueType Src0VT = ArgVT[1];
534 field ValueType Src1VT = ArgVT[2];
535 field ValueType Src2VT = ArgVT[3];
536 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
537 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
538 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
539 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
540 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
541 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
543 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
544 field bit HasModifiers = hasModifiers<Src0VT>.ret;
546 field dag Outs = (outs DstRC:$dst);
548 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
549 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
552 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
553 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
556 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
557 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
558 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
559 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
560 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
561 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
562 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
563 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
564 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
566 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
567 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
568 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
569 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
570 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
571 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
572 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
573 let Src0RC32 = VCSrc_32;
575 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
576 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
578 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
579 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
580 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
581 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
584 class VOP <string opName> {
585 string OpName = opName;
588 class VOP2_REV <string revOp, bit isOrig> {
589 string RevOp = revOp;
593 class AtomicNoRet <string noRetOp, bit isRet> {
594 string NoRetOp = noRetOp;
598 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
599 VOP1Common <outs, ins, "", pattern>,
600 SIMCInstr<opName, SISubtarget.NONE> {
604 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
606 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
608 def _si : VOP1<op.SI, outs, ins, asm, []>,
609 SIMCInstr <opName, SISubtarget.SI>;
612 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
614 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
615 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
616 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
617 bits<2> omod = !if(HasModifiers, ?, 0);
618 bits<1> clamp = !if(HasModifiers, ?, 0);
619 bits<9> src1 = !if(HasSrc1, ?, 0);
620 bits<9> src2 = !if(HasSrc2, ?, 0);
623 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
624 VOP3Common <outs, ins, "", pattern>,
626 SIMCInstr<opName, SISubtarget.NONE> {
630 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
631 VOP3 <op, outs, ins, asm, []>,
632 SIMCInstr<opName, SISubtarget.SI>;
634 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
635 string opName, int NumSrcArgs, bit HasMods = 1> {
637 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
639 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
640 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
641 !if(!eq(NumSrcArgs, 2), 0, 1),
646 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
647 list<dag> pattern, string opName, bit HasMods = 1> {
649 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
651 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
652 VOP3DisableFields<0, 0, HasMods>;
655 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
656 list<dag> pattern, string opName, string revOp,
657 bit HasMods = 1, bit UseFullOp = 0> {
659 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
660 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
662 def _si : VOP3_Real_si <op,
663 outs, ins, asm, opName>,
664 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
665 VOP3DisableFields<1, 0, HasMods>;
668 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
669 list<dag> pattern, string opName, string revOp,
670 bit HasMods = 1, bit UseFullOp = 0> {
671 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
672 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
674 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
675 // can write it into any SGPR. We currently don't use the carry out,
676 // so for now hardcode it to VCC as well.
677 let sdst = SIOperand.VCC, Defs = [VCC] in {
678 def _si : VOP3b <op, outs, ins, asm, pattern>,
679 VOP3DisableFields<1, 0, HasMods>,
680 SIMCInstr<opName, SISubtarget.SI>,
681 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
682 } // End sdst = SIOperand.VCC, Defs = [VCC]
685 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
686 list<dag> pattern, string opName,
687 bit HasMods, bit defExec> {
689 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
691 def _si : VOP3_Real_si <
692 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
693 outs, ins, asm, opName>,
694 VOP3DisableFields<1, 0, HasMods> {
695 let Defs = !if(defExec, [EXEC], []);
699 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
700 dag ins32, string asm32, list<dag> pat32,
701 dag ins64, string asm64, list<dag> pat64,
704 def _e32 : VOP1 <op.SI, outs, ins32, opName#asm32, pat32>, VOP<opName>;
706 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
709 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
710 SDPatternOperator node = null_frag> : VOP1_Helper <
712 P.Ins32, P.Asm32, [],
715 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
716 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
717 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
721 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
722 list<dag> pattern, string revOp> :
723 VOP2 <op, outs, ins, opName#asm, pattern>,
725 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
727 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
728 dag ins32, string asm32, list<dag> pat32,
729 dag ins64, string asm64, list<dag> pat64,
730 string revOp, bit HasMods> {
731 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
733 defm _e64 : VOP3_2_m <
734 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
735 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
739 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
740 SDPatternOperator node = null_frag,
741 string revOp = opName> : VOP2_Helper <
743 P.Ins32, P.Asm32, [],
747 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
748 i1:$clamp, i32:$omod)),
749 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
750 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
751 revOp, P.HasModifiers
754 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
755 dag ins32, string asm32, list<dag> pat32,
756 dag ins64, string asm64, list<dag> pat64,
757 string revOp, bit HasMods> {
759 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
761 defm _e64 : VOP3b_2_m <
762 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
763 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
767 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
768 SDPatternOperator node = null_frag,
769 string revOp = opName> : VOP2b_Helper <
771 P.Ins32, P.Asm32, [],
775 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
776 i1:$clamp, i32:$omod)),
777 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
778 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
779 revOp, P.HasModifiers
782 multiclass VOPC_Helper <bits<8> op, string opName,
783 dag ins32, string asm32, list<dag> pat32,
784 dag out64, dag ins64, string asm64, list<dag> pat64,
785 bit HasMods, bit DefExec> {
786 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
787 let Defs = !if(DefExec, [EXEC], []);
790 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
794 multiclass VOPCInst <bits<8> op, string opName,
795 VOPProfile P, PatLeaf cond = COND_NULL,
796 bit DefExec = 0> : VOPC_Helper <
798 P.Ins32, P.Asm32, [],
799 (outs SReg_64:$dst), P.Ins64, P.Asm64,
802 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
803 i1:$clamp, i32:$omod)),
804 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
806 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
807 P.HasModifiers, DefExec
810 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
811 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
813 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
814 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
816 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
817 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
819 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
820 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
823 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
824 PatLeaf cond = COND_NULL>
825 : VOPCInst <op, opName, P, cond, 1>;
827 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
828 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
830 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
831 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
833 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
834 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
836 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
837 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
839 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
840 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
841 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
844 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
845 SDPatternOperator node = null_frag> : VOP3_Helper <
846 op, opName, P.Outs, P.Ins64, P.Asm64,
847 !if(!eq(P.NumSrcArgs, 3),
850 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
851 i1:$clamp, i32:$omod)),
852 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
853 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
854 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
856 !if(!eq(P.NumSrcArgs, 2),
859 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
860 i1:$clamp, i32:$omod)),
861 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
862 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
863 /* P.NumSrcArgs == 1 */,
866 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
867 i1:$clamp, i32:$omod))))],
868 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
869 P.NumSrcArgs, P.HasModifiers
872 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
873 string opName, list<dag> pattern> :
875 op, (outs vrc:$dst0, SReg_64:$dst1),
876 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
877 InputModsNoDefault:$src1_modifiers, arc:$src1,
878 InputModsNoDefault:$src2_modifiers, arc:$src2,
879 ClampMod:$clamp, i32imm:$omod),
880 opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
884 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
885 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
887 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
888 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
891 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
892 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
893 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
894 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
895 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
896 i32:$src1_modifiers, P.Src1VT:$src1,
897 i32:$src2_modifiers, P.Src2VT:$src2,
901 //===----------------------------------------------------------------------===//
902 // Vector I/O classes
903 //===----------------------------------------------------------------------===//
905 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
906 DS <op, outs, ins, asm, pat> {
909 // Single load interpret the 2 i8imm operands as a single i16 offset.
910 let offset0 = offset{7-0};
911 let offset1 = offset{15-8};
914 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
916 (outs regClass:$vdst),
917 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
918 asm#" $vdst, $addr, $offset, [M0]",
926 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
928 (outs regClass:$vdst),
929 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
930 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
938 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
941 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
942 asm#" $addr, $data0, $offset [M0]",
950 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
953 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
954 u8imm:$offset0, u8imm:$offset1),
955 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
962 // 1 address, 1 data.
963 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
966 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
967 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
968 AtomicNoRet<noRetOp, 1> {
974 let hasPostISelHook = 1; // Adjusted to no return version.
977 // 1 address, 2 data.
978 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
981 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
982 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
984 AtomicNoRet<noRetOp, 1> {
988 let hasPostISelHook = 1; // Adjusted to no return version.
991 // 1 address, 2 data.
992 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
995 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
996 asm#" $addr, $data0, $data1, $offset, [M0]",
998 AtomicNoRet<noRetOp, 0> {
1003 // 1 address, 1 data.
1004 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1007 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
1008 asm#" $addr, $data0, $offset, [M0]",
1010 AtomicNoRet<noRetOp, 0> {
1017 //===----------------------------------------------------------------------===//
1019 //===----------------------------------------------------------------------===//
1021 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1022 MTBUF <outs, ins, "", pattern>,
1023 SIMCInstr<opName, SISubtarget.NONE> {
1027 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1029 MTBUF <outs, ins, asm, []>,
1031 SIMCInstr<opName, SISubtarget.SI>;
1033 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1034 list<dag> pattern> {
1036 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1038 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1042 let mayStore = 1, mayLoad = 0 in {
1044 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1045 RegisterClass regClass> : MTBUF_m <
1047 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1048 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1049 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1050 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1051 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1054 } // mayStore = 1, mayLoad = 0
1056 let mayLoad = 1, mayStore = 0 in {
1058 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1059 RegisterClass regClass> : MTBUF_m <
1060 op, opName, (outs regClass:$dst),
1061 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1062 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1063 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1064 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1065 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1068 } // mayLoad = 1, mayStore = 0
1070 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1072 bit IsAddr64 = is_addr64;
1073 string OpName = NAME # suffix;
1076 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1077 : MUBUF <op, outs, ins, asm, pattern> {
1087 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1088 : MUBUF <op, outs, ins, asm, pattern> {
1098 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1099 ValueType vt, SDPatternOperator atomic> {
1101 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1103 // No return variants
1106 def _ADDR64 : MUBUFAtomicAddr64 <
1108 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1109 mbuf_offset:$offset, slc:$slc),
1110 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1111 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1113 def _OFFSET : MUBUFAtomicOffset <
1115 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1116 SSrc_32:$soffset, slc:$slc),
1117 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1118 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1121 // Variant that return values
1122 let glc = 1, Constraints = "$vdata = $vdata_in",
1123 DisableEncoding = "$vdata_in" in {
1125 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1126 op, (outs rc:$vdata),
1127 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1128 mbuf_offset:$offset, slc:$slc),
1129 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1131 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1132 i1:$slc), vt:$vdata_in))]
1133 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1135 def _RTN_OFFSET : MUBUFAtomicOffset <
1136 op, (outs rc:$vdata),
1137 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1138 SSrc_32:$soffset, slc:$slc),
1139 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1141 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1142 i1:$slc), vt:$vdata_in))]
1143 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1147 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1150 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1151 ValueType load_vt = i32,
1152 SDPatternOperator ld = null_frag> {
1154 let lds = 0, mayLoad = 1 in {
1158 let offen = 0, idxen = 0, vaddr = 0 in {
1159 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1160 (ins SReg_128:$srsrc,
1161 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1162 slc:$slc, tfe:$tfe),
1163 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1164 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1165 i32:$soffset, i16:$offset,
1166 i1:$glc, i1:$slc, i1:$tfe)))]>,
1167 MUBUFAddr64Table<0>;
1170 let offen = 1, idxen = 0 in {
1171 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1172 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1173 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1175 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1178 let offen = 0, idxen = 1 in {
1179 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1180 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1181 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1182 slc:$slc, tfe:$tfe),
1183 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1186 let offen = 1, idxen = 1 in {
1187 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1188 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1189 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1190 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1194 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1195 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1196 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1197 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1198 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1199 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1204 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1205 ValueType store_vt, SDPatternOperator st> {
1207 let addr64 = 0, lds = 0 in {
1211 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1212 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1214 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1215 "$glc"#"$slc"#"$tfe",
1219 let offen = 0, idxen = 0, vaddr = 0 in {
1220 def _OFFSET : MUBUF <
1222 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1223 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1224 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1225 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1226 i16:$offset, i1:$glc, i1:$slc,
1228 >, MUBUFAddr64Table<0>;
1229 } // offen = 0, idxen = 0, vaddr = 0
1231 let offen = 1, idxen = 0 in {
1232 def _OFFEN : MUBUF <
1234 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1235 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1236 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1237 "$glc"#"$slc"#"$tfe",
1240 } // end offen = 1, idxen = 0
1242 } // End addr64 = 0, lds = 0
1244 def _ADDR64 : MUBUF <
1246 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1247 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1248 [(st store_vt:$vdata,
1249 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1263 let soffset = 128; // ZERO
1267 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1268 FLAT <op, (outs regClass:$data),
1269 (ins VReg_64:$addr),
1270 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1277 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1278 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1279 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1291 class MIMG_Mask <string op, int channels> {
1293 int Channels = channels;
1296 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1297 RegisterClass dst_rc,
1298 RegisterClass src_rc> : MIMG <
1300 (outs dst_rc:$vdata),
1301 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1302 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1304 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1305 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1310 let hasPostISelHook = 1;
1313 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1314 RegisterClass dst_rc,
1316 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1317 MIMG_Mask<asm#"_V1", channels>;
1318 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1319 MIMG_Mask<asm#"_V2", channels>;
1320 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1321 MIMG_Mask<asm#"_V4", channels>;
1324 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1325 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1326 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1327 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1328 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1331 class MIMG_Sampler_Helper <bits<7> op, string asm,
1332 RegisterClass dst_rc,
1333 RegisterClass src_rc> : MIMG <
1335 (outs dst_rc:$vdata),
1336 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1337 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1338 SReg_256:$srsrc, SReg_128:$ssamp),
1339 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1340 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1344 let hasPostISelHook = 1;
1347 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1348 RegisterClass dst_rc,
1350 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1351 MIMG_Mask<asm#"_V1", channels>;
1352 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1353 MIMG_Mask<asm#"_V2", channels>;
1354 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1355 MIMG_Mask<asm#"_V4", channels>;
1356 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1357 MIMG_Mask<asm#"_V8", channels>;
1358 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1359 MIMG_Mask<asm#"_V16", channels>;
1362 multiclass MIMG_Sampler <bits<7> op, string asm> {
1363 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1364 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1365 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1366 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1369 class MIMG_Gather_Helper <bits<7> op, string asm,
1370 RegisterClass dst_rc,
1371 RegisterClass src_rc> : MIMG <
1373 (outs dst_rc:$vdata),
1374 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1375 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1376 SReg_256:$srsrc, SReg_128:$ssamp),
1377 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1378 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1383 // DMASK was repurposed for GATHER4. 4 components are always
1384 // returned and DMASK works like a swizzle - it selects
1385 // the component to fetch. The only useful DMASK values are
1386 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1387 // (red,red,red,red) etc.) The ISA document doesn't mention
1389 // Therefore, disable all code which updates DMASK by setting these two:
1391 let hasPostISelHook = 0;
1394 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1395 RegisterClass dst_rc,
1397 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1398 MIMG_Mask<asm#"_V1", channels>;
1399 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1400 MIMG_Mask<asm#"_V2", channels>;
1401 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1402 MIMG_Mask<asm#"_V4", channels>;
1403 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1404 MIMG_Mask<asm#"_V8", channels>;
1405 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1406 MIMG_Mask<asm#"_V16", channels>;
1409 multiclass MIMG_Gather <bits<7> op, string asm> {
1410 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1411 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1412 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1413 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1416 //===----------------------------------------------------------------------===//
1417 // Vector instruction mappings
1418 //===----------------------------------------------------------------------===//
1420 // Maps an opcode in e32 form to its e64 equivalent
1421 def getVOPe64 : InstrMapping {
1422 let FilterClass = "VOP";
1423 let RowFields = ["OpName"];
1424 let ColFields = ["Size"];
1426 let ValueCols = [["8"]];
1429 // Maps an opcode in e64 form to its e32 equivalent
1430 def getVOPe32 : InstrMapping {
1431 let FilterClass = "VOP";
1432 let RowFields = ["OpName"];
1433 let ColFields = ["Size"];
1435 let ValueCols = [["4"]];
1438 // Maps an original opcode to its commuted version
1439 def getCommuteRev : InstrMapping {
1440 let FilterClass = "VOP2_REV";
1441 let RowFields = ["RevOp"];
1442 let ColFields = ["IsOrig"];
1444 let ValueCols = [["0"]];
1447 def getMaskedMIMGOp : InstrMapping {
1448 let FilterClass = "MIMG_Mask";
1449 let RowFields = ["Op"];
1450 let ColFields = ["Channels"];
1452 let ValueCols = [["1"], ["2"], ["3"] ];
1455 // Maps an commuted opcode to its original version
1456 def getCommuteOrig : InstrMapping {
1457 let FilterClass = "VOP2_REV";
1458 let RowFields = ["RevOp"];
1459 let ColFields = ["IsOrig"];
1461 let ValueCols = [["1"]];
1464 def isDS : InstrMapping {
1465 let FilterClass = "DS";
1466 let RowFields = ["Inst"];
1467 let ColFields = ["Size"];
1469 let ValueCols = [["8"]];
1472 def getMCOpcode : InstrMapping {
1473 let FilterClass = "SIMCInstr";
1474 let RowFields = ["PseudoInstr"];
1475 let ColFields = ["Subtarget"];
1476 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1477 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1480 def getAddr64Inst : InstrMapping {
1481 let FilterClass = "MUBUFAddr64Table";
1482 let RowFields = ["OpName"];
1483 let ColFields = ["IsAddr64"];
1485 let ValueCols = [["1"]];
1488 // Maps an atomic opcode to its version with a return value.
1489 def getAtomicRetOp : InstrMapping {
1490 let FilterClass = "AtomicNoRet";
1491 let RowFields = ["NoRetOp"];
1492 let ColFields = ["IsRet"];
1494 let ValueCols = [["1"]];
1497 // Maps an atomic opcode to its returnless version.
1498 def getAtomicNoRetOp : InstrMapping {
1499 let FilterClass = "AtomicNoRet";
1500 let RowFields = ["NoRetOp"];
1501 let ColFields = ["IsRet"];
1503 let ValueCols = [["0"]];
1506 include "SIInstructions.td"