1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 let OperandType = "OPERAND_IMMEDIATE" in {
166 def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
169 def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
172 def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
175 def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
178 def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
181 def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
184 def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
188 def omod : Operand <i32> {
189 let PrintMethod = "printOModSI";
192 def ClampMod : Operand <i1> {
193 let PrintMethod = "printClampSI";
196 } // End OperandType = "OPERAND_IMMEDIATE"
198 //===----------------------------------------------------------------------===//
200 //===----------------------------------------------------------------------===//
202 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
203 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
205 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
206 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
207 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
208 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
209 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
210 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
212 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
213 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
215 //===----------------------------------------------------------------------===//
216 // SI assembler operands
217 //===----------------------------------------------------------------------===//
237 //===----------------------------------------------------------------------===//
239 // SI Instruction multiclass helpers.
241 // Instructions with _32 take 32-bit operands.
242 // Instructions with _64 take 64-bit operands.
244 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
245 // encoding is the standard encoding, but instruction that make use of
246 // any of the instruction modifiers must use the 64-bit encoding.
248 // Instructions with _e32 use the 32-bit encoding.
249 // Instructions with _e64 use the 64-bit encoding.
251 //===----------------------------------------------------------------------===//
253 //===----------------------------------------------------------------------===//
255 //===----------------------------------------------------------------------===//
257 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
258 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
259 opName#" $dst, $src0", pattern
262 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
263 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
264 opName#" $dst, $src0", pattern
267 // 64-bit input, 32-bit output.
268 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
269 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
270 opName#" $dst, $src0", pattern
273 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
274 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
275 opName#" $dst, $src0, $src1", pattern
278 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
279 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
280 opName#" $dst, $src0, $src1", pattern
283 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
284 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
285 opName#" $dst, $src0, $src1", pattern
289 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
290 string opName, PatLeaf cond> : SOPC <
291 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
292 opName#" $dst, $src0, $src1", []>;
294 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
295 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
297 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
298 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
300 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
301 op, (outs SReg_32:$dst), (ins i16imm:$src0),
302 opName#" $dst, $src0", pattern
305 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
306 op, (outs SReg_64:$dst), (ins i16imm:$src0),
307 opName#" $dst, $src0", pattern
310 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
311 RegisterClass dstClass> {
313 op, 1, (outs dstClass:$dst),
314 (ins baseClass:$sbase, u32imm:$offset),
315 asm#" $dst, $sbase, $offset", []
319 op, 0, (outs dstClass:$dst),
320 (ins baseClass:$sbase, SReg_32:$soff),
321 asm#" $dst, $sbase, $soff", []
325 //===----------------------------------------------------------------------===//
326 // Vector ALU classes
327 //===----------------------------------------------------------------------===//
329 // This must always be right before the operand being input modified.
330 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
331 let PrintMethod = "printOperandAndMods";
333 def InputModsNoDefault : Operand <i32> {
334 let PrintMethod = "printOperandAndMods";
337 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
339 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
340 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
344 // Returns the register class to use for the destination of VOP[123C]
345 // instructions for the given VT.
346 class getVALUDstForVT<ValueType VT> {
347 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
350 // Returns the register class to use for source 0 of VOP[12C]
351 // instructions for the given VT.
352 class getVOPSrc0ForVT<ValueType VT> {
353 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
356 // Returns the register class to use for source 1 of VOP[12C] for the
358 class getVOPSrc1ForVT<ValueType VT> {
359 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
362 // Returns the register classes for the source arguments of a VOP[12C]
363 // instruction for the given SrcVTs.
364 class getInRC32 <list<ValueType> SrcVT> {
365 list<RegisterClass> ret = [
366 getVOPSrc0ForVT<SrcVT[0]>.ret,
367 getVOPSrc1ForVT<SrcVT[1]>.ret
371 // Returns the register class to use for sources of VOP3 instructions for the
373 class getVOP3SrcForVT<ValueType VT> {
374 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
377 // Returns the register classes for the source arguments of a VOP3
378 // instruction for the given SrcVTs.
379 class getInRC64 <list<ValueType> SrcVT> {
380 list<RegisterClass> ret = [
381 getVOP3SrcForVT<SrcVT[0]>.ret,
382 getVOP3SrcForVT<SrcVT[1]>.ret,
383 getVOP3SrcForVT<SrcVT[2]>.ret
387 // Returns 1 if the source arguments have modifiers, 0 if they do not.
388 class hasModifiers<ValueType SrcVT> {
389 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
390 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
393 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
394 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
395 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
396 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
400 // Returns the input arguments for VOP3 instructions for the given SrcVT.
401 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
402 RegisterClass Src2RC, int NumSrcArgs,
406 !if (!eq(NumSrcArgs, 1),
407 !if (!eq(HasModifiers, 1),
408 // VOP1 with modifiers
409 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
410 ClampMod:$clamp, omod:$omod)
412 // VOP1 without modifiers
415 !if (!eq(NumSrcArgs, 2),
416 !if (!eq(HasModifiers, 1),
417 // VOP 2 with modifiers
418 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
419 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
420 ClampMod:$clamp, omod:$omod)
422 // VOP2 without modifiers
423 (ins Src0RC:$src0, Src1RC:$src1)
425 /* NumSrcArgs == 3 */,
426 !if (!eq(HasModifiers, 1),
427 // VOP3 with modifiers
428 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
429 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
430 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
431 ClampMod:$clamp, omod:$omod)
433 // VOP3 without modifiers
434 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
438 // Returns the assembly string for the inputs and outputs of a VOP[12C]
439 // instruction. This does not add the _e32 suffix, so it can be reused
441 class getAsm32 <int NumSrcArgs> {
442 string src1 = ", $src1";
443 string src2 = ", $src2";
444 string ret = " $dst, $src0"#
445 !if(!eq(NumSrcArgs, 1), "", src1)#
446 !if(!eq(NumSrcArgs, 3), src2, "");
449 // Returns the assembly string for the inputs and outputs of a VOP3
451 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
452 string src0 = "$src0_modifiers,";
453 string src1 = !if(!eq(NumSrcArgs, 1), "",
454 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
455 " $src1_modifiers,"));
456 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
458 !if(!eq(HasModifiers, 0),
459 getAsm32<NumSrcArgs>.ret,
460 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
464 class VOPProfile <list<ValueType> _ArgVT> {
466 field list<ValueType> ArgVT = _ArgVT;
468 field ValueType DstVT = ArgVT[0];
469 field ValueType Src0VT = ArgVT[1];
470 field ValueType Src1VT = ArgVT[2];
471 field ValueType Src2VT = ArgVT[3];
472 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
473 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
474 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
475 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
476 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
477 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
479 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
480 field bit HasModifiers = hasModifiers<Src0VT>.ret;
482 field dag Outs = (outs DstRC:$dst);
484 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
485 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
488 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
489 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
492 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
493 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
494 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
495 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
496 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
497 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
498 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
499 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
500 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
502 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
503 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
504 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
505 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
506 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
507 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
508 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
509 let Src0RC32 = VCSrc_32;
511 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
512 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
514 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
515 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
516 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
517 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
520 class VOP <string opName> {
521 string OpName = opName;
524 class VOP2_REV <string revOp, bit isOrig> {
525 string RevOp = revOp;
529 class AtomicNoRet <string noRetOp, bit isRet> {
530 string NoRetOp = noRetOp;
534 class SIMCInstr <string pseudo, int subtarget> {
535 string PseudoInstr = pseudo;
536 int Subtarget = subtarget;
539 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
541 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
542 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
543 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
544 bits<2> omod = !if(HasModifiers, ?, 0);
545 bits<1> clamp = !if(HasModifiers, ?, 0);
546 bits<9> src1 = !if(HasSrc1, ?, 0);
547 bits<9> src2 = !if(HasSrc2, ?, 0);
550 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
551 VOP3Common <outs, ins, "", pattern>,
553 SIMCInstr<opName, SISubtarget.NONE> {
557 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
558 VOP3 <op, outs, ins, asm, []>,
559 SIMCInstr<opName, SISubtarget.SI>;
561 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
562 string opName, int NumSrcArgs, bit HasMods = 1> {
564 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
566 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
567 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
568 !if(!eq(NumSrcArgs, 2), 0, 1),
573 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
574 list<dag> pattern, string opName, bit HasMods = 1> {
576 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
578 def _si : VOP3_Real_si <
579 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
580 outs, ins, asm, opName>,
581 VOP3DisableFields<0, 0, HasMods>;
584 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
585 list<dag> pattern, string opName, string revOp,
586 bit HasMods = 1, bit UseFullOp = 0> {
588 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
589 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
591 def _si : VOP3_Real_si <op,
592 outs, ins, asm, opName>,
593 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
594 VOP3DisableFields<1, 0, HasMods>;
597 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
598 list<dag> pattern, string opName, string revOp,
599 bit HasMods = 1, bit UseFullOp = 0> {
600 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
601 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
603 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
604 // can write it into any SGPR. We currently don't use the carry out,
605 // so for now hardcode it to VCC as well.
606 let sdst = SIOperand.VCC, Defs = [VCC] in {
607 def _si : VOP3b <op, outs, ins, asm, pattern>,
608 VOP3DisableFields<1, 0, HasMods>,
609 SIMCInstr<opName, SISubtarget.SI>,
610 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
611 } // End sdst = SIOperand.VCC, Defs = [VCC]
614 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
615 list<dag> pattern, string opName,
616 bit HasMods, bit defExec> {
618 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
620 def _si : VOP3_Real_si <
621 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
622 outs, ins, asm, opName>,
623 VOP3DisableFields<1, 0, HasMods> {
624 let Defs = !if(defExec, [EXEC], []);
628 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
629 dag ins32, string asm32, list<dag> pat32,
630 dag ins64, string asm64, list<dag> pat64,
633 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
635 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
638 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
639 SDPatternOperator node = null_frag> : VOP1_Helper <
641 P.Ins32, P.Asm32, [],
644 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
645 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
646 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
650 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
651 list<dag> pattern, string revOp> :
652 VOP2 <op, outs, ins, opName#asm, pattern>,
654 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
656 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
657 dag ins32, string asm32, list<dag> pat32,
658 dag ins64, string asm64, list<dag> pat64,
659 string revOp, bit HasMods> {
660 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
662 defm _e64 : VOP3_2_m <
663 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
664 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
668 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
669 SDPatternOperator node = null_frag,
670 string revOp = opName> : VOP2_Helper <
672 P.Ins32, P.Asm32, [],
676 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
677 i1:$clamp, i32:$omod)),
678 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
679 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
680 revOp, P.HasModifiers
683 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
684 dag ins32, string asm32, list<dag> pat32,
685 dag ins64, string asm64, list<dag> pat64,
686 string revOp, bit HasMods> {
688 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
690 defm _e64 : VOP3b_2_m <
691 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
692 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
696 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
697 SDPatternOperator node = null_frag,
698 string revOp = opName> : VOP2b_Helper <
700 P.Ins32, P.Asm32, [],
704 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
705 i1:$clamp, i32:$omod)),
706 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
707 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
708 revOp, P.HasModifiers
711 multiclass VOPC_Helper <bits<8> op, string opName,
712 dag ins32, string asm32, list<dag> pat32,
713 dag out64, dag ins64, string asm64, list<dag> pat64,
714 bit HasMods, bit DefExec> {
715 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
716 let Defs = !if(DefExec, [EXEC], []);
719 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
723 multiclass VOPCInst <bits<8> op, string opName,
724 VOPProfile P, PatLeaf cond = COND_NULL,
725 bit DefExec = 0> : VOPC_Helper <
727 P.Ins32, P.Asm32, [],
728 (outs SReg_64:$dst), P.Ins64, P.Asm64,
731 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
732 i1:$clamp, i32:$omod)),
733 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
735 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
736 P.HasModifiers, DefExec
739 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
740 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
742 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
743 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
745 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
746 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
748 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
749 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
752 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
753 PatLeaf cond = COND_NULL>
754 : VOPCInst <op, opName, P, cond, 1>;
756 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
757 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
759 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
760 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
762 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
763 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
765 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
766 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
768 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
769 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
770 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
773 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
774 SDPatternOperator node = null_frag> : VOP3_Helper <
775 op, opName, P.Outs, P.Ins64, P.Asm64,
776 !if(!eq(P.NumSrcArgs, 3),
779 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
780 i1:$clamp, i32:$omod)),
781 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
782 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
783 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
785 !if(!eq(P.NumSrcArgs, 2),
788 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
789 i1:$clamp, i32:$omod)),
790 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
791 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
792 /* P.NumSrcArgs == 1 */,
795 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
796 i1:$clamp, i32:$omod))))],
797 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
798 P.NumSrcArgs, P.HasModifiers
801 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
802 string opName, list<dag> pattern> :
804 op, (outs vrc:$dst0, SReg_64:$dst1),
805 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
806 InputModsNoDefault:$src1_modifiers, arc:$src1,
807 InputModsNoDefault:$src2_modifiers, arc:$src2,
808 ClampMod:$clamp, i32imm:$omod),
809 opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
813 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
814 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
816 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
817 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
820 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
821 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
822 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
823 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
824 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
825 i32:$src1_modifiers, P.Src1VT:$src1,
826 i32:$src2_modifiers, P.Src2VT:$src2,
830 //===----------------------------------------------------------------------===//
831 // Vector I/O classes
832 //===----------------------------------------------------------------------===//
834 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
835 DS <op, outs, ins, asm, pat> {
838 // Single load interpret the 2 i8imm operands as a single i16 offset.
839 let offset0 = offset{7-0};
840 let offset1 = offset{15-8};
843 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
845 (outs regClass:$vdst),
846 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
847 asm#" $vdst, $addr, $offset, [M0]",
855 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
857 (outs regClass:$vdst),
858 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
859 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
867 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
870 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
871 asm#" $addr, $data0, $offset [M0]",
879 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
882 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
883 u8imm:$offset0, u8imm:$offset1),
884 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
891 // 1 address, 1 data.
892 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
895 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
896 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
897 AtomicNoRet<noRetOp, 1> {
903 let hasPostISelHook = 1; // Adjusted to no return version.
906 // 1 address, 2 data.
907 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
910 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
911 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
913 AtomicNoRet<noRetOp, 1> {
917 let hasPostISelHook = 1; // Adjusted to no return version.
920 // 1 address, 2 data.
921 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
924 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
925 asm#" $addr, $data0, $data1, $offset, [M0]",
927 AtomicNoRet<noRetOp, 0> {
932 // 1 address, 1 data.
933 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
936 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
937 asm#" $addr, $data0, $offset, [M0]",
939 AtomicNoRet<noRetOp, 0> {
946 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
948 bit IsAddr64 = is_addr64;
949 string OpName = NAME # suffix;
952 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
955 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
956 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
957 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
958 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
959 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
965 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
966 : MUBUF <op, outs, ins, asm, pattern> {
976 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
977 : MUBUF <op, outs, ins, asm, pattern> {
987 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
988 ValueType vt, SDPatternOperator atomic> {
990 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
992 // No return variants
995 def _ADDR64 : MUBUFAtomicAddr64 <
997 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
998 mbuf_offset:$offset, slc:$slc),
999 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1000 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1002 def _OFFSET : MUBUFAtomicOffset <
1004 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1005 SSrc_32:$soffset, slc:$slc),
1006 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1007 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1010 // Variant that return values
1011 let glc = 1, Constraints = "$vdata = $vdata_in",
1012 DisableEncoding = "$vdata_in" in {
1014 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1015 op, (outs rc:$vdata),
1016 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1017 mbuf_offset:$offset, slc:$slc),
1018 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1020 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1021 i1:$slc), vt:$vdata_in))]
1022 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1024 def _RTN_OFFSET : MUBUFAtomicOffset <
1025 op, (outs rc:$vdata),
1026 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1027 SSrc_32:$soffset, slc:$slc),
1028 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1030 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1031 i1:$slc), vt:$vdata_in))]
1032 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1036 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1039 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1040 ValueType load_vt = i32,
1041 SDPatternOperator ld = null_frag> {
1043 let lds = 0, mayLoad = 1 in {
1047 let offen = 0, idxen = 0, vaddr = 0 in {
1048 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1049 (ins SReg_128:$srsrc,
1050 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1051 slc:$slc, tfe:$tfe),
1052 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1053 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1054 i32:$soffset, i16:$offset,
1055 i1:$glc, i1:$slc, i1:$tfe)))]>,
1056 MUBUFAddr64Table<0>;
1059 let offen = 1, idxen = 0 in {
1060 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1061 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1062 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1064 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1067 let offen = 0, idxen = 1 in {
1068 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1069 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1070 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1071 slc:$slc, tfe:$tfe),
1072 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1075 let offen = 1, idxen = 1 in {
1076 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1077 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1078 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1079 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1083 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1084 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1085 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1086 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1087 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1088 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1093 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1094 ValueType store_vt, SDPatternOperator st> {
1096 let addr64 = 0, lds = 0 in {
1100 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1101 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1103 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1104 "$glc"#"$slc"#"$tfe",
1108 let offen = 0, idxen = 0, vaddr = 0 in {
1109 def _OFFSET : MUBUF <
1111 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1112 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1113 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1114 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1115 i16:$offset, i1:$glc, i1:$slc,
1117 >, MUBUFAddr64Table<0>;
1118 } // offen = 0, idxen = 0, vaddr = 0
1120 let offen = 1, idxen = 0 in {
1121 def _OFFEN : MUBUF <
1123 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1124 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1125 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1126 "$glc"#"$slc"#"$tfe",
1129 } // end offen = 1, idxen = 0
1131 } // End addr64 = 0, lds = 0
1133 def _ADDR64 : MUBUF <
1135 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1136 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1137 [(st store_vt:$vdata,
1138 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1152 let soffset = 128; // ZERO
1156 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1157 FLAT <op, (outs regClass:$data),
1158 (ins VReg_64:$addr),
1159 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1166 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1167 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1168 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1180 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
1182 (outs regClass:$dst),
1183 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1184 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1185 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1186 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1187 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
1193 class MIMG_Mask <string op, int channels> {
1195 int Channels = channels;
1198 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1199 RegisterClass dst_rc,
1200 RegisterClass src_rc> : MIMG <
1202 (outs dst_rc:$vdata),
1203 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1204 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1206 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1207 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1212 let hasPostISelHook = 1;
1215 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1216 RegisterClass dst_rc,
1218 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1219 MIMG_Mask<asm#"_V1", channels>;
1220 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1221 MIMG_Mask<asm#"_V2", channels>;
1222 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1223 MIMG_Mask<asm#"_V4", channels>;
1226 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1227 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1228 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1229 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1230 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1233 class MIMG_Sampler_Helper <bits<7> op, string asm,
1234 RegisterClass dst_rc,
1235 RegisterClass src_rc> : MIMG <
1237 (outs dst_rc:$vdata),
1238 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1239 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1240 SReg_256:$srsrc, SReg_128:$ssamp),
1241 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1242 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1246 let hasPostISelHook = 1;
1249 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1250 RegisterClass dst_rc,
1252 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1253 MIMG_Mask<asm#"_V1", channels>;
1254 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1255 MIMG_Mask<asm#"_V2", channels>;
1256 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1257 MIMG_Mask<asm#"_V4", channels>;
1258 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1259 MIMG_Mask<asm#"_V8", channels>;
1260 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1261 MIMG_Mask<asm#"_V16", channels>;
1264 multiclass MIMG_Sampler <bits<7> op, string asm> {
1265 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1266 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1267 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1268 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1271 class MIMG_Gather_Helper <bits<7> op, string asm,
1272 RegisterClass dst_rc,
1273 RegisterClass src_rc> : MIMG <
1275 (outs dst_rc:$vdata),
1276 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1277 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1278 SReg_256:$srsrc, SReg_128:$ssamp),
1279 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1280 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1285 // DMASK was repurposed for GATHER4. 4 components are always
1286 // returned and DMASK works like a swizzle - it selects
1287 // the component to fetch. The only useful DMASK values are
1288 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1289 // (red,red,red,red) etc.) The ISA document doesn't mention
1291 // Therefore, disable all code which updates DMASK by setting these two:
1293 let hasPostISelHook = 0;
1296 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1297 RegisterClass dst_rc,
1299 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1300 MIMG_Mask<asm#"_V1", channels>;
1301 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1302 MIMG_Mask<asm#"_V2", channels>;
1303 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1304 MIMG_Mask<asm#"_V4", channels>;
1305 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1306 MIMG_Mask<asm#"_V8", channels>;
1307 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1308 MIMG_Mask<asm#"_V16", channels>;
1311 multiclass MIMG_Gather <bits<7> op, string asm> {
1312 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1313 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1314 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1315 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1318 //===----------------------------------------------------------------------===//
1319 // Vector instruction mappings
1320 //===----------------------------------------------------------------------===//
1322 // Maps an opcode in e32 form to its e64 equivalent
1323 def getVOPe64 : InstrMapping {
1324 let FilterClass = "VOP";
1325 let RowFields = ["OpName"];
1326 let ColFields = ["Size"];
1328 let ValueCols = [["8"]];
1331 // Maps an opcode in e64 form to its e32 equivalent
1332 def getVOPe32 : InstrMapping {
1333 let FilterClass = "VOP";
1334 let RowFields = ["OpName"];
1335 let ColFields = ["Size"];
1337 let ValueCols = [["4"]];
1340 // Maps an original opcode to its commuted version
1341 def getCommuteRev : InstrMapping {
1342 let FilterClass = "VOP2_REV";
1343 let RowFields = ["RevOp"];
1344 let ColFields = ["IsOrig"];
1346 let ValueCols = [["0"]];
1349 def getMaskedMIMGOp : InstrMapping {
1350 let FilterClass = "MIMG_Mask";
1351 let RowFields = ["Op"];
1352 let ColFields = ["Channels"];
1354 let ValueCols = [["1"], ["2"], ["3"] ];
1357 // Maps an commuted opcode to its original version
1358 def getCommuteOrig : InstrMapping {
1359 let FilterClass = "VOP2_REV";
1360 let RowFields = ["RevOp"];
1361 let ColFields = ["IsOrig"];
1363 let ValueCols = [["1"]];
1366 def isDS : InstrMapping {
1367 let FilterClass = "DS";
1368 let RowFields = ["Inst"];
1369 let ColFields = ["Size"];
1371 let ValueCols = [["8"]];
1374 def getMCOpcode : InstrMapping {
1375 let FilterClass = "SIMCInstr";
1376 let RowFields = ["PseudoInstr"];
1377 let ColFields = ["Subtarget"];
1378 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1379 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1382 def getAddr64Inst : InstrMapping {
1383 let FilterClass = "MUBUFAddr64Table";
1384 let RowFields = ["OpName"];
1385 let ColFields = ["IsAddr64"];
1387 let ValueCols = [["1"]];
1390 // Maps an atomic opcode to its version with a return value.
1391 def getAtomicRetOp : InstrMapping {
1392 let FilterClass = "AtomicNoRet";
1393 let RowFields = ["NoRetOp"];
1394 let ColFields = ["IsRet"];
1396 let ValueCols = [["1"]];
1399 // Maps an atomic opcode to its returnless version.
1400 def getAtomicNoRetOp : InstrMapping {
1401 let FilterClass = "AtomicNoRet";
1402 let RowFields = ["NoRetOp"];
1403 let ColFields = ["IsRet"];
1405 let ValueCols = [["0"]];
1408 include "SIInstructions.td"