1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isSICI : Predicate<
10 "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
11 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
12 >, AssemblerPredicate<"FeatureGCN1Encoding">;
13 def isCI : Predicate<"Subtarget->getGeneration() "
14 ">= AMDGPUSubtarget::SEA_ISLANDS">;
15 def isVI : Predicate <
16 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
17 AssemblerPredicate<"FeatureGCN3Encoding">;
24 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
25 field bits<8> SI = si;
26 field bits<8> VI = vi;
28 field bits<9> SI3 = {0, si{7-0}};
29 field bits<10> VI3 = {0, 0, vi{7-0}};
32 class vop1 <bits<8> si, bits<8> vi = si> : vop {
33 field bits<8> SI = si;
34 field bits<8> VI = vi;
36 field bits<9> SI3 = {1, 1, si{6-0}};
37 field bits<10> VI3 = !add(0x140, vi);
40 class vop2 <bits<6> si, bits<6> vi = si> : vop {
41 field bits<6> SI = si;
42 field bits<6> VI = vi;
44 field bits<9> SI3 = {1, 0, 0, si{5-0}};
45 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
48 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
49 // that doesn't have VOP2 encoding on VI
50 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
54 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
59 class sop1 <bits<8> si, bits<8> vi = si> {
60 field bits<8> SI = si;
61 field bits<8> VI = vi;
64 class sop2 <bits<7> si, bits<7> vi = si> {
65 field bits<7> SI = si;
66 field bits<7> VI = vi;
69 class sopk <bits<5> si, bits<5> vi = si> {
70 field bits<5> SI = si;
71 field bits<5> VI = vi;
74 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
75 // in AMDGPUInstrInfo.cpp
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
87 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
88 [SDNPMayLoad, SDNPMemOperand]
91 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
93 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
94 SDTCisVT<1, iAny>, // vdata(VGPR)
95 SDTCisVT<2, i32>, // num_channels(imm)
96 SDTCisVT<3, i32>, // vaddr(VGPR)
97 SDTCisVT<4, i32>, // soffset(SGPR)
98 SDTCisVT<5, i32>, // inst_offset(imm)
99 SDTCisVT<6, i32>, // dfmt(imm)
100 SDTCisVT<7, i32>, // nfmt(imm)
101 SDTCisVT<8, i32>, // offen(imm)
102 SDTCisVT<9, i32>, // idxen(imm)
103 SDTCisVT<10, i32>, // glc(imm)
104 SDTCisVT<11, i32>, // slc(imm)
105 SDTCisVT<12, i32> // tfe(imm)
107 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
110 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
111 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
115 class SDSample<string opcode> : SDNode <opcode,
116 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
117 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
120 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
121 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
122 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
123 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
125 def SIconstdata_ptr : SDNode<
126 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
129 // Transformation function, extract the lower 32bit of a 64bit immediate
130 def LO32 : SDNodeXForm<imm, [{
131 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
134 def LO32f : SDNodeXForm<fpimm, [{
135 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
136 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
139 // Transformation function, extract the upper 32bit of a 64bit immediate
140 def HI32 : SDNodeXForm<imm, [{
141 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
144 def HI32f : SDNodeXForm<fpimm, [{
145 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
146 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
149 def IMM8bitDWORD : PatLeaf <(imm),
150 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
153 def as_dword_i32imm : SDNodeXForm<imm, [{
154 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
157 def as_i1imm : SDNodeXForm<imm, [{
158 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
161 def as_i8imm : SDNodeXForm<imm, [{
162 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
165 def as_i16imm : SDNodeXForm<imm, [{
166 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
169 def as_i32imm: SDNodeXForm<imm, [{
170 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
173 def as_i64imm: SDNodeXForm<imm, [{
174 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
177 // Copied from the AArch64 backend:
178 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
179 return CurDAG->getTargetConstant(
180 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
183 // Copied from the AArch64 backend:
184 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
185 return CurDAG->getTargetConstant(
186 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
189 def IMM8bit : PatLeaf <(imm),
190 [{return isUInt<8>(N->getZExtValue());}]
193 def IMM12bit : PatLeaf <(imm),
194 [{return isUInt<12>(N->getZExtValue());}]
197 def IMM16bit : PatLeaf <(imm),
198 [{return isUInt<16>(N->getZExtValue());}]
201 def IMM20bit : PatLeaf <(imm),
202 [{return isUInt<20>(N->getZExtValue());}]
205 def IMM32bit : PatLeaf <(imm),
206 [{return isUInt<32>(N->getZExtValue());}]
209 def mubuf_vaddr_offset : PatFrag<
210 (ops node:$ptr, node:$offset, node:$imm_offset),
211 (add (add node:$ptr, node:$offset), node:$imm_offset)
214 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
215 return isInlineImmediate(N);
218 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
219 return isInlineImmediate(N);
222 class SGPRImm <dag frag> : PatLeaf<frag, [{
223 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
226 const SIRegisterInfo *SIRI =
227 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
228 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
230 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
237 //===----------------------------------------------------------------------===//
239 //===----------------------------------------------------------------------===//
241 def FRAMEri32 : Operand<iPTR> {
242 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
245 def SoppBrTarget : AsmOperandClass {
246 let Name = "SoppBrTarget";
247 let ParserMethod = "parseSOppBrTarget";
250 def sopp_brtarget : Operand<OtherVT> {
251 let EncoderMethod = "getSOPPBrEncoding";
252 let OperandType = "OPERAND_PCREL";
253 let ParserMatchClass = SoppBrTarget;
256 include "SIInstrFormats.td"
257 include "VIInstrFormats.td"
259 def MubufOffsetMatchClass : AsmOperandClass {
260 let Name = "MubufOffset";
261 let ParserMethod = "parseMubufOptionalOps";
262 let RenderMethod = "addImmOperands";
265 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
266 let Name = "DSOffset"#parser;
267 let ParserMethod = parser;
268 let RenderMethod = "addImmOperands";
269 let PredicateMethod = "isDSOffset";
272 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
273 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
275 def DSOffset01MatchClass : AsmOperandClass {
276 let Name = "DSOffset1";
277 let ParserMethod = "parseDSOff01OptionalOps";
278 let RenderMethod = "addImmOperands";
279 let PredicateMethod = "isDSOffset01";
282 class GDSBaseMatchClass <string parser> : AsmOperandClass {
283 let Name = "GDS"#parser;
284 let PredicateMethod = "isImm";
285 let ParserMethod = parser;
286 let RenderMethod = "addImmOperands";
289 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
290 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
292 def GLCMatchClass : AsmOperandClass {
294 let PredicateMethod = "isImm";
295 let ParserMethod = "parseMubufOptionalOps";
296 let RenderMethod = "addImmOperands";
299 def SLCMatchClass : AsmOperandClass {
301 let PredicateMethod = "isImm";
302 let ParserMethod = "parseMubufOptionalOps";
303 let RenderMethod = "addImmOperands";
306 def TFEMatchClass : AsmOperandClass {
308 let PredicateMethod = "isImm";
309 let ParserMethod = "parseMubufOptionalOps";
310 let RenderMethod = "addImmOperands";
313 def OModMatchClass : AsmOperandClass {
315 let PredicateMethod = "isImm";
316 let ParserMethod = "parseVOP3OptionalOps";
317 let RenderMethod = "addImmOperands";
320 def ClampMatchClass : AsmOperandClass {
322 let PredicateMethod = "isImm";
323 let ParserMethod = "parseVOP3OptionalOps";
324 let RenderMethod = "addImmOperands";
327 let OperandType = "OPERAND_IMMEDIATE" in {
329 def offen : Operand<i1> {
330 let PrintMethod = "printOffen";
332 def idxen : Operand<i1> {
333 let PrintMethod = "printIdxen";
335 def addr64 : Operand<i1> {
336 let PrintMethod = "printAddr64";
338 def mbuf_offset : Operand<i16> {
339 let PrintMethod = "printMBUFOffset";
340 let ParserMatchClass = MubufOffsetMatchClass;
342 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
343 let PrintMethod = "printDSOffset";
344 let ParserMatchClass = mc;
346 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
347 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
349 def ds_offset0 : Operand<i8> {
350 let PrintMethod = "printDSOffset0";
351 let ParserMatchClass = DSOffset01MatchClass;
353 def ds_offset1 : Operand<i8> {
354 let PrintMethod = "printDSOffset1";
355 let ParserMatchClass = DSOffset01MatchClass;
357 class gds_base <AsmOperandClass mc> : Operand <i1> {
358 let PrintMethod = "printGDS";
359 let ParserMatchClass = mc;
361 def gds : gds_base <GDSMatchClass>;
363 def gds01 : gds_base <GDS01MatchClass>;
365 def glc : Operand <i1> {
366 let PrintMethod = "printGLC";
367 let ParserMatchClass = GLCMatchClass;
369 def slc : Operand <i1> {
370 let PrintMethod = "printSLC";
371 let ParserMatchClass = SLCMatchClass;
373 def tfe : Operand <i1> {
374 let PrintMethod = "printTFE";
375 let ParserMatchClass = TFEMatchClass;
378 def omod : Operand <i32> {
379 let PrintMethod = "printOModSI";
380 let ParserMatchClass = OModMatchClass;
383 def ClampMod : Operand <i1> {
384 let PrintMethod = "printClampSI";
385 let ParserMatchClass = ClampMatchClass;
388 } // End OperandType = "OPERAND_IMMEDIATE"
390 def VOPDstS64 : VOPDstOperand <SReg_64>;
392 //===----------------------------------------------------------------------===//
394 //===----------------------------------------------------------------------===//
396 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
397 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
399 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
400 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
401 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
402 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
403 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
404 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
406 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
407 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
408 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
409 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
411 //===----------------------------------------------------------------------===//
412 // SI assembler operands
413 //===----------------------------------------------------------------------===//
434 //===----------------------------------------------------------------------===//
436 // SI Instruction multiclass helpers.
438 // Instructions with _32 take 32-bit operands.
439 // Instructions with _64 take 64-bit operands.
441 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
442 // encoding is the standard encoding, but instruction that make use of
443 // any of the instruction modifiers must use the 64-bit encoding.
445 // Instructions with _e32 use the 32-bit encoding.
446 // Instructions with _e64 use the 64-bit encoding.
448 //===----------------------------------------------------------------------===//
450 class SIMCInstr <string pseudo, int subtarget> {
451 string PseudoInstr = pseudo;
452 int Subtarget = subtarget;
455 //===----------------------------------------------------------------------===//
457 //===----------------------------------------------------------------------===//
459 class EXPCommon : InstSI<
461 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
462 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
463 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
472 let isPseudo = 1, isCodeGenOnly = 1 in {
473 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
476 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
478 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
481 //===----------------------------------------------------------------------===//
483 //===----------------------------------------------------------------------===//
485 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
486 SOP1 <outs, ins, "", pattern>,
487 SIMCInstr<opName, SISubtarget.NONE> {
489 let isCodeGenOnly = 1;
492 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
493 SOP1 <outs, ins, asm, []>,
495 SIMCInstr<opName, SISubtarget.SI> {
496 let isCodeGenOnly = 0;
497 let AssemblerPredicates = [isSICI];
500 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
501 SOP1 <outs, ins, asm, []>,
503 SIMCInstr<opName, SISubtarget.VI> {
504 let isCodeGenOnly = 0;
505 let AssemblerPredicates = [isVI];
508 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
511 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
513 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
515 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
519 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
520 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
521 opName#" $dst, $src0", pattern
524 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
525 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
526 opName#" $dst, $src0", pattern
529 // no input, 64-bit output.
530 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
531 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
533 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
538 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
544 // 64-bit input, no output
545 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
546 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
548 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
553 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
559 // 64-bit input, 32-bit output.
560 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
561 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
562 opName#" $dst, $src0", pattern
565 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
566 SOP2<outs, ins, "", pattern>,
567 SIMCInstr<opName, SISubtarget.NONE> {
569 let isCodeGenOnly = 1;
572 // Pseudo instructions have no encodings, but adding this field here allows
574 // let sdst = xxx in {
575 // for multiclasses that include both real and pseudo instructions.
576 field bits<7> sdst = 0;
579 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
580 SOP2<outs, ins, asm, []>,
582 SIMCInstr<opName, SISubtarget.SI> {
583 let AssemblerPredicates = [isSICI];
586 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
587 SOP2<outs, ins, asm, []>,
589 SIMCInstr<opName, SISubtarget.VI> {
590 let AssemblerPredicates = [isVI];
593 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
594 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
595 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
597 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
598 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
599 opName#" $dst, $src0, $src1 [$scc]">;
601 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
602 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
603 opName#" $dst, $src0, $src1 [$scc]">;
606 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
609 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
611 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
613 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
617 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
618 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
619 opName#" $dst, $src0, $src1", pattern
622 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
623 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
624 opName#" $dst, $src0, $src1", pattern
627 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
628 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
629 opName#" $dst, $src0, $src1", pattern
632 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
633 string opName, PatLeaf cond> : SOPC <
634 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
635 opName#" $src0, $src1", []>;
637 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
638 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
640 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
641 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
643 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
644 SOPK <outs, ins, "", pattern>,
645 SIMCInstr<opName, SISubtarget.NONE> {
647 let isCodeGenOnly = 1;
650 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
651 SOPK <outs, ins, asm, []>,
653 SIMCInstr<opName, SISubtarget.SI> {
654 let AssemblerPredicates = [isSICI];
655 let isCodeGenOnly = 0;
658 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
659 SOPK <outs, ins, asm, []>,
661 SIMCInstr<opName, SISubtarget.VI> {
662 let AssemblerPredicates = [isVI];
663 let isCodeGenOnly = 0;
666 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
667 string asm = opName#opAsm> {
668 def "" : SOPK_Pseudo <opName, outs, ins, []>;
670 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
672 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
676 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
677 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
680 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
681 opName#" $dst, $src0">;
683 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
684 opName#" $dst, $src0">;
687 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
688 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
689 (ins SReg_32:$src0, u16imm:$src1), pattern>;
691 let DisableEncoding = "$dst" in {
692 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
693 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
695 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
696 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
700 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
701 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
705 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
706 string argAsm, string asm = opName#argAsm> {
708 def "" : SOPK_Pseudo <opName, outs, ins, []>;
710 def _si : SOPK <outs, ins, asm, []>,
712 SIMCInstr<opName, SISubtarget.SI> {
713 let AssemblerPredicates = [isSICI];
714 let isCodeGenOnly = 0;
717 def _vi : SOPK <outs, ins, asm, []>,
719 SIMCInstr<opName, SISubtarget.VI> {
720 let AssemblerPredicates = [isVI];
721 let isCodeGenOnly = 0;
724 //===----------------------------------------------------------------------===//
726 //===----------------------------------------------------------------------===//
728 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
729 SMRD <outs, ins, "", pattern>,
730 SIMCInstr<opName, SISubtarget.NONE> {
732 let isCodeGenOnly = 1;
735 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
737 SMRD <outs, ins, asm, []>,
739 SIMCInstr<opName, SISubtarget.SI> {
740 let AssemblerPredicates = [isSICI];
743 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
745 SMRD <outs, ins, asm, []>,
747 SIMCInstr<opName, SISubtarget.VI> {
748 let AssemblerPredicates = [isVI];
751 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
752 string asm, list<dag> pattern> {
754 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
756 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
758 // glc is only applicable to scalar stores, which are not yet
761 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
765 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
766 RegisterClass dstClass> {
768 op, opName#"_IMM", 1, (outs dstClass:$dst),
769 (ins baseClass:$sbase, u32imm:$offset),
770 opName#" $dst, $sbase, $offset", []
773 defm _SGPR : SMRD_m <
774 op, opName#"_SGPR", 0, (outs dstClass:$dst),
775 (ins baseClass:$sbase, SReg_32:$soff),
776 opName#" $dst, $sbase, $soff", []
780 //===----------------------------------------------------------------------===//
781 // Vector ALU classes
782 //===----------------------------------------------------------------------===//
784 // This must always be right before the operand being input modified.
785 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
786 let PrintMethod = "printOperandAndMods";
789 def InputModsMatchClass : AsmOperandClass {
790 let Name = "RegWithInputMods";
793 def InputModsNoDefault : Operand <i32> {
794 let PrintMethod = "printOperandAndMods";
795 let ParserMatchClass = InputModsMatchClass;
798 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
800 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
801 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
805 // Returns the register class to use for the destination of VOP[123C]
806 // instructions for the given VT.
807 class getVALUDstForVT<ValueType VT> {
808 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
809 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
810 VOPDstOperand<SReg_64>)); // else VT == i1
813 // Returns the register class to use for source 0 of VOP[12C]
814 // instructions for the given VT.
815 class getVOPSrc0ForVT<ValueType VT> {
816 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
819 // Returns the register class to use for source 1 of VOP[12C] for the
821 class getVOPSrc1ForVT<ValueType VT> {
822 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
825 // Returns the register class to use for sources of VOP3 instructions for the
827 class getVOP3SrcForVT<ValueType VT> {
828 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
831 // Returns 1 if the source arguments have modifiers, 0 if they do not.
832 class hasModifiers<ValueType SrcVT> {
833 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
834 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
837 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
838 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
839 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
840 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
844 // Returns the input arguments for VOP3 instructions for the given SrcVT.
845 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
846 RegisterOperand Src2RC, int NumSrcArgs,
850 !if (!eq(NumSrcArgs, 1),
851 !if (!eq(HasModifiers, 1),
852 // VOP1 with modifiers
853 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
854 ClampMod:$clamp, omod:$omod)
856 // VOP1 without modifiers
859 !if (!eq(NumSrcArgs, 2),
860 !if (!eq(HasModifiers, 1),
861 // VOP 2 with modifiers
862 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
863 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
864 ClampMod:$clamp, omod:$omod)
866 // VOP2 without modifiers
867 (ins Src0RC:$src0, Src1RC:$src1)
869 /* NumSrcArgs == 3 */,
870 !if (!eq(HasModifiers, 1),
871 // VOP3 with modifiers
872 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
873 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
874 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
875 ClampMod:$clamp, omod:$omod)
877 // VOP3 without modifiers
878 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
882 // Returns the assembly string for the inputs and outputs of a VOP[12C]
883 // instruction. This does not add the _e32 suffix, so it can be reused
885 class getAsm32 <int NumSrcArgs> {
886 string src1 = ", $src1";
887 string src2 = ", $src2";
888 string ret = "$dst, $src0"#
889 !if(!eq(NumSrcArgs, 1), "", src1)#
890 !if(!eq(NumSrcArgs, 3), src2, "");
893 // Returns the assembly string for the inputs and outputs of a VOP3
895 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
896 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
897 string src1 = !if(!eq(NumSrcArgs, 1), "",
898 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
899 " $src1_modifiers,"));
900 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
902 !if(!eq(HasModifiers, 0),
903 getAsm32<NumSrcArgs>.ret,
904 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
908 class VOPProfile <list<ValueType> _ArgVT> {
910 field list<ValueType> ArgVT = _ArgVT;
912 field ValueType DstVT = ArgVT[0];
913 field ValueType Src0VT = ArgVT[1];
914 field ValueType Src1VT = ArgVT[2];
915 field ValueType Src2VT = ArgVT[3];
916 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
917 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
918 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
919 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
920 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
921 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
923 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
924 field bit HasModifiers = hasModifiers<Src0VT>.ret;
926 field dag Outs = (outs DstRC:$dst);
928 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
929 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
932 field string Asm32 = getAsm32<NumSrcArgs>.ret;
933 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
936 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
937 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
938 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
939 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
940 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
941 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
942 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
943 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
944 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
946 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
947 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
948 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
949 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
950 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
951 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
952 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
953 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
954 let Src0RC32 = VCSrc_32;
957 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
958 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
959 let Asm64 = "$dst, $src0_modifiers, $src1";
962 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
963 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
964 let Asm64 = "$dst, $src0_modifiers, $src1";
967 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
968 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
969 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
970 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
971 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
972 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
973 let Asm64 = "$dst, $src0, $src1, $src2";
976 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
977 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
978 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
979 field string Asm = "$dst, $src0, $vsrc1, $src2";
981 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
982 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
983 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
986 class VOP <string opName> {
987 string OpName = opName;
990 class VOP2_REV <string revOp, bit isOrig> {
991 string RevOp = revOp;
995 class AtomicNoRet <string noRetOp, bit isRet> {
996 string NoRetOp = noRetOp;
1000 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1001 VOP1Common <outs, ins, "", pattern>,
1003 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1004 MnemonicAlias<opName#"_e32", opName> {
1006 let isCodeGenOnly = 1;
1012 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1013 VOP1<op.SI, outs, ins, asm, []>,
1014 SIMCInstr <opName#"_e32", SISubtarget.SI>;
1016 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1017 VOP1<op.VI, outs, ins, asm, []>,
1018 SIMCInstr <opName#"_e32", SISubtarget.VI>;
1020 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1022 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1024 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1026 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
1029 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1031 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1033 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1036 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1037 VOP2Common <outs, ins, "", pattern>,
1039 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1040 MnemonicAlias<opName#"_e32", opName> {
1042 let isCodeGenOnly = 1;
1045 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1046 VOP2 <op.SI, outs, ins, opName#asm, []>,
1047 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1048 let AssemblerPredicates = [isSICI];
1051 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1052 VOP2 <op.VI, outs, ins, opName#asm, []>,
1053 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1054 let AssemblerPredicates = [isVI];
1057 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1058 string opName, string revOp> {
1059 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1060 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1062 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1065 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1066 string opName, string revOp> {
1067 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1068 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1070 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1072 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1076 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1078 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1079 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1080 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1081 bits<2> omod = !if(HasModifiers, ?, 0);
1082 bits<1> clamp = !if(HasModifiers, ?, 0);
1083 bits<9> src1 = !if(HasSrc1, ?, 0);
1084 bits<9> src2 = !if(HasSrc2, ?, 0);
1087 class VOP3DisableModFields <bit HasSrc0Mods,
1088 bit HasSrc1Mods = 0,
1089 bit HasSrc2Mods = 0,
1090 bit HasOutputMods = 0> {
1091 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1092 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1093 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1094 bits<2> omod = !if(HasOutputMods, ?, 0);
1095 bits<1> clamp = !if(HasOutputMods, ?, 0);
1098 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1099 VOP3Common <outs, ins, "", pattern>,
1101 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1102 MnemonicAlias<opName#"_e64", opName> {
1104 let isCodeGenOnly = 1;
1107 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1108 VOP3Common <outs, ins, asm, []>,
1110 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1111 let AssemblerPredicates = [isSICI];
1114 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1115 VOP3Common <outs, ins, asm, []>,
1117 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1118 let AssemblerPredicates = [isVI];
1121 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1122 VOP3Common <outs, ins, asm, []>,
1124 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1125 let AssemblerPredicates = [isSICI];
1128 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1129 VOP3Common <outs, ins, asm, []>,
1131 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1132 let AssemblerPredicates = [isVI];
1135 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1136 string opName, int NumSrcArgs, bit HasMods = 1> {
1138 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1140 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1141 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1142 !if(!eq(NumSrcArgs, 2), 0, 1),
1144 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1145 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1146 !if(!eq(NumSrcArgs, 2), 0, 1),
1150 // VOP3_m without source modifiers
1151 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1152 string opName, int NumSrcArgs, bit HasMods = 1> {
1154 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1156 let src0_modifiers = 0,
1161 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1162 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1166 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1167 list<dag> pattern, string opName, bit HasMods = 1> {
1169 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1171 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1172 VOP3DisableFields<0, 0, HasMods>;
1174 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1175 VOP3DisableFields<0, 0, HasMods>;
1178 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1179 list<dag> pattern, string opName, bit HasMods = 1> {
1181 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1183 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1184 VOP3DisableFields<0, 0, HasMods>;
1185 // No VI instruction. This class is for SI only.
1188 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1189 list<dag> pattern, string opName, string revOp,
1190 bit HasMods = 1, bit UseFullOp = 0> {
1192 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1193 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1195 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1196 VOP3DisableFields<1, 0, HasMods>;
1198 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1199 VOP3DisableFields<1, 0, HasMods>;
1202 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1203 list<dag> pattern, string opName, string revOp,
1204 bit HasMods = 1, bit UseFullOp = 0> {
1206 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1207 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1209 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1210 VOP3DisableFields<1, 0, HasMods>;
1212 // No VI instruction. This class is for SI only.
1215 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1216 // option of implicit vcc use?
1217 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1218 list<dag> pattern, string opName, string revOp,
1219 bit HasMods = 1, bit UseFullOp = 0> {
1220 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1221 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1223 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1224 // can write it into any SGPR. We currently don't use the carry out,
1225 // so for now hardcode it to VCC as well.
1226 let sdst = SIOperand.VCC, Defs = [VCC] in {
1227 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1228 VOP3DisableFields<1, 0, HasMods>;
1230 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1231 VOP3DisableFields<1, 0, HasMods>;
1232 } // End sdst = SIOperand.VCC, Defs = [VCC]
1235 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1236 list<dag> pattern, string opName, string revOp,
1237 bit HasMods = 1, bit UseFullOp = 0> {
1238 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1241 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1242 VOP3DisableFields<1, 1, HasMods>;
1244 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1245 VOP3DisableFields<1, 1, HasMods>;
1248 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1249 list<dag> pattern, string opName,
1250 bit HasMods, bit defExec, string revOp> {
1252 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1253 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1255 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1256 VOP3DisableFields<1, 0, HasMods> {
1257 let Defs = !if(defExec, [EXEC], []);
1260 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1261 VOP3DisableFields<1, 0, HasMods> {
1262 let Defs = !if(defExec, [EXEC], []);
1266 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1267 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1268 string asm, list<dag> pattern = []> {
1269 let isPseudo = 1, isCodeGenOnly = 1 in {
1270 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1271 SIMCInstr<opName, SISubtarget.NONE>;
1274 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1275 SIMCInstr <opName, SISubtarget.SI> {
1276 let AssemblerPredicates = [isSICI];
1279 def _vi : VOP3Common <outs, ins, asm, []>,
1281 VOP3DisableFields <1, 0, 0>,
1282 SIMCInstr <opName, SISubtarget.VI> {
1283 let AssemblerPredicates = [isVI];
1287 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1288 dag ins32, string asm32, list<dag> pat32,
1289 dag ins64, string asm64, list<dag> pat64,
1292 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1294 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1297 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1298 SDPatternOperator node = null_frag> : VOP1_Helper <
1300 P.Ins32, P.Asm32, [],
1303 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1304 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1305 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1309 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1310 SDPatternOperator node = null_frag> {
1312 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1314 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1316 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1317 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1318 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1319 opName, P.HasModifiers>;
1322 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1323 dag ins32, string asm32, list<dag> pat32,
1324 dag ins64, string asm64, list<dag> pat64,
1325 string revOp, bit HasMods> {
1326 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1328 defm _e64 : VOP3_2_m <op,
1329 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1333 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1334 SDPatternOperator node = null_frag,
1335 string revOp = opName> : VOP2_Helper <
1337 P.Ins32, P.Asm32, [],
1341 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1342 i1:$clamp, i32:$omod)),
1343 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1344 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1345 revOp, P.HasModifiers
1348 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1349 SDPatternOperator node = null_frag,
1350 string revOp = opName> {
1351 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1353 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1356 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1357 i1:$clamp, i32:$omod)),
1358 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1359 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1360 opName, revOp, P.HasModifiers>;
1363 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1364 dag ins32, string asm32, list<dag> pat32,
1365 dag ins64, string asm64, list<dag> pat64,
1366 string revOp, bit HasMods> {
1368 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1370 defm _e64 : VOP3b_2_m <op,
1371 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1375 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1376 SDPatternOperator node = null_frag,
1377 string revOp = opName> : VOP2b_Helper <
1379 P.Ins32, P.Asm32, [],
1383 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1384 i1:$clamp, i32:$omod)),
1385 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1386 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1387 revOp, P.HasModifiers
1390 // A VOP2 instruction that is VOP3-only on VI.
1391 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1392 dag ins32, string asm32, list<dag> pat32,
1393 dag ins64, string asm64, list<dag> pat64,
1394 string revOp, bit HasMods> {
1395 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1397 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1401 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1402 SDPatternOperator node = null_frag,
1403 string revOp = opName>
1406 P.Ins32, P.Asm32, [],
1410 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1411 i1:$clamp, i32:$omod)),
1412 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1413 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1414 revOp, P.HasModifiers
1417 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1419 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1421 let isCodeGenOnly = 0 in {
1422 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1423 !strconcat(opName, VOP_MADK.Asm), []>,
1424 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1427 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1428 !strconcat(opName, VOP_MADK.Asm), []>,
1429 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1431 } // End isCodeGenOnly = 0
1434 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1435 VOPCCommon <ins, "", pattern>,
1437 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1438 MnemonicAlias<opName#"_e32", opName> {
1440 let isCodeGenOnly = 1;
1443 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1444 string opName, bit DefExec, string revOpName = ""> {
1445 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1447 def _si : VOPC<op.SI, ins, asm, []>,
1448 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1449 let Defs = !if(DefExec, [EXEC], []);
1450 let hasSideEffects = DefExec;
1453 def _vi : VOPC<op.VI, ins, asm, []>,
1454 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1455 let Defs = !if(DefExec, [EXEC], []);
1456 let hasSideEffects = DefExec;
1460 multiclass VOPC_Helper <vopc op, string opName,
1461 dag ins32, string asm32, list<dag> pat32,
1462 dag out64, dag ins64, string asm64, list<dag> pat64,
1463 bit HasMods, bit DefExec, string revOp> {
1464 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1466 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1467 opName, HasMods, DefExec, revOp>;
1470 // Special case for class instructions which only have modifiers on
1471 // the 1st source operand.
1472 multiclass VOPC_Class_Helper <vopc op, string opName,
1473 dag ins32, string asm32, list<dag> pat32,
1474 dag out64, dag ins64, string asm64, list<dag> pat64,
1475 bit HasMods, bit DefExec, string revOp> {
1476 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1478 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1479 opName, HasMods, DefExec, revOp>,
1480 VOP3DisableModFields<1, 0, 0>;
1483 multiclass VOPCInst <vopc op, string opName,
1484 VOPProfile P, PatLeaf cond = COND_NULL,
1485 string revOp = opName,
1486 bit DefExec = 0> : VOPC_Helper <
1488 P.Ins32, P.Asm32, [],
1489 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1492 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1493 i1:$clamp, i32:$omod)),
1494 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1496 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1497 P.HasModifiers, DefExec, revOp
1500 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1501 bit DefExec = 0> : VOPC_Class_Helper <
1503 P.Ins32, P.Asm32, [],
1504 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1507 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1508 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1509 P.HasModifiers, DefExec, opName
1513 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1514 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1516 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1517 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1519 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1520 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1522 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1523 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1526 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1527 PatLeaf cond = COND_NULL,
1529 : VOPCInst <op, opName, P, cond, revOp, 1>;
1531 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1532 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1534 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1535 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1537 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1538 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1540 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1541 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1543 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1544 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1545 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1548 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1549 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1551 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1552 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1554 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1555 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1557 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1558 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1560 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1561 SDPatternOperator node = null_frag> : VOP3_Helper <
1562 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1563 !if(!eq(P.NumSrcArgs, 3),
1566 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1567 i1:$clamp, i32:$omod)),
1568 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1569 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1570 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1572 !if(!eq(P.NumSrcArgs, 2),
1575 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1576 i1:$clamp, i32:$omod)),
1577 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1578 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1579 /* P.NumSrcArgs == 1 */,
1582 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1583 i1:$clamp, i32:$omod))))],
1584 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1585 P.NumSrcArgs, P.HasModifiers
1588 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1589 // only VOP instruction that implicitly reads VCC.
1590 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1592 SDPatternOperator node = null_frag> : VOP3_Helper <
1594 (outs P.DstRC.RegClass:$dst),
1595 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1596 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1597 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1600 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1602 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1603 i1:$clamp, i32:$omod)),
1604 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1605 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1610 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1611 string opName, list<dag> pattern> :
1613 op, (outs vrc:$vdst, SReg_64:$sdst),
1614 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1615 InputModsNoDefault:$src1_modifiers, arc:$src1,
1616 InputModsNoDefault:$src2_modifiers, arc:$src2,
1617 ClampMod:$clamp, omod:$omod),
1618 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1619 opName, opName, 1, 1
1622 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1623 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1625 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1626 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1629 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1630 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1631 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1632 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1633 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1634 i32:$src1_modifiers, P.Src1VT:$src1,
1635 i32:$src2_modifiers, P.Src2VT:$src2,
1639 //===----------------------------------------------------------------------===//
1640 // Interpolation opcodes
1641 //===----------------------------------------------------------------------===//
1643 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1644 VINTRPCommon <outs, ins, "", pattern>,
1645 SIMCInstr<opName, SISubtarget.NONE> {
1647 let isCodeGenOnly = 1;
1650 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1652 VINTRPCommon <outs, ins, asm, []>,
1654 SIMCInstr<opName, SISubtarget.SI>;
1656 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1658 VINTRPCommon <outs, ins, asm, []>,
1660 SIMCInstr<opName, SISubtarget.VI>;
1662 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1663 string disableEncoding = "", string constraints = "",
1664 list<dag> pattern = []> {
1665 let DisableEncoding = disableEncoding,
1666 Constraints = constraints in {
1667 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1669 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1671 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1675 //===----------------------------------------------------------------------===//
1676 // Vector I/O classes
1677 //===----------------------------------------------------------------------===//
1679 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1680 DS <outs, ins, "", pattern>,
1681 SIMCInstr <opName, SISubtarget.NONE> {
1683 let isCodeGenOnly = 1;
1686 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1687 DS <outs, ins, asm, []>,
1689 SIMCInstr <opName, SISubtarget.SI> {
1690 let isCodeGenOnly = 0;
1693 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1694 DS <outs, ins, asm, []>,
1696 SIMCInstr <opName, SISubtarget.VI>;
1698 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1699 DS_Real_si <op,opName, outs, ins, asm> {
1701 // Single load interpret the 2 i8imm operands as a single i16 offset.
1703 let offset0 = offset{7-0};
1704 let offset1 = offset{15-8};
1705 let isCodeGenOnly = 0;
1708 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1709 DS_Real_vi <op, opName, outs, ins, asm> {
1711 // Single load interpret the 2 i8imm operands as a single i16 offset.
1713 let offset0 = offset{7-0};
1714 let offset1 = offset{15-8};
1717 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1718 dag outs = (outs rc:$vdst),
1719 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1720 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1722 def "" : DS_Pseudo <opName, outs, ins, []>;
1724 let data0 = 0, data1 = 0 in {
1725 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1726 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1730 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1731 dag outs = (outs rc:$vdst),
1732 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1733 gds01:$gds, M0Reg:$m0),
1734 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1736 def "" : DS_Pseudo <opName, outs, ins, []>;
1738 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
1739 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1740 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1744 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1746 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1748 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1750 def "" : DS_Pseudo <opName, outs, ins, []>,
1751 AtomicNoRet<opName, 0>;
1753 let data1 = 0, vdst = 0 in {
1754 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1755 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1759 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1761 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1762 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds, M0Reg:$m0),
1763 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1765 def "" : DS_Pseudo <opName, outs, ins, []>;
1767 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
1768 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1769 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1773 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1774 string noRetOp = "",
1775 dag outs = (outs rc:$vdst),
1776 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1778 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1780 def "" : DS_Pseudo <opName, outs, ins, []>,
1781 AtomicNoRet<noRetOp, 1>;
1784 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1785 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1789 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1790 string noRetOp = "", dag ins,
1791 dag outs = (outs rc:$vdst),
1792 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1794 def "" : DS_Pseudo <opName, outs, ins, []>,
1795 AtomicNoRet<noRetOp, 1>;
1797 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1798 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1801 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1802 string noRetOp = "", RegisterClass src = rc> :
1803 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1804 (ins VGPR_32:$addr, src:$data0, src:$data1,
1805 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1808 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1809 string noRetOp = opName,
1811 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1812 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1813 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1815 def "" : DS_Pseudo <opName, outs, ins, []>,
1816 AtomicNoRet<noRetOp, 0>;
1819 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1820 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1824 multiclass DS_0A_RET <bits<8> op, string opName,
1825 dag outs = (outs VGPR_32:$vdst),
1826 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1827 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1829 let mayLoad = 1, mayStore = 1 in {
1830 def "" : DS_Pseudo <opName, outs, ins, []>;
1832 let addr = 0, data0 = 0, data1 = 0 in {
1833 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1834 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1835 } // end addr = 0, data0 = 0, data1 = 0
1836 } // end mayLoad = 1, mayStore = 1
1839 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1840 dag outs = (outs VGPR_32:$vdst),
1841 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset, M0Reg:$m0),
1842 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1844 def "" : DS_Pseudo <opName, outs, ins, []>;
1846 let data0 = 0, data1 = 0, gds = 1 in {
1847 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1848 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1849 } // end data0 = 0, data1 = 0, gds = 1
1852 multiclass DS_1A_GDS <bits<8> op, string opName,
1854 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
1855 string asm = opName#" $addr gds"> {
1857 def "" : DS_Pseudo <opName, outs, ins, []>;
1859 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1860 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1861 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1862 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1865 multiclass DS_1A <bits<8> op, string opName,
1867 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0, gds:$gds),
1868 string asm = opName#" $addr"#"$offset"#"$gds"> {
1870 let mayLoad = 1, mayStore = 1 in {
1871 def "" : DS_Pseudo <opName, outs, ins, []>;
1873 let vdst = 0, data0 = 0, data1 = 0 in {
1874 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1875 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1876 } // let vdst = 0, data0 = 0, data1 = 0
1877 } // end mayLoad = 1, mayStore = 1
1880 //===----------------------------------------------------------------------===//
1882 //===----------------------------------------------------------------------===//
1884 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1885 MTBUF <outs, ins, "", pattern>,
1886 SIMCInstr<opName, SISubtarget.NONE> {
1888 let isCodeGenOnly = 1;
1891 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1893 MTBUF <outs, ins, asm, []>,
1895 SIMCInstr<opName, SISubtarget.SI>;
1897 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1898 MTBUF <outs, ins, asm, []>,
1900 SIMCInstr <opName, SISubtarget.VI>;
1902 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1903 list<dag> pattern> {
1905 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1907 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1909 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1913 let mayStore = 1, mayLoad = 0 in {
1915 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1916 RegisterClass regClass> : MTBUF_m <
1918 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1919 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1920 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1921 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1922 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1925 } // mayStore = 1, mayLoad = 0
1927 let mayLoad = 1, mayStore = 0 in {
1929 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1930 RegisterClass regClass> : MTBUF_m <
1931 op, opName, (outs regClass:$dst),
1932 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1933 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1934 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1935 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1936 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1939 } // mayLoad = 1, mayStore = 0
1941 //===----------------------------------------------------------------------===//
1943 //===----------------------------------------------------------------------===//
1945 class mubuf <bits<7> si, bits<7> vi = si> {
1946 field bits<7> SI = si;
1947 field bits<7> VI = vi;
1950 let isCodeGenOnly = 0 in {
1952 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1953 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1957 } // End let isCodeGenOnly = 0
1959 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1960 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
1964 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1965 bit IsAddr64 = is_addr64;
1966 string OpName = NAME # suffix;
1969 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1970 MUBUF <outs, ins, "", pattern>,
1971 SIMCInstr<opName, SISubtarget.NONE> {
1973 let isCodeGenOnly = 1;
1975 // dummy fields, so that we can use let statements around multiclasses
1985 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1987 MUBUF <outs, ins, asm, []>,
1989 SIMCInstr<opName, SISubtarget.SI> {
1993 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1995 MUBUF <outs, ins, asm, []>,
1997 SIMCInstr<opName, SISubtarget.VI> {
2001 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2002 list<dag> pattern> {
2004 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2005 MUBUFAddr64Table <0>;
2007 let addr64 = 0, isCodeGenOnly = 0 in {
2008 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2011 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2014 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2015 dag ins, string asm, list<dag> pattern> {
2017 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2018 MUBUFAddr64Table <1>;
2020 let addr64 = 1, isCodeGenOnly = 0 in {
2021 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2024 // There is no VI version. If the pseudo is selected, it should be lowered
2025 // for VI appropriately.
2028 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2029 string asm, list<dag> pattern, bit is_return> {
2031 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2032 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2033 AtomicNoRet<NAME#"_OFFSET", is_return>;
2035 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2037 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2040 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2044 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2045 string asm, list<dag> pattern, bit is_return> {
2047 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2048 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2049 AtomicNoRet<NAME#"_ADDR64", is_return>;
2051 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2052 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2055 // There is no VI version. If the pseudo is selected, it should be lowered
2056 // for VI appropriately.
2059 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2060 ValueType vt, SDPatternOperator atomic> {
2062 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2064 // No return variants
2067 defm _ADDR64 : MUBUFAtomicAddr64_m <
2068 op, name#"_addr64", (outs),
2069 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
2070 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2071 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2074 defm _OFFSET : MUBUFAtomicOffset_m <
2075 op, name#"_offset", (outs),
2076 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2078 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2082 // Variant that return values
2083 let glc = 1, Constraints = "$vdata = $vdata_in",
2084 DisableEncoding = "$vdata_in" in {
2086 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2087 op, name#"_rtn_addr64", (outs rc:$vdata),
2088 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
2089 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2090 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2092 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2093 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2096 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2097 op, name#"_rtn_offset", (outs rc:$vdata),
2098 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2099 mbuf_offset:$offset, slc:$slc),
2100 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2102 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2103 i1:$slc), vt:$vdata_in))], 1
2108 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2111 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2112 ValueType load_vt = i32,
2113 SDPatternOperator ld = null_frag> {
2115 let mayLoad = 1, mayStore = 0 in {
2116 let offen = 0, idxen = 0, vaddr = 0 in {
2117 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2118 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2119 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2120 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2121 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2122 i32:$soffset, i16:$offset,
2123 i1:$glc, i1:$slc, i1:$tfe)))]>;
2126 let offen = 1, idxen = 0 in {
2127 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2128 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2129 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2131 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2134 let offen = 0, idxen = 1 in {
2135 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2136 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2137 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2138 slc:$slc, tfe:$tfe),
2139 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2142 let offen = 1, idxen = 1 in {
2143 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2144 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2145 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2146 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2149 let offen = 0, idxen = 0 in {
2150 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2151 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2152 SCSrc_32:$soffset, mbuf_offset:$offset,
2153 glc:$glc, slc:$slc, tfe:$tfe),
2154 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2155 "$glc"#"$slc"#"$tfe",
2156 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2157 i64:$vaddr, i32:$soffset,
2158 i16:$offset, i1:$glc, i1:$slc,
2164 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2165 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2166 let mayLoad = 0, mayStore = 1 in {
2167 defm : MUBUF_m <op, name, (outs),
2168 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2169 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2171 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2172 "$glc"#"$slc"#"$tfe", []>;
2174 let offen = 0, idxen = 0, vaddr = 0 in {
2175 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2176 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2177 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2178 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2179 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2180 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2181 } // offen = 0, idxen = 0, vaddr = 0
2183 let offen = 1, idxen = 0 in {
2184 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2185 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2186 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2187 slc:$slc, tfe:$tfe),
2188 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2189 "$glc"#"$slc"#"$tfe", []>;
2190 } // end offen = 1, idxen = 0
2192 let offen = 0, idxen = 1 in {
2193 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2194 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2195 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2196 slc:$slc, tfe:$tfe),
2197 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2200 let offen = 1, idxen = 1 in {
2201 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2202 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2203 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2204 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2207 let offen = 0, idxen = 0 in {
2208 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2209 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2211 mbuf_offset:$offset, glc:$glc, slc:$slc,
2213 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2214 "$offset"#"$glc"#"$slc"#"$tfe",
2215 [(st store_vt:$vdata,
2216 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2217 i32:$soffset, i16:$offset,
2218 i1:$glc, i1:$slc, i1:$tfe))]>;
2220 } // End mayLoad = 0, mayStore = 1
2223 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2224 FLAT <op, (outs regClass:$vdst),
2225 (ins VReg_64:$addr),
2226 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2234 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2235 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2236 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2249 class MIMG_Mask <string op, int channels> {
2251 int Channels = channels;
2254 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2255 RegisterClass dst_rc,
2256 RegisterClass src_rc> : MIMG <
2258 (outs dst_rc:$vdata),
2259 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2260 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2262 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2263 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2268 let hasPostISelHook = 1;
2271 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2272 RegisterClass dst_rc,
2274 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2275 MIMG_Mask<asm#"_V1", channels>;
2276 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2277 MIMG_Mask<asm#"_V2", channels>;
2278 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2279 MIMG_Mask<asm#"_V4", channels>;
2282 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2283 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2284 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2285 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2286 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2289 class MIMG_Sampler_Helper <bits<7> op, string asm,
2290 RegisterClass dst_rc,
2291 RegisterClass src_rc, int wqm> : MIMG <
2293 (outs dst_rc:$vdata),
2294 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2295 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2296 SReg_256:$srsrc, SReg_128:$ssamp),
2297 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2298 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2302 let hasPostISelHook = 1;
2306 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2307 RegisterClass dst_rc,
2308 int channels, int wqm> {
2309 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2310 MIMG_Mask<asm#"_V1", channels>;
2311 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2312 MIMG_Mask<asm#"_V2", channels>;
2313 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2314 MIMG_Mask<asm#"_V4", channels>;
2315 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2316 MIMG_Mask<asm#"_V8", channels>;
2317 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2318 MIMG_Mask<asm#"_V16", channels>;
2321 multiclass MIMG_Sampler <bits<7> op, string asm> {
2322 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2323 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2324 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2325 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2328 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2329 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2330 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2331 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2332 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2335 class MIMG_Gather_Helper <bits<7> op, string asm,
2336 RegisterClass dst_rc,
2337 RegisterClass src_rc, int wqm> : MIMG <
2339 (outs dst_rc:$vdata),
2340 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2341 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2342 SReg_256:$srsrc, SReg_128:$ssamp),
2343 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2344 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2349 // DMASK was repurposed for GATHER4. 4 components are always
2350 // returned and DMASK works like a swizzle - it selects
2351 // the component to fetch. The only useful DMASK values are
2352 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2353 // (red,red,red,red) etc.) The ISA document doesn't mention
2355 // Therefore, disable all code which updates DMASK by setting these two:
2357 let hasPostISelHook = 0;
2361 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2362 RegisterClass dst_rc,
2363 int channels, int wqm> {
2364 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2365 MIMG_Mask<asm#"_V1", channels>;
2366 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2367 MIMG_Mask<asm#"_V2", channels>;
2368 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2369 MIMG_Mask<asm#"_V4", channels>;
2370 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2371 MIMG_Mask<asm#"_V8", channels>;
2372 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2373 MIMG_Mask<asm#"_V16", channels>;
2376 multiclass MIMG_Gather <bits<7> op, string asm> {
2377 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2378 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2379 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2380 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2383 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2384 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2385 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2386 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2387 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2390 //===----------------------------------------------------------------------===//
2391 // Vector instruction mappings
2392 //===----------------------------------------------------------------------===//
2394 // Maps an opcode in e32 form to its e64 equivalent
2395 def getVOPe64 : InstrMapping {
2396 let FilterClass = "VOP";
2397 let RowFields = ["OpName"];
2398 let ColFields = ["Size"];
2400 let ValueCols = [["8"]];
2403 // Maps an opcode in e64 form to its e32 equivalent
2404 def getVOPe32 : InstrMapping {
2405 let FilterClass = "VOP";
2406 let RowFields = ["OpName"];
2407 let ColFields = ["Size"];
2409 let ValueCols = [["4"]];
2412 def getMaskedMIMGOp : InstrMapping {
2413 let FilterClass = "MIMG_Mask";
2414 let RowFields = ["Op"];
2415 let ColFields = ["Channels"];
2417 let ValueCols = [["1"], ["2"], ["3"] ];
2420 // Maps an commuted opcode to its original version
2421 def getCommuteOrig : InstrMapping {
2422 let FilterClass = "VOP2_REV";
2423 let RowFields = ["RevOp"];
2424 let ColFields = ["IsOrig"];
2426 let ValueCols = [["1"]];
2429 // Maps an original opcode to its commuted version
2430 def getCommuteRev : InstrMapping {
2431 let FilterClass = "VOP2_REV";
2432 let RowFields = ["RevOp"];
2433 let ColFields = ["IsOrig"];
2435 let ValueCols = [["0"]];
2438 def getCommuteCmpOrig : InstrMapping {
2439 let FilterClass = "VOP2_REV";
2440 let RowFields = ["RevOp"];
2441 let ColFields = ["IsOrig"];
2443 let ValueCols = [["1"]];
2446 // Maps an original opcode to its commuted version
2447 def getCommuteCmpRev : InstrMapping {
2448 let FilterClass = "VOP2_REV";
2449 let RowFields = ["RevOp"];
2450 let ColFields = ["IsOrig"];
2452 let ValueCols = [["0"]];
2456 def getMCOpcodeGen : InstrMapping {
2457 let FilterClass = "SIMCInstr";
2458 let RowFields = ["PseudoInstr"];
2459 let ColFields = ["Subtarget"];
2460 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2461 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2464 def getAddr64Inst : InstrMapping {
2465 let FilterClass = "MUBUFAddr64Table";
2466 let RowFields = ["OpName"];
2467 let ColFields = ["IsAddr64"];
2469 let ValueCols = [["1"]];
2472 // Maps an atomic opcode to its version with a return value.
2473 def getAtomicRetOp : InstrMapping {
2474 let FilterClass = "AtomicNoRet";
2475 let RowFields = ["NoRetOp"];
2476 let ColFields = ["IsRet"];
2478 let ValueCols = [["1"]];
2481 // Maps an atomic opcode to its returnless version.
2482 def getAtomicNoRetOp : InstrMapping {
2483 let FilterClass = "AtomicNoRet";
2484 let RowFields = ["NoRetOp"];
2485 let ColFields = ["IsRet"];
2487 let ValueCols = [["0"]];
2490 include "SIInstructions.td"
2491 include "CIInstructions.td"
2492 include "VIInstructions.td"