1 //===--------------------- R600MergeVectorRegisters.cpp -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass merges inputs of swizzeable instructions into vector sharing
12 /// common data and/or have enough undef subreg using swizzle abilities.
14 /// For instance let's consider the following pseudo code :
15 /// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
17 /// vreg7<def> = REG_SEQ vreg1, sub0, vreg3, sub1, undef, sub2, vreg4, sub3
18 /// (swizzable Inst) vreg7, SwizzleMask : sub0, sub1, sub2, sub3
21 /// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
23 /// vreg7<def> = INSERT_SUBREG vreg4, sub3
24 /// (swizzable Inst) vreg7, SwizzleMask : sub0, sub2, sub1, sub3
26 /// This allow regalloc to reduce register pressure for vector registers and
27 /// to reduce MOV count.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "vec-merger"
31 #include "llvm/Support/Debug.h"
33 #include "R600InstrInfo.h"
34 #include "llvm/CodeGen/DFAPacketizer.h"
35 #include "llvm/CodeGen/MachineDominators.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineLoopInfo.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
48 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
49 for (MachineRegisterInfo::def_iterator It = MRI.def_begin(Reg),
50 E = MRI.def_end(); It != E; ++It) {
51 return (*It).isImplicitDef();
53 llvm_unreachable("Reg without a def");
60 DenseMap<unsigned, unsigned> RegToChan;
61 std::vector<unsigned> UndefReg;
62 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
63 assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE);
64 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
65 MachineOperand &MO = Instr->getOperand(i);
66 unsigned Chan = Instr->getOperand(i + 1).getImm();
67 if (isImplicitlyDef(MRI, MO.getReg()))
68 UndefReg.push_back(Chan);
70 RegToChan[MO.getReg()] = Chan;
75 bool operator==(const RegSeqInfo &RSI) const {
76 return RSI.Instr == Instr;
80 class R600VectorRegMerger : public MachineFunctionPass {
82 MachineRegisterInfo *MRI;
83 const R600InstrInfo *TII;
84 bool canSwizzle(const MachineInstr &) const;
85 bool areAllUsesSwizzeable(unsigned Reg) const;
86 void SwizzleInput(MachineInstr &,
87 const std::vector<std::pair<unsigned, unsigned> > &) const;
88 bool tryMergeVector(const RegSeqInfo *, RegSeqInfo *,
89 std::vector<std::pair<unsigned, unsigned> > &Remap) const;
90 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
91 std::vector<std::pair<unsigned, unsigned> > &RemapChan);
92 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
93 std::vector<std::pair<unsigned, unsigned> > &RemapChan);
94 MachineInstr *RebuildVector(RegSeqInfo *MI,
95 const RegSeqInfo *BaseVec,
96 const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const;
97 void RemoveMI(MachineInstr *);
98 void trackRSI(const RegSeqInfo &RSI);
100 typedef DenseMap<unsigned, std::vector<MachineInstr *> > InstructionSetMap;
101 DenseMap<MachineInstr *, RegSeqInfo> PreviousRegSeq;
102 InstructionSetMap PreviousRegSeqByReg;
103 InstructionSetMap PreviousRegSeqByUndefCount;
106 R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
107 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
109 void getAnalysisUsage(AnalysisUsage &AU) const {
110 AU.setPreservesCFG();
111 AU.addRequired<MachineDominatorTree>();
112 AU.addPreserved<MachineDominatorTree>();
113 AU.addRequired<MachineLoopInfo>();
114 AU.addPreserved<MachineLoopInfo>();
115 MachineFunctionPass::getAnalysisUsage(AU);
118 const char *getPassName() const {
119 return "R600 Vector Registers Merge Pass";
122 bool runOnMachineFunction(MachineFunction &Fn);
125 char R600VectorRegMerger::ID = 0;
127 bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI)
129 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
131 switch (MI.getOpcode()) {
132 case AMDGPU::R600_ExportSwz:
133 case AMDGPU::EG_ExportSwz:
140 bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
141 RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned> > &Remap)
143 unsigned CurrentUndexIdx = 0;
144 for (DenseMap<unsigned, unsigned>::iterator It = ToMerge->RegToChan.begin(),
145 E = ToMerge->RegToChan.end(); It != E; ++It) {
146 DenseMap<unsigned, unsigned>::const_iterator PosInUntouched =
147 Untouched->RegToChan.find((*It).first);
148 if (PosInUntouched != Untouched->RegToChan.end()) {
149 Remap.push_back(std::pair<unsigned, unsigned>
150 ((*It).second, (*PosInUntouched).second));
153 if (CurrentUndexIdx >= Untouched->UndefReg.size())
155 Remap.push_back(std::pair<unsigned, unsigned>
156 ((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
162 MachineInstr *R600VectorRegMerger::RebuildVector(
163 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
164 const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const {
165 unsigned Reg = RSI->Instr->getOperand(0).getReg();
166 MachineBasicBlock::iterator Pos = RSI->Instr;
167 MachineBasicBlock &MBB = *Pos->getParent();
168 DebugLoc DL = Pos->getDebugLoc();
170 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg();
171 DenseMap<unsigned, unsigned> UpdatedRegToChan = BaseRSI->RegToChan;
172 std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg;
173 for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(),
174 E = RSI->RegToChan.end(); It != E; ++It) {
175 if (BaseRSI->RegToChan.find((*It).first) != BaseRSI->RegToChan.end()) {
176 UpdatedRegToChan[(*It).first] = (*It).second;
179 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
180 unsigned SubReg = (*It).first;
181 unsigned Swizzle = (*It).second;
183 for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
184 if (RemapChan[j].first == Swizzle) {
185 Chan = RemapChan[j].second;
189 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
194 UpdatedRegToChan[SubReg] = Chan;
195 for (std::vector<unsigned>::iterator RemoveIt = UpdatedUndef.begin(),
196 RemoveE = UpdatedUndef.end(); RemoveIt != RemoveE; ++ RemoveIt) {
197 if (*RemoveIt == Chan)
198 UpdatedUndef.erase(RemoveIt);
200 DEBUG(dbgs() << " ->"; Tmp->dump(););
203 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg)
205 DEBUG(dbgs() << " ->"; Pos->dump(););
207 DEBUG(dbgs() << " Updating Swizzle:\n");
208 for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg),
209 E = MRI->use_end(); It != E; ++It) {
210 DEBUG(dbgs() << " ";(*It).dump(); dbgs() << " ->");
211 SwizzleInput(*It, RemapChan);
214 RSI->Instr->eraseFromParent();
218 RSI->RegToChan = UpdatedRegToChan;
219 RSI->UndefReg = UpdatedUndef;
224 void R600VectorRegMerger::RemoveMI(MachineInstr *MI) {
225 for (InstructionSetMap::iterator It = PreviousRegSeqByReg.begin(),
226 E = PreviousRegSeqByReg.end(); It != E; ++It) {
227 std::vector<MachineInstr *> &MIs = (*It).second;
228 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end());
230 for (InstructionSetMap::iterator It = PreviousRegSeqByUndefCount.begin(),
231 E = PreviousRegSeqByUndefCount.end(); It != E; ++It) {
232 std::vector<MachineInstr *> &MIs = (*It).second;
233 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end());
237 void R600VectorRegMerger::SwizzleInput(MachineInstr &MI,
238 const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const {
240 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
244 for (unsigned i = 0; i < 4; i++) {
245 unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1;
246 for (unsigned j = 0, e = RemapChan.size(); j < e; j++) {
247 if (RemapChan[j].first == Swizzle) {
248 MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);
255 bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const {
256 for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg),
257 E = MRI->use_end(); It != E; ++It) {
258 if (!canSwizzle(*It))
264 bool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI,
265 RegSeqInfo &CompatibleRSI,
266 std::vector<std::pair<unsigned, unsigned> > &RemapChan) {
267 for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(),
268 MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) {
271 if (PreviousRegSeqByReg[MOp->getReg()].empty())
273 std::vector<MachineInstr *> MIs = PreviousRegSeqByReg[MOp->getReg()];
274 for (unsigned i = 0, e = MIs.size(); i < e; i++) {
275 CompatibleRSI = PreviousRegSeq[MIs[i]];
276 if (RSI == CompatibleRSI)
278 if (tryMergeVector(&CompatibleRSI, &RSI, RemapChan))
285 bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI,
286 RegSeqInfo &CompatibleRSI,
287 std::vector<std::pair<unsigned, unsigned> > &RemapChan) {
288 unsigned NeededUndefs = 4 - RSI.UndefReg.size();
289 if (PreviousRegSeqByUndefCount[NeededUndefs].empty())
291 std::vector<MachineInstr *> &MIs =
292 PreviousRegSeqByUndefCount[NeededUndefs];
293 CompatibleRSI = PreviousRegSeq[MIs.back()];
294 tryMergeVector(&CompatibleRSI, &RSI, RemapChan);
298 void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
299 for (DenseMap<unsigned, unsigned>::const_iterator
300 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) {
301 PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr);
303 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
304 PreviousRegSeq[RSI.Instr] = RSI;
307 bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
308 MRI = &(Fn.getRegInfo());
309 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
310 MBB != MBBe; ++MBB) {
311 MachineBasicBlock *MB = MBB;
312 PreviousRegSeq.clear();
313 PreviousRegSeqByReg.clear();
314 PreviousRegSeqByUndefCount.clear();
316 for (MachineBasicBlock::iterator MII = MB->begin(), MIIE = MB->end();
317 MII != MIIE; ++MII) {
318 MachineInstr *MI = MII;
319 if (MI->getOpcode() != AMDGPU::REG_SEQUENCE)
322 RegSeqInfo RSI(*MRI, MI);
324 // All uses of MI are swizzeable ?
325 unsigned Reg = MI->getOperand(0).getReg();
326 if (!areAllUsesSwizzeable(Reg))
329 DEBUG (dbgs() << "Trying to optimize ";
333 RegSeqInfo CandidateRSI;
334 std::vector<std::pair<unsigned, unsigned> > RemapChan;
335 DEBUG(dbgs() << "Using common slots...\n";);
336 if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) {
337 // Remove CandidateRSI mapping
338 RemoveMI(CandidateRSI.Instr);
339 MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
343 DEBUG(dbgs() << "Using free slots...\n";);
345 if (tryMergeUsingFreeSlot(RSI, CandidateRSI, RemapChan)) {
346 RemoveMI(CandidateRSI.Instr);
347 MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
360 llvm::FunctionPass *llvm::createR600VectorRegMerger(TargetMachine &tm) {
361 return new R600VectorRegMerger(tm);