1 //===-- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass compute turns all control flow pseudo instructions into native one
12 /// computing their address on the fly ; it also sets STACK_SIZE info.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "r600cf"
16 #include "llvm/Support/Debug.h"
17 #include "llvm/Support/raw_ostream.h"
20 #include "R600Defines.h"
21 #include "R600InstrInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "R600RegisterInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 class R600ControlFlowFinalizer : public MachineFunctionPass {
34 const R600InstrInfo *TII;
35 unsigned MaxFetchInst;
37 bool isFetch(const MachineInstr *MI) const {
38 switch (MI->getOpcode()) {
39 case AMDGPU::TEX_VTX_CONSTBUF:
40 case AMDGPU::TEX_VTX_TEXBUF:
42 case AMDGPU::TEX_GET_TEXTURE_RESINFO:
43 case AMDGPU::TEX_GET_GRADIENTS_H:
44 case AMDGPU::TEX_GET_GRADIENTS_V:
45 case AMDGPU::TEX_SET_GRADIENTS_H:
46 case AMDGPU::TEX_SET_GRADIENTS_V:
47 case AMDGPU::TEX_SAMPLE:
48 case AMDGPU::TEX_SAMPLE_C:
49 case AMDGPU::TEX_SAMPLE_L:
50 case AMDGPU::TEX_SAMPLE_C_L:
51 case AMDGPU::TEX_SAMPLE_LB:
52 case AMDGPU::TEX_SAMPLE_C_LB:
53 case AMDGPU::TEX_SAMPLE_G:
54 case AMDGPU::TEX_SAMPLE_C_G:
56 case AMDGPU::TXD_SHADOW:
63 bool IsTrivialInst(MachineInstr *MI) const {
64 switch (MI->getOpcode()) {
73 MachineBasicBlock::iterator
74 MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
75 unsigned CfAddress) const {
76 MachineBasicBlock::iterator ClauseHead = I;
77 unsigned AluInstCount = 0;
78 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
84 if (AluInstCount > MaxFetchInst)
87 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
88 TII->get(AMDGPU::CF_TC))
89 .addImm(CfAddress) // ADDR
90 .addImm(AluInstCount); // COUNT
93 void CounterPropagateAddr(MachineInstr *MI, unsigned Addr) const {
94 MI->getOperand(0).setImm(Addr + MI->getOperand(0).getImm());
96 void CounterPropagateAddr(std::set<MachineInstr *> MIs, unsigned Addr)
98 for (std::set<MachineInstr *>::iterator It = MIs.begin(), E = MIs.end();
100 MachineInstr *MI = *It;
101 CounterPropagateAddr(MI, Addr);
106 R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID),
107 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) {
108 const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
109 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD4XXX)
115 virtual bool runOnMachineFunction(MachineFunction &MF) {
116 unsigned MaxStack = 0;
117 unsigned CurrentStack = 0;
118 for (MachineFunction::iterator MB = MF.begin(), ME = MF.end(); MB != ME;
120 MachineBasicBlock &MBB = *MB;
121 unsigned CfCount = 0;
122 std::vector<std::pair<unsigned, std::set<MachineInstr *> > > LoopStack;
123 std::vector<MachineInstr * > IfThenElseStack;
124 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
125 if (MFI->ShaderType == 1) {
126 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
127 TII->get(AMDGPU::CF_CALL_FS));
130 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
133 DEBUG(dbgs() << CfCount << ":"; I->dump(););
134 I = MakeFetchClause(MBB, I, 0);
139 MachineBasicBlock::iterator MI = I;
141 switch (MI->getOpcode()) {
142 case AMDGPU::CF_ALU_PUSH_BEFORE:
144 MaxStack = std::max(MaxStack, CurrentStack);
146 DEBUG(dbgs() << CfCount << ":"; MI->dump(););
149 case AMDGPU::WHILELOOP: {
151 MaxStack = std::max(MaxStack, CurrentStack);
152 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
153 TII->get(AMDGPU::WHILE_LOOP))
155 std::pair<unsigned, std::set<MachineInstr *> > Pair(CfCount,
156 std::set<MachineInstr *>());
157 Pair.second.insert(MIb);
158 LoopStack.push_back(Pair);
159 MI->eraseFromParent();
163 case AMDGPU::ENDLOOP: {
165 std::pair<unsigned, std::set<MachineInstr *> > Pair =
167 LoopStack.pop_back();
168 CounterPropagateAddr(Pair.second, CfCount);
169 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::END_LOOP))
170 .addImm(Pair.first + 1);
171 MI->eraseFromParent();
175 case AMDGPU::IF_PREDICATE_SET: {
176 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
177 TII->get(AMDGPU::CF_JUMP))
180 IfThenElseStack.push_back(MIb);
181 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
182 MI->eraseFromParent();
187 MachineInstr * JumpInst = IfThenElseStack.back();
188 IfThenElseStack.pop_back();
189 CounterPropagateAddr(JumpInst, CfCount);
190 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
191 TII->get(AMDGPU::CF_ELSE))
194 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
195 IfThenElseStack.push_back(MIb);
196 MI->eraseFromParent();
200 case AMDGPU::ENDIF: {
202 MachineInstr *IfOrElseInst = IfThenElseStack.back();
203 IfThenElseStack.pop_back();
204 CounterPropagateAddr(IfOrElseInst, CfCount);
205 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
206 TII->get(AMDGPU::POP))
209 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
210 MI->eraseFromParent();
214 case AMDGPU::PREDICATED_BREAK: {
217 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::CF_JUMP))
220 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
221 TII->get(AMDGPU::LOOP_BREAK))
223 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::POP))
226 LoopStack.back().second.insert(MIb);
227 MI->eraseFromParent();
230 case AMDGPU::CONTINUE: {
231 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
232 TII->get(AMDGPU::CF_CONTINUE))
234 LoopStack.back().second.insert(MIb);
235 MI->eraseFromParent();
243 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
244 TII->get(AMDGPU::STACK_SIZE))
251 const char *getPassName() const {
252 return "R600 Control Flow Finalizer Pass";
256 char R600ControlFlowFinalizer::ID = 0;
261 llvm::FunctionPass *llvm::createR600ControlFlowFinalizer(TargetMachine &TM) {
262 return new R600ControlFlowFinalizer(TM);