1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/Support/MathExtras.h"
20 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
23 printInstruction(MI, OS);
25 printAnnotation(OS, Annot);
28 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
30 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
33 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
35 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
38 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
43 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
45 if (MI->getOperand(OpNo).getImm())
49 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
51 if (MI->getOperand(OpNo).getImm())
55 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
57 if (MI->getOperand(OpNo).getImm())
61 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
63 if (MI->getOperand(OpNo).getImm()) {
65 printU16ImmOperand(MI, OpNo, O);
69 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
71 if (MI->getOperand(OpNo).getImm())
75 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
77 if (MI->getOperand(OpNo).getImm())
81 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
83 if (MI->getOperand(OpNo).getImm())
87 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
101 case AMDGPU::FLAT_SCR:
110 case AMDGPU::EXEC_LO:
113 case AMDGPU::EXEC_HI:
116 case AMDGPU::FLAT_SCR_LO:
117 O << "flat_scratch_lo";
119 case AMDGPU::FLAT_SCR_HI:
120 O << "flat_scratch_hi";
129 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
132 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
135 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
138 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
141 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
144 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
147 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
150 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
153 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
156 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
159 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
163 O << getRegisterName(reg);
167 // The low 8 bits of the encoding value is the register index, for both VGPRs
169 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
175 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
178 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
179 int32_t SImm = static_cast<int32_t>(Imm);
180 if (SImm >= -16 && SImm <= 64) {
185 if (Imm == FloatToBits(1.0f) ||
186 Imm == FloatToBits(-1.0f) ||
187 Imm == FloatToBits(0.5f) ||
188 Imm == FloatToBits(-0.5f) ||
189 Imm == FloatToBits(2.0f) ||
190 Imm == FloatToBits(-2.0f) ||
191 Imm == FloatToBits(4.0f) ||
192 Imm == FloatToBits(-4.0f)) {
193 O << BitsToFloat(Imm);
197 O << formatHex(static_cast<uint64_t>(Imm));
200 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
203 const MCOperand &Op = MI->getOperand(OpNo);
205 switch (Op.getReg()) {
206 // This is the default predicate state, so we don't need to print it.
207 case AMDGPU::PRED_SEL_OFF:
211 printRegOperand(Op.getReg(), O);
214 } else if (Op.isImm()) {
215 printImmediate(Op.getImm(), O);
216 } else if (Op.isFPImm()) {
218 } else if (Op.isExpr()) {
219 const MCExpr *Exp = Op.getExpr();
222 assert(!"unknown operand type in printOperand");
226 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
228 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
229 if (InputModifiers & 0x1)
231 if (InputModifiers & 0x2)
233 printOperand(MI, OpNo + 1, O);
234 if (InputModifiers & 0x2)
238 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
240 unsigned Imm = MI->getOperand(OpNum).getImm();
244 } else if (Imm == 1) {
246 } else if (Imm == 0) {
249 assert(!"Invalid interpolation parameter slot");
253 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
255 printOperand(MI, OpNo, O);
257 printOperand(MI, OpNo + 1, O);
260 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
261 raw_ostream &O, StringRef Asm,
263 const MCOperand &Op = MI->getOperand(OpNo);
265 if (Op.getImm() == 1) {
272 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
274 printIfSet(MI, OpNo, O, "|");
277 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
279 printIfSet(MI, OpNo, O, "_SAT");
282 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
284 int32_t Imm = MI->getOperand(OpNo).getImm();
285 O << Imm << '(' << BitsToFloat(Imm) << ')';
288 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
290 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
293 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
295 printIfSet(MI, OpNo, O, "-");
298 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
300 switch (MI->getOperand(OpNo).getImm()) {
314 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
316 printIfSet(MI, OpNo, O, "+");
319 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
321 printIfSet(MI, OpNo, O, "ExecMask,");
324 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
326 printIfSet(MI, OpNo, O, "Pred,");
329 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
331 const MCOperand &Op = MI->getOperand(OpNo);
332 if (Op.getImm() == 0) {
337 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
339 const char * chans = "XYZW";
340 int sel = MI->getOperand(OpNo).getImm();
349 O << cb << "[" << sel << "]";
350 } else if (sel >= 448) {
353 } else if (sel >= 0){
358 O << "." << chans[chan];
361 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
363 int BankSwizzle = MI->getOperand(OpNo).getImm();
364 switch (BankSwizzle) {
366 O << "BS:VEC_021/SCL_122";
369 O << "BS:VEC_120/SCL_212";
372 O << "BS:VEC_102/SCL_221";
386 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
388 unsigned Sel = MI->getOperand(OpNo).getImm();
416 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
418 unsigned CT = MI->getOperand(OpNo).getImm();
431 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
433 int KCacheMode = MI->getOperand(OpNo).getImm();
434 if (KCacheMode > 0) {
435 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
436 O << "CB" << KCacheBank <<":";
437 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
438 int LineSize = (KCacheMode == 1)?16:32;
439 O << KCacheAddr * 16 << "-" << KCacheAddr * 16 + LineSize;
443 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
445 unsigned SImm16 = MI->getOperand(OpNo).getImm();
446 unsigned Msg = SImm16 & 0xF;
447 if (Msg == 2 || Msg == 3) {
448 unsigned Op = (SImm16 >> 4) & 0xF;
456 unsigned Stream = (SImm16 >> 8) & 0x3;
463 O << " stream " << Stream;
471 O << "unknown(" << Msg << ") ";
474 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
476 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
477 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
478 // works so it might be a misprint in docs.
479 unsigned SImm16 = MI->getOperand(OpNo).getImm();
480 unsigned Vmcnt = SImm16 & 0xF;
481 unsigned Expcnt = (SImm16 >> 4) & 0xF;
482 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
484 O << "vmcnt(" << Vmcnt << ") ";
486 O << "expcnt(" << Expcnt << ") ";
488 O << "lgkmcnt(" << Lgkmcnt << ")";
491 #include "AMDGPUGenAsmWriter.inc"