1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/Support/MathExtras.h"
20 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
23 printInstruction(MI, OS);
25 printAnnotation(OS, Annot);
28 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
30 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
33 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
35 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
38 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
43 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
45 if (MI->getOperand(OpNo).getImm())
49 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
51 if (MI->getOperand(OpNo).getImm())
55 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
57 if (MI->getOperand(OpNo).getImm())
61 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
63 if (MI->getOperand(OpNo).getImm()) {
65 printU16ImmOperand(MI, OpNo, O);
69 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
71 if (MI->getOperand(OpNo).getImm())
75 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
77 if (MI->getOperand(OpNo).getImm())
81 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
83 if (MI->getOperand(OpNo).getImm())
87 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
101 case AMDGPU::FLAT_SCR:
110 case AMDGPU::EXEC_LO:
113 case AMDGPU::EXEC_HI:
116 case AMDGPU::FLAT_SCR_LO:
117 O << "flat_scratch_lo";
119 case AMDGPU::FLAT_SCR_HI:
120 O << "flat_scratch_hi";
129 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
132 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
135 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
138 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
141 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
144 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
147 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
150 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
153 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
156 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
159 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
163 O << getRegisterName(reg);
167 // The low 8 bits of the encoding value is the register index, for both VGPRs
169 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
175 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
178 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
179 int32_t SImm = static_cast<int32_t>(Imm);
180 if (SImm >= -16 && SImm <= 64) {
185 if (Imm == FloatToBits(0.0f))
187 else if (Imm == FloatToBits(1.0f))
189 else if (Imm == FloatToBits(-1.0f))
191 else if (Imm == FloatToBits(0.5f))
193 else if (Imm == FloatToBits(-0.5f))
195 else if (Imm == FloatToBits(2.0f))
197 else if (Imm == FloatToBits(-2.0f))
199 else if (Imm == FloatToBits(4.0f))
201 else if (Imm == FloatToBits(-4.0f))
204 O << formatHex(static_cast<uint64_t>(Imm));
208 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
211 const MCOperand &Op = MI->getOperand(OpNo);
213 switch (Op.getReg()) {
214 // This is the default predicate state, so we don't need to print it.
215 case AMDGPU::PRED_SEL_OFF:
219 printRegOperand(Op.getReg(), O);
222 } else if (Op.isImm()) {
223 printImmediate(Op.getImm(), O);
224 } else if (Op.isFPImm()) {
226 // We special case 0.0 because otherwise it will be printed as an integer.
227 if (Op.getFPImm() == 0.0)
230 printImmediate(FloatToBits(Op.getFPImm()), O);
231 } else if (Op.isExpr()) {
232 const MCExpr *Exp = Op.getExpr();
235 llvm_unreachable("unknown operand type in printOperand");
239 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
241 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
242 if (InputModifiers & 0x1)
244 if (InputModifiers & 0x2)
246 printOperand(MI, OpNo + 1, O);
247 if (InputModifiers & 0x2)
251 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
253 unsigned Imm = MI->getOperand(OpNum).getImm();
257 } else if (Imm == 1) {
259 } else if (Imm == 0) {
262 llvm_unreachable("Invalid interpolation parameter slot");
266 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
268 printOperand(MI, OpNo, O);
270 printOperand(MI, OpNo + 1, O);
273 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
274 raw_ostream &O, StringRef Asm,
276 const MCOperand &Op = MI->getOperand(OpNo);
278 if (Op.getImm() == 1) {
285 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
287 printIfSet(MI, OpNo, O, "|");
290 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
292 printIfSet(MI, OpNo, O, "_SAT");
295 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
297 int32_t Imm = MI->getOperand(OpNo).getImm();
298 O << Imm << '(' << BitsToFloat(Imm) << ')';
301 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
303 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
306 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
308 printIfSet(MI, OpNo, O, "-");
311 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
313 switch (MI->getOperand(OpNo).getImm()) {
327 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
329 printIfSet(MI, OpNo, O, "+");
332 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
334 printIfSet(MI, OpNo, O, "ExecMask,");
337 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
339 printIfSet(MI, OpNo, O, "Pred,");
342 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
344 const MCOperand &Op = MI->getOperand(OpNo);
345 if (Op.getImm() == 0) {
350 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
352 const char * chans = "XYZW";
353 int sel = MI->getOperand(OpNo).getImm();
362 O << cb << '[' << sel << ']';
363 } else if (sel >= 448) {
366 } else if (sel >= 0){
371 O << '.' << chans[chan];
374 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
376 int BankSwizzle = MI->getOperand(OpNo).getImm();
377 switch (BankSwizzle) {
379 O << "BS:VEC_021/SCL_122";
382 O << "BS:VEC_120/SCL_212";
385 O << "BS:VEC_102/SCL_221";
399 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
401 unsigned Sel = MI->getOperand(OpNo).getImm();
429 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
431 unsigned CT = MI->getOperand(OpNo).getImm();
444 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
446 int KCacheMode = MI->getOperand(OpNo).getImm();
447 if (KCacheMode > 0) {
448 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
449 O << "CB" << KCacheBank << ':';
450 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
451 int LineSize = (KCacheMode == 1) ? 16 : 32;
452 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
456 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
458 unsigned SImm16 = MI->getOperand(OpNo).getImm();
459 unsigned Msg = SImm16 & 0xF;
460 if (Msg == 2 || Msg == 3) {
461 unsigned Op = (SImm16 >> 4) & 0xF;
469 unsigned Stream = (SImm16 >> 8) & 0x3;
476 O << " stream " << Stream;
484 O << "unknown(" << Msg << ") ";
487 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
489 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
490 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
491 // works so it might be a misprint in docs.
492 unsigned SImm16 = MI->getOperand(OpNo).getImm();
493 unsigned Vmcnt = SImm16 & 0xF;
494 unsigned Expcnt = (SImm16 >> 4) & 0xF;
495 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
497 O << "vmcnt(" << Vmcnt << ") ";
499 O << "expcnt(" << Expcnt << ") ";
501 O << "lgkmcnt(" << Lgkmcnt << ')';
504 #include "AMDGPUGenAsmWriter.inc"