1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "SIDefines.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCInstrInfo.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/MathExtras.h"
22 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
25 printInstruction(MI, OS);
27 printAnnotation(OS, Annot);
30 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
32 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
35 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
37 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
40 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
42 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
45 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
47 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
50 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
52 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
55 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
57 if (MI->getOperand(OpNo).getImm())
61 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
63 if (MI->getOperand(OpNo).getImm())
67 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
69 if (MI->getOperand(OpNo).getImm())
73 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
75 if (MI->getOperand(OpNo).getImm()) {
77 printU16ImmDecOperand(MI, OpNo, O);
81 void AMDGPUInstPrinter::printDSOffset(const MCInst *MI, unsigned OpNo,
83 uint16_t Imm = MI->getOperand(OpNo).getImm();
86 printU16ImmDecOperand(MI, OpNo, O);
90 void AMDGPUInstPrinter::printDSOffset0(const MCInst *MI, unsigned OpNo,
93 printU8ImmDecOperand(MI, OpNo, O);
96 void AMDGPUInstPrinter::printDSOffset1(const MCInst *MI, unsigned OpNo,
99 printU8ImmDecOperand(MI, OpNo, O);
102 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
104 if (MI->getOperand(OpNo).getImm())
108 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
110 if (MI->getOperand(OpNo).getImm())
114 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
116 if (MI->getOperand(OpNo).getImm())
120 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
134 case AMDGPU::FLAT_SCR:
143 case AMDGPU::EXEC_LO:
146 case AMDGPU::EXEC_HI:
149 case AMDGPU::FLAT_SCR_LO:
150 O << "flat_scratch_lo";
152 case AMDGPU::FLAT_SCR_HI:
153 O << "flat_scratch_hi";
162 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
165 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
168 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
171 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
174 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
177 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
180 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
183 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
186 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
189 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
192 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
196 O << getRegisterName(reg);
200 // The low 8 bits of the encoding value is the register index, for both VGPRs
202 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
208 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
211 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
212 int32_t SImm = static_cast<int32_t>(Imm);
213 if (SImm >= -16 && SImm <= 64) {
218 if (Imm == FloatToBits(0.0f))
220 else if (Imm == FloatToBits(1.0f))
222 else if (Imm == FloatToBits(-1.0f))
224 else if (Imm == FloatToBits(0.5f))
226 else if (Imm == FloatToBits(-0.5f))
228 else if (Imm == FloatToBits(2.0f))
230 else if (Imm == FloatToBits(-2.0f))
232 else if (Imm == FloatToBits(4.0f))
234 else if (Imm == FloatToBits(-4.0f))
237 O << formatHex(static_cast<uint64_t>(Imm));
240 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
241 int64_t SImm = static_cast<int64_t>(Imm);
242 if (SImm >= -16 && SImm <= 64) {
247 if (Imm == DoubleToBits(0.0))
249 else if (Imm == DoubleToBits(1.0))
251 else if (Imm == DoubleToBits(-1.0))
253 else if (Imm == DoubleToBits(0.5))
255 else if (Imm == DoubleToBits(-0.5))
257 else if (Imm == DoubleToBits(2.0))
259 else if (Imm == DoubleToBits(-2.0))
261 else if (Imm == DoubleToBits(4.0))
263 else if (Imm == DoubleToBits(-4.0))
266 llvm_unreachable("64-bit literal constants not supported");
269 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
272 const MCOperand &Op = MI->getOperand(OpNo);
274 switch (Op.getReg()) {
275 // This is the default predicate state, so we don't need to print it.
276 case AMDGPU::PRED_SEL_OFF:
280 printRegOperand(Op.getReg(), O);
283 } else if (Op.isImm()) {
284 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
285 int RCID = Desc.OpInfo[OpNo].RegClass;
287 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
288 if (ImmRC.getSize() == 4)
289 printImmediate32(Op.getImm(), O);
290 else if (ImmRC.getSize() == 8)
291 printImmediate64(Op.getImm(), O);
293 llvm_unreachable("Invalid register class size");
295 // We hit this for the immediate instruction bits that don't yet have a
297 // TODO: Eventually this should be unnecessary.
298 O << formatDec(Op.getImm());
300 } else if (Op.isFPImm()) {
301 // We special case 0.0 because otherwise it will be printed as an integer.
302 if (Op.getFPImm() == 0.0)
305 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
306 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
308 if (ImmRC.getSize() == 4)
309 printImmediate32(FloatToBits(Op.getFPImm()), O);
310 else if (ImmRC.getSize() == 8)
311 printImmediate64(DoubleToBits(Op.getFPImm()), O);
313 llvm_unreachable("Invalid register class size");
315 } else if (Op.isExpr()) {
316 const MCExpr *Exp = Op.getExpr();
319 llvm_unreachable("unknown operand type in printOperand");
323 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
325 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
326 if (InputModifiers & SISrcMods::NEG)
328 if (InputModifiers & SISrcMods::ABS)
330 printOperand(MI, OpNo + 1, O);
331 if (InputModifiers & SISrcMods::ABS)
335 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
337 unsigned Imm = MI->getOperand(OpNum).getImm();
341 } else if (Imm == 1) {
343 } else if (Imm == 0) {
346 llvm_unreachable("Invalid interpolation parameter slot");
350 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
352 printOperand(MI, OpNo, O);
354 printOperand(MI, OpNo + 1, O);
357 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
358 raw_ostream &O, StringRef Asm,
360 const MCOperand &Op = MI->getOperand(OpNo);
362 if (Op.getImm() == 1) {
369 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
371 printIfSet(MI, OpNo, O, "|");
374 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
376 printIfSet(MI, OpNo, O, "_SAT");
379 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
381 if (MI->getOperand(OpNo).getImm())
385 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
387 int Imm = MI->getOperand(OpNo).getImm();
388 if (Imm == SIOutMods::MUL2)
390 else if (Imm == SIOutMods::MUL4)
392 else if (Imm == SIOutMods::DIV2)
396 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
398 int32_t Imm = MI->getOperand(OpNo).getImm();
399 O << Imm << '(' << BitsToFloat(Imm) << ')';
402 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
404 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
407 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
409 printIfSet(MI, OpNo, O, "-");
412 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
414 switch (MI->getOperand(OpNo).getImm()) {
428 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
430 printIfSet(MI, OpNo, O, "+");
433 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
435 printIfSet(MI, OpNo, O, "ExecMask,");
438 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
440 printIfSet(MI, OpNo, O, "Pred,");
443 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
445 const MCOperand &Op = MI->getOperand(OpNo);
446 if (Op.getImm() == 0) {
451 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
453 const char * chans = "XYZW";
454 int sel = MI->getOperand(OpNo).getImm();
463 O << cb << '[' << sel << ']';
464 } else if (sel >= 448) {
467 } else if (sel >= 0){
472 O << '.' << chans[chan];
475 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
477 int BankSwizzle = MI->getOperand(OpNo).getImm();
478 switch (BankSwizzle) {
480 O << "BS:VEC_021/SCL_122";
483 O << "BS:VEC_120/SCL_212";
486 O << "BS:VEC_102/SCL_221";
500 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
502 unsigned Sel = MI->getOperand(OpNo).getImm();
530 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
532 unsigned CT = MI->getOperand(OpNo).getImm();
545 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
547 int KCacheMode = MI->getOperand(OpNo).getImm();
548 if (KCacheMode > 0) {
549 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
550 O << "CB" << KCacheBank << ':';
551 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
552 int LineSize = (KCacheMode == 1) ? 16 : 32;
553 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
557 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
559 unsigned SImm16 = MI->getOperand(OpNo).getImm();
560 unsigned Msg = SImm16 & 0xF;
561 if (Msg == 2 || Msg == 3) {
562 unsigned Op = (SImm16 >> 4) & 0xF;
570 unsigned Stream = (SImm16 >> 8) & 0x3;
577 O << " stream " << Stream;
585 O << "unknown(" << Msg << ") ";
588 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
590 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
591 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
592 // works so it might be a misprint in docs.
593 unsigned SImm16 = MI->getOperand(OpNo).getImm();
594 unsigned Vmcnt = SImm16 & 0xF;
595 unsigned Expcnt = (SImm16 >> 4) & 0xF;
596 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
598 bool NeedSpace = false;
601 O << "vmcnt(" << Vmcnt << ')';
608 O << "expcnt(" << Expcnt << ')';
612 if (Lgkmcnt != 0x7) {
615 O << "lgkmcnt(" << Lgkmcnt << ')';
619 #include "AMDGPUGenAsmWriter.inc"