lib/Target/R600/AMDGPURegisterInfo.cpp

   1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "AMDGPURegisterInfo.h"
  16 #include "AMDGPUTargetMachine.h"
  17
  18 using namespace llvm;
  19
  20 AMDGPURegisterInfo::AMDGPURegisterInfo(const AMDGPUSubtarget &st)
  21 : AMDGPUGenRegisterInfo(0),
  22   ST(st)
  23   { }
  24
  25 //===----------------------------------------------------------------------===//
  26 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
  27 // they are not supported at this time.
  28 //===----------------------------------------------------------------------===//
  29
  30 const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
  31
  32 const MCPhysReg*
  33 AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
  34   return &CalleeSavedReg;
  35 }
  36
  37 void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
  38                                              int SPAdj,
  39                                              unsigned FIOperandNum,
  40                                              RegScavenger *RS) const {
  41   llvm_unreachable("Subroutines not supported yet");
  42 }
  43
  44 unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
  45   return AMDGPU::NoRegister;
  46 }
  47
  48 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
  49   static const unsigned SubRegs[] = {
  50     AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
  51     AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
  52     AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
  53     AMDGPU::sub15
  54   };
  55
  56   assert(Channel < array_lengthof(SubRegs));
  57   return SubRegs[Channel];
  58 }
  59
  60 unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
  61
  62   return getSubRegFromChannel(IndirectIndex);
  63 }
  64
  65 #define GET_REGINFO_TARGET_DESC
  66 #include "AMDGPUGenRegisterInfo.inc"