1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
39 def COND_EQ : PatLeaf <
41 [{switch(N->get()){{default: return false;
42 case ISD::SETOEQ: case ISD::SETUEQ:
43 case ISD::SETEQ: return true;}}}]
46 def COND_NE : PatLeaf <
48 [{switch(N->get()){{default: return false;
49 case ISD::SETONE: case ISD::SETUNE:
50 case ISD::SETNE: return true;}}}]
52 def COND_GT : PatLeaf <
54 [{switch(N->get()){{default: return false;
55 case ISD::SETOGT: case ISD::SETUGT:
56 case ISD::SETGT: return true;}}}]
59 def COND_GE : PatLeaf <
61 [{switch(N->get()){{default: return false;
62 case ISD::SETOGE: case ISD::SETUGE:
63 case ISD::SETGE: return true;}}}]
66 def COND_LT : PatLeaf <
68 [{switch(N->get()){{default: return false;
69 case ISD::SETOLT: case ISD::SETULT:
70 case ISD::SETLT: return true;}}}]
73 def COND_LE : PatLeaf <
75 [{switch(N->get()){{default: return false;
76 case ISD::SETOLE: case ISD::SETULE:
77 case ISD::SETLE: return true;}}}]
80 def COND_NULL : PatLeaf <
85 //===----------------------------------------------------------------------===//
86 // Load/Store Pattern Fragments
87 //===----------------------------------------------------------------------===//
89 def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
90 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
93 def zextloadi8_constant : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
94 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
97 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
98 return isLocalLoad(dyn_cast<LoadSDNode>(N));
101 def local_store : PatFrag<(ops node:$val, node:$ptr),
102 (store node:$val, node:$ptr), [{
103 return isLocalStore(dyn_cast<StoreSDNode>(N));
107 int TWO_PI = 0x40c90fdb;
109 int TWO_PI_INV = 0x3e22f983;
110 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
112 def CONST : Constants;
114 def FP_ZERO : PatLeaf <
116 [{return N->getValueAPF().isZero();}]
119 def FP_ONE : PatLeaf <
121 [{return N->isExactlyValue(1.0);}]
124 let isCodeGenOnly = 1, isPseudo = 1 in {
126 let usesCustomInserter = 1 in {
128 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
132 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
135 class FABS <RegisterClass rc> : AMDGPUShaderInst <
139 [(set f32:$dst, (fabs f32:$src0))]
142 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
146 [(set f32:$dst, (fneg f32:$src0))]
149 } // usesCustomInserter = 1
151 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
152 ComplexPattern addrPat> {
153 def RegisterLoad : AMDGPUShaderInst <
154 (outs dstClass:$dst),
155 (ins addrClass:$addr, i32imm:$chan),
156 "RegisterLoad $dst, $addr",
157 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
159 let isRegisterLoad = 1;
162 def RegisterStore : AMDGPUShaderInst <
164 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
165 "RegisterStore $val, $addr",
166 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
168 let isRegisterStore = 1;
172 } // End isCodeGenOnly = 1, isPseudo = 1
174 /* Generic helper patterns for intrinsics */
175 /* -------------------------------------- */
177 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
179 (fpow f32:$src0, f32:$src1),
180 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
183 /* Other helper patterns */
184 /* --------------------- */
186 /* Extract element pattern */
187 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
190 (sub_type (vector_extract vec_type:$src, sub_idx)),
191 (EXTRACT_SUBREG $src, sub_reg)
194 /* Insert element pattern */
195 class Insert_Element <ValueType elem_type, ValueType vec_type,
196 int sub_idx, SubRegIndex sub_reg>
198 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
199 (INSERT_SUBREG $vec, $elem, sub_reg)
202 // Vector Build pattern
203 class Vector1_Build <ValueType vecType, ValueType elemType,
204 RegisterClass rc> : Pat <
205 (vecType (build_vector elemType:$src)),
206 (vecType (COPY_TO_REGCLASS $src, rc))
209 class Vector2_Build <ValueType vecType, ValueType elemType> : Pat <
210 (vecType (build_vector elemType:$sub0, elemType:$sub1)),
211 (INSERT_SUBREG (INSERT_SUBREG
212 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1)
215 class Vector4_Build <ValueType vecType, ValueType elemType> : Pat <
216 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)),
217 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
218 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3)
221 class Vector8_Build <ValueType vecType, ValueType elemType> : Pat <
222 (vecType (build_vector elemType:$sub0, elemType:$sub1,
223 elemType:$sub2, elemType:$sub3,
224 elemType:$sub4, elemType:$sub5,
225 elemType:$sub6, elemType:$sub7)),
226 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
227 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
228 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1),
229 $sub2, sub2), $sub3, sub3),
230 $sub4, sub4), $sub5, sub5),
231 $sub6, sub6), $sub7, sub7)
234 class Vector16_Build <ValueType vecType, ValueType elemType> : Pat <
235 (vecType (build_vector elemType:$sub0, elemType:$sub1,
236 elemType:$sub2, elemType:$sub3,
237 elemType:$sub4, elemType:$sub5,
238 elemType:$sub6, elemType:$sub7,
239 elemType:$sub8, elemType:$sub9,
240 elemType:$sub10, elemType:$sub11,
241 elemType:$sub12, elemType:$sub13,
242 elemType:$sub14, elemType:$sub15)),
243 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
244 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
245 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
246 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
247 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1),
248 $sub2, sub2), $sub3, sub3),
249 $sub4, sub4), $sub5, sub5),
250 $sub6, sub6), $sub7, sub7),
251 $sub8, sub8), $sub9, sub9),
252 $sub10, sub10), $sub11, sub11),
253 $sub12, sub12), $sub13, sub13),
254 $sub14, sub14), $sub15, sub15)
257 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
258 // can handle COPY instructions.
259 // bitconvert pattern
260 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
261 (dt (bitconvert (st rc:$src0))),
265 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
266 // can handle COPY instructions.
267 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
268 (vt (AMDGPUdwordaddr (vt rc:$addr))),
274 multiclass BFIPatterns <Instruction BFI_INT> {
276 // Definition from ISA doc:
277 // (y & x) | (z & ~x)
279 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
283 // SHA-256 Ch function
286 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
292 // SHA-256 Ma patterns
294 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
295 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
296 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
297 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
300 // Bitfield extract patterns
302 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
303 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
304 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
306 class BFEPattern <Instruction BFE> : Pat <
307 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
312 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
313 (rotr i32:$src0, i32:$src1),
314 (BIT_ALIGN $src0, $src0, $src1)
317 include "R600Instructions.td"
319 include "SIInstrInfo.td"