1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
39 def COND_EQ : PatLeaf <
41 [{switch(N->get()){{default: return false;
42 case ISD::SETOEQ: case ISD::SETUEQ:
43 case ISD::SETEQ: return true;}}}]
46 def COND_NE : PatLeaf <
48 [{switch(N->get()){{default: return false;
49 case ISD::SETONE: case ISD::SETUNE:
50 case ISD::SETNE: return true;}}}]
52 def COND_GT : PatLeaf <
54 [{switch(N->get()){{default: return false;
55 case ISD::SETOGT: case ISD::SETUGT:
56 case ISD::SETGT: return true;}}}]
59 def COND_GE : PatLeaf <
61 [{switch(N->get()){{default: return false;
62 case ISD::SETOGE: case ISD::SETUGE:
63 case ISD::SETGE: return true;}}}]
66 def COND_LT : PatLeaf <
68 [{switch(N->get()){{default: return false;
69 case ISD::SETOLT: case ISD::SETULT:
70 case ISD::SETLT: return true;}}}]
73 def COND_LE : PatLeaf <
75 [{switch(N->get()){{default: return false;
76 case ISD::SETOLE: case ISD::SETULE:
77 case ISD::SETLE: return true;}}}]
80 def COND_NULL : PatLeaf <
85 //===----------------------------------------------------------------------===//
86 // Load/Store Pattern Fragments
87 //===----------------------------------------------------------------------===//
89 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
90 LoadSDNode *L = cast<LoadSDNode>(N);
91 return L->getExtensionType() == ISD::ZEXTLOAD ||
92 L->getExtensionType() == ISD::EXTLOAD;
95 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
96 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
99 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
100 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
103 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
104 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
107 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
108 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
111 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
112 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
115 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
116 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
119 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
120 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
123 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
124 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
127 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
128 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
131 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
132 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
135 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
136 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
139 def az_extloadi32_global : PatFrag<(ops node:$ptr),
140 (az_extloadi32 node:$ptr), [{
141 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
144 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
145 (az_extloadi32 node:$ptr), [{
146 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
149 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
150 (truncstorei8 node:$val, node:$ptr), [{
151 return isGlobalStore(dyn_cast<StoreSDNode>(N));
154 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
155 (truncstorei16 node:$val, node:$ptr), [{
156 return isGlobalStore(dyn_cast<StoreSDNode>(N));
159 def local_store : PatFrag<(ops node:$val, node:$ptr),
160 (store node:$val, node:$ptr), [{
161 return isLocalStore(dyn_cast<StoreSDNode>(N));
164 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
165 (truncstorei8 node:$val, node:$ptr), [{
166 return isLocalStore(dyn_cast<StoreSDNode>(N));
169 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
170 (truncstorei16 node:$val, node:$ptr), [{
171 return isLocalStore(dyn_cast<StoreSDNode>(N));
174 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
175 return isLocalLoad(dyn_cast<LoadSDNode>(N));
178 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
179 (AMDGPUstore_mskor node:$val, node:$ptr), [{
180 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
184 int TWO_PI = 0x40c90fdb;
186 int TWO_PI_INV = 0x3e22f983;
187 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
189 def CONST : Constants;
191 def FP_ZERO : PatLeaf <
193 [{return N->getValueAPF().isZero();}]
196 def FP_ONE : PatLeaf <
198 [{return N->isExactlyValue(1.0);}]
201 def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>;
202 def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>;
204 let isCodeGenOnly = 1, isPseudo = 1 in {
206 let usesCustomInserter = 1 in {
208 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
212 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
215 class FABS <RegisterClass rc> : AMDGPUShaderInst <
219 [(set f32:$dst, (fabs f32:$src0))]
222 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
226 [(set f32:$dst, (fneg f32:$src0))]
229 } // usesCustomInserter = 1
231 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
232 ComplexPattern addrPat> {
233 def RegisterLoad : AMDGPUShaderInst <
234 (outs dstClass:$dst),
235 (ins addrClass:$addr, i32imm:$chan),
236 "RegisterLoad $dst, $addr",
237 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
239 let isRegisterLoad = 1;
242 def RegisterStore : AMDGPUShaderInst <
244 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
245 "RegisterStore $val, $addr",
246 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
248 let isRegisterStore = 1;
252 } // End isCodeGenOnly = 1, isPseudo = 1
254 /* Generic helper patterns for intrinsics */
255 /* -------------------------------------- */
257 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
259 (fpow f32:$src0, f32:$src1),
260 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
263 /* Other helper patterns */
264 /* --------------------- */
266 /* Extract element pattern */
267 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
270 (sub_type (vector_extract vec_type:$src, sub_idx)),
271 (EXTRACT_SUBREG $src, sub_reg)
274 /* Insert element pattern */
275 class Insert_Element <ValueType elem_type, ValueType vec_type,
276 int sub_idx, SubRegIndex sub_reg>
278 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
279 (INSERT_SUBREG $vec, $elem, sub_reg)
282 class Vector4_Build <ValueType vecType, ValueType elemType> : Pat <
283 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)),
284 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
285 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3)
288 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
289 // can handle COPY instructions.
290 // bitconvert pattern
291 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
292 (dt (bitconvert (st rc:$src0))),
296 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
297 // can handle COPY instructions.
298 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
299 (vt (AMDGPUdwordaddr (vt rc:$addr))),
305 multiclass BFIPatterns <Instruction BFI_INT> {
307 // Definition from ISA doc:
308 // (y & x) | (z & ~x)
310 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
314 // SHA-256 Ch function
317 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
323 // SHA-256 Ma patterns
325 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
326 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
327 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
328 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
331 // Bitfield extract patterns
333 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
334 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
335 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
337 class BFEPattern <Instruction BFE> : Pat <
338 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
343 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
344 (rotr i32:$src0, i32:$src1),
345 (BIT_ALIGN $src0, $src0, $src1)
348 // 24-bit arithmetic patterns
349 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
352 class UMUL24Pattern <Instruction UMUL24> : Pat <
353 (mul U24:$x, U24:$y),
358 include "R600Instructions.td"
360 include "SIInstrInfo.td"