1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class MachineRegisterInfo;
26 class AMDGPUTargetLowering : public TargetLowering {
28 void ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
29 SmallVectorImpl<SDValue> &Args,
30 unsigned Start, unsigned Count) const;
31 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
34 /// \brief Lower vector stores by merging the vector elements into an integer
35 /// of the same bitwidth.
36 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
37 /// \brief Split a vector store into multiple scalar stores.
38 /// \returns The resulting chain.
39 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
40 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
44 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
47 /// \returns a RegisterSDNode representing Reg.
48 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
49 const TargetRegisterClass *RC,
50 unsigned Reg, EVT VT) const;
51 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
52 SelectionDAG &DAG) const;
53 /// \brief Split a vector load into multiple scalar loads.
54 SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
55 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
56 bool isHWTrueValue(SDValue Op) const;
57 bool isHWFalseValue(SDValue Op) const;
59 void AnalyzeFormalArguments(CCState &State,
60 const SmallVectorImpl<ISD::InputArg> &Ins) const;
63 AMDGPUTargetLowering(TargetMachine &TM);
65 virtual bool isFAbsFree(EVT VT) const;
66 virtual bool isFNegFree(EVT VT) const;
67 virtual MVT getVectorIdxTy() const;
68 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
70 const SmallVectorImpl<ISD::OutputArg> &Outs,
71 const SmallVectorImpl<SDValue> &OutVals,
72 SDLoc DL, SelectionDAG &DAG) const;
73 virtual SDValue LowerCall(CallLoweringInfo &CLI,
74 SmallVectorImpl<SDValue> &InVals) const {
76 llvm_unreachable("Undefined function");
79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
80 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
83 virtual const char* getTargetNodeName(unsigned Opcode) const;
85 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
89 // Functions defined in AMDILISelLowering.cpp
92 /// \brief Determine which of the bits specified in \p Mask are known to be
93 /// either zero or one and return them in the \p KnownZero and \p KnownOne
95 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
98 const SelectionDAG &DAG,
99 unsigned Depth = 0) const;
101 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
102 const CallInst &I, unsigned Intrinsic) const;
104 /// We want to mark f32/f64 floating point values as legal.
105 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
107 /// We don't want to shrink f64/f32 constants.
108 bool ShouldShrinkFPConstant(EVT VT) const;
111 void InitAMDILLowering();
112 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
122 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
123 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
127 namespace AMDGPUISD {
131 FIRST_NUMBER = ISD::BUILTIN_OP_END,
132 CALL, // Function call based on a single integer
133 UMUL, // 32bit unsigned multiplication
134 DIV_INF, // Divide with infinity returned on zero divisor
137 // End AMDIL ISD Opcodes
160 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
163 TBUFFER_STORE_FORMAT,
164 LAST_AMDGPU_ISD_NUMBER
168 } // End namespace AMDGPUISD
170 } // End namespace llvm
172 #endif // AMDGPUISELLOWERING_H