1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
27 class AMDGPUTargetLowering : public TargetLowering {
29 const AMDGPUSubtarget *Subtarget;
32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
35 SelectionDAG &DAG) const;
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 /// \brief Lower vector stores by merging the vector elements into an integer
41 /// of the same bitwidth.
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43 /// \brief Split a vector store into multiple scalar stores.
44 /// \returns The resulting chain.
45 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
50 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
53 /// \returns a RegisterSDNode representing Reg.
54 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
55 const TargetRegisterClass *RC,
56 unsigned Reg, EVT VT) const;
57 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
58 SelectionDAG &DAG) const;
59 /// \brief Split a vector load into multiple scalar loads.
60 SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
61 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
63 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
64 bool isHWTrueValue(SDValue Op) const;
65 bool isHWFalseValue(SDValue Op) const;
67 /// The SelectionDAGBuilder will automatically promote function arguments
68 /// with illegal types. However, this does not work for the AMDGPU targets
69 /// since the function arguments are stored in memory as these illegal types.
70 /// In order to handle this properly we need to get the origianl types sizes
71 /// from the LLVM IR Function and fixup the ISD:InputArg values before
72 /// passing them to AnalyzeFormalArguments()
73 void getOriginalFunctionArgs(SelectionDAG &DAG,
75 const SmallVectorImpl<ISD::InputArg> &Ins,
76 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
77 void AnalyzeFormalArguments(CCState &State,
78 const SmallVectorImpl<ISD::InputArg> &Ins) const;
81 AMDGPUTargetLowering(TargetMachine &TM);
83 virtual bool isFAbsFree(EVT VT) const override;
84 virtual bool isFNegFree(EVT VT) const override;
85 virtual bool isTruncateFree(EVT Src, EVT Dest) const override;
86 virtual bool isTruncateFree(Type *Src, Type *Dest) const override;
88 virtual bool isZExtFree(Type *Src, Type *Dest) const override;
89 virtual bool isZExtFree(EVT Src, EVT Dest) const override;
91 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
93 virtual MVT getVectorIdxTy() const override;
94 virtual bool isLoadBitCastBeneficial(EVT, EVT) const override;
95 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
97 const SmallVectorImpl<ISD::OutputArg> &Outs,
98 const SmallVectorImpl<SDValue> &OutVals,
99 SDLoc DL, SelectionDAG &DAG) const;
100 virtual SDValue LowerCall(CallLoweringInfo &CLI,
101 SmallVectorImpl<SDValue> &InVals) const;
103 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
104 virtual void ReplaceNodeResults(SDNode * N,
105 SmallVectorImpl<SDValue> &Results,
106 SelectionDAG &DAG) const override;
108 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
111 virtual const char* getTargetNodeName(unsigned Opcode) const;
113 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
117 /// \brief Determine which of the bits specified in \p Mask are known to be
118 /// either zero or one and return them in the \p KnownZero and \p KnownOne
120 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
123 const SelectionDAG &DAG,
124 unsigned Depth = 0) const override;
126 // Functions defined in AMDILISelLowering.cpp
128 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
129 const CallInst &I, unsigned Intrinsic) const;
131 /// We want to mark f32/f64 floating point values as legal.
132 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
134 /// We don't want to shrink f64/f32 constants.
135 bool ShouldShrinkFPConstant(EVT VT) const;
137 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
140 void InitAMDILLowering();
141 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
144 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
145 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
149 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
151 SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
153 SelectionDAG &DAG) const;
154 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
155 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
156 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
160 namespace AMDGPUISD {
164 FIRST_NUMBER = ISD::BUILTIN_OP_END,
165 CALL, // Function call based on a single integer
166 UMUL, // 32bit unsigned multiplication
167 DIV_INF, // Divide with infinity returned on zero divisor
170 // End AMDIL ISD Opcodes
183 BFE_U32, // Extract range of bits with zero extension to 32-bits.
184 BFE_I32, // Extract range of bits with sign extension to 32-bits.
185 BFI, // (src0 & src1) | (~src0 & src2)
186 BFM, // Insert a range of bits into a 32-bit word.
199 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
202 TBUFFER_STORE_FORMAT,
203 LAST_AMDGPU_ISD_NUMBER
207 } // End namespace AMDGPUISD
209 } // End namespace llvm
211 #endif // AMDGPUISELLOWERING_H