1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "R600InstrInfo.h"
18 #include "SIISelLowering.h"
19 #include "llvm/Analysis/ValueTracking.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/ValueMap.h"
25 #include "llvm/Support/Compiler.h"
31 //===----------------------------------------------------------------------===//
32 // Instruction Selector Implementation
33 //===----------------------------------------------------------------------===//
36 /// AMDGPU specific code to select AMDGPU machine instructions for
37 /// SelectionDAG operations.
38 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
39 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
40 // make the right decision when generating code for different targets.
41 const AMDGPUSubtarget &Subtarget;
43 AMDGPUDAGToDAGISel(TargetMachine &TM);
44 virtual ~AMDGPUDAGToDAGISel();
46 SDNode *Select(SDNode *N);
47 virtual const char *getPassName() const;
48 virtual void PostprocessISelDAG();
51 bool isInlineImmediate(SDNode *N) const;
52 inline SDValue getSmallIPtrImm(unsigned Imm);
53 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
54 const R600InstrInfo *TII);
55 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
56 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
58 // Complex pattern selectors
59 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
60 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
61 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
63 static bool checkType(const Value *ptr, unsigned int addrspace);
64 static bool checkPrivateAddress(const MachineMemOperand *Op);
66 static bool isGlobalStore(const StoreSDNode *N);
67 static bool isPrivateStore(const StoreSDNode *N);
68 static bool isLocalStore(const StoreSDNode *N);
69 static bool isRegionStore(const StoreSDNode *N);
71 bool isCPLoad(const LoadSDNode *N) const;
72 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
73 bool isGlobalLoad(const LoadSDNode *N) const;
74 bool isParamLoad(const LoadSDNode *N) const;
75 bool isPrivateLoad(const LoadSDNode *N) const;
76 bool isLocalLoad(const LoadSDNode *N) const;
77 bool isRegionLoad(const LoadSDNode *N) const;
79 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
80 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
81 bool SelectGlobalValueVariableOffset(SDValue Addr,
82 SDValue &BaseReg, SDValue& Offset);
83 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
84 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
86 // Include the pieces autogenerated from the target description.
87 #include "AMDGPUGenDAGISel.inc"
89 } // end anonymous namespace
91 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
92 // DAG, ready for instruction scheduling.
93 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
95 return new AMDGPUDAGToDAGISel(TM);
98 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
99 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
102 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
105 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
106 const SITargetLowering *TL
107 = static_cast<const SITargetLowering *>(getTargetLowering());
108 return TL->analyzeImmediate(N) == 0;
111 /// \brief Determine the register class for \p OpNo
112 /// \returns The register class of the virtual register that will be used for
113 /// the given operand number \OpNo or NULL if the register class cannot be
115 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
116 unsigned OpNo) const {
117 if (!N->isMachineOpcode()) {
120 switch (N->getMachineOpcode()) {
122 const MCInstrDesc &Desc = TM.getInstrInfo()->get(N->getMachineOpcode());
123 unsigned OpIdx = Desc.getNumDefs() + OpNo;
124 if (OpIdx >= Desc.getNumOperands())
126 int RegClass = Desc.OpInfo[OpIdx].RegClass;
127 if (RegClass == -1) {
130 return TM.getRegisterInfo()->getRegClass(RegClass);
132 case AMDGPU::REG_SEQUENCE: {
133 const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(
134 cast<ConstantSDNode>(N->getOperand(0))->getZExtValue());
136 dyn_cast<ConstantSDNode>(N->getOperand(OpNo + 1))->getZExtValue();
137 return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx);
142 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
143 return CurDAG->getTargetConstant(Imm, MVT::i32);
146 bool AMDGPUDAGToDAGISel::SelectADDRParam(
147 SDValue Addr, SDValue& R1, SDValue& R2) {
149 if (Addr.getOpcode() == ISD::FrameIndex) {
150 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
151 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
152 R2 = CurDAG->getTargetConstant(0, MVT::i32);
155 R2 = CurDAG->getTargetConstant(0, MVT::i32);
157 } else if (Addr.getOpcode() == ISD::ADD) {
158 R1 = Addr.getOperand(0);
159 R2 = Addr.getOperand(1);
162 R2 = CurDAG->getTargetConstant(0, MVT::i32);
167 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
168 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
169 Addr.getOpcode() == ISD::TargetGlobalAddress) {
172 return SelectADDRParam(Addr, R1, R2);
176 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
177 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
178 Addr.getOpcode() == ISD::TargetGlobalAddress) {
182 if (Addr.getOpcode() == ISD::FrameIndex) {
183 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
184 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
185 R2 = CurDAG->getTargetConstant(0, MVT::i64);
188 R2 = CurDAG->getTargetConstant(0, MVT::i64);
190 } else if (Addr.getOpcode() == ISD::ADD) {
191 R1 = Addr.getOperand(0);
192 R2 = Addr.getOperand(1);
195 R2 = CurDAG->getTargetConstant(0, MVT::i64);
200 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
201 unsigned int Opc = N->getOpcode();
202 if (N->isMachineOpcode()) {
204 return NULL; // Already selected.
208 // We are selecting i64 ADD here instead of custom lower it during
209 // DAG legalization, so we can fold some i64 ADDs used for address
210 // calculation into the LOAD and STORE instructions.
212 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
213 if (N->getValueType(0) != MVT::i64 ||
214 ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
218 SDValue LHS = N->getOperand(0);
219 SDValue RHS = N->getOperand(1);
221 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
222 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
224 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
225 DL, MVT::i32, LHS, Sub0);
226 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
227 DL, MVT::i32, LHS, Sub1);
229 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
230 DL, MVT::i32, RHS, Sub0);
231 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
232 DL, MVT::i32, RHS, Sub1);
234 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
236 SmallVector<SDValue, 8> AddLoArgs;
237 AddLoArgs.push_back(SDValue(Lo0, 0));
238 AddLoArgs.push_back(SDValue(Lo1, 0));
240 SDNode *AddLo = CurDAG->getMachineNode(AMDGPU::S_ADD_I32, DL,
242 SDValue Carry = SDValue(AddLo, 1);
243 SDNode *AddHi = CurDAG->getMachineNode(AMDGPU::S_ADDC_U32, DL,
244 MVT::i32, SDValue(Hi0, 0),
245 SDValue(Hi1, 0), Carry);
248 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
254 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args, 5);
256 case ISD::BUILD_VECTOR: {
258 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
259 const AMDGPURegisterInfo *TRI =
260 static_cast<const AMDGPURegisterInfo*>(TM.getRegisterInfo());
261 const SIRegisterInfo *SIRI =
262 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
263 EVT VT = N->getValueType(0);
264 unsigned NumVectorElts = VT.getVectorNumElements();
265 assert(VT.getVectorElementType().bitsEq(MVT::i32));
266 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
268 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
270 if (!U->isMachineOpcode()) {
273 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
277 if (SIRI->isSGPRClass(RC)) {
281 switch(NumVectorElts) {
282 case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID :
283 AMDGPU::SReg_32RegClassID;
285 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
286 AMDGPU::SReg_64RegClassID;
288 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
289 AMDGPU::SReg_128RegClassID;
291 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
292 AMDGPU::SReg_256RegClassID;
294 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
295 AMDGPU::SReg_512RegClassID;
297 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
300 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
301 // that adds a 128 bits reg copy when going through TwoAddressInstructions
302 // pass. We want to avoid 128 bits copies as much as possible because they
303 // can't be bundled by our scheduler.
304 switch(NumVectorElts) {
305 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
306 case 4: RegClassID = AMDGPU::R600_Reg128RegClassID; break;
307 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
311 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
313 if (NumVectorElts == 1) {
314 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS,
315 VT.getVectorElementType(),
316 N->getOperand(0), RegClass);
319 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
321 // 16 = Max Num Vector Elements
322 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
323 // 1 = Vector Register Class
324 SDValue RegSeqArgs[16 * 2 + 1];
326 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
327 bool IsRegSeq = true;
328 for (unsigned i = 0; i < N->getNumOperands(); i++) {
329 // XXX: Why is this here?
330 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
334 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
335 RegSeqArgs[1 + (2 * i) + 1] =
336 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
340 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
341 RegSeqArgs, 2 * N->getNumOperands() + 1);
343 case ISD::BUILD_PAIR: {
344 SDValue RC, SubReg0, SubReg1;
345 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
346 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
349 if (N->getValueType(0) == MVT::i128) {
350 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
351 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
352 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
353 } else if (N->getValueType(0) == MVT::i64) {
354 RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
355 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
356 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
358 llvm_unreachable("Unhandled value type for BUILD_PAIR");
360 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
361 N->getOperand(1), SubReg1 };
362 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
363 SDLoc(N), N->getValueType(0), Ops);
367 case ISD::ConstantFP: {
368 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
369 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
370 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
374 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
375 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
377 ConstantSDNode *C = cast<ConstantSDNode>(N);
378 Imm = C->getZExtValue();
381 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
382 CurDAG->getConstant(Imm & 0xFFFFFFFF, MVT::i32));
383 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
384 CurDAG->getConstant(Imm >> 32, MVT::i32));
385 const SDValue Ops[] = {
386 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
387 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
388 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
391 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N),
392 N->getValueType(0), Ops);
395 case AMDGPUISD::REGISTER_LOAD: {
396 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
397 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
399 SDValue Addr, Offset;
401 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
402 const SDValue Ops[] = {
405 CurDAG->getTargetConstant(0, MVT::i32),
408 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
409 CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
412 case AMDGPUISD::REGISTER_STORE: {
413 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
414 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
416 SDValue Addr, Offset;
417 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
418 const SDValue Ops[] = {
422 CurDAG->getTargetConstant(0, MVT::i32),
425 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
426 CurDAG->getVTList(MVT::Other),
430 return SelectCode(N);
434 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
435 assert(addrspace != 0 && "Use checkPrivateAddress instead.");
439 Type *ptrType = ptr->getType();
440 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
443 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
444 if (Op->getPseudoValue()) return true;
445 const Value *ptr = Op->getValue();
446 if (!ptr) return false;
447 PointerType *ptrType = dyn_cast<PointerType>(ptr->getType());
448 return ptrType->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
451 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
452 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
455 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
456 return (!checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS)
457 && !checkType(N->getMemOperand()->getValue(),
458 AMDGPUAS::GLOBAL_ADDRESS)
459 && !checkType(N->getMemOperand()->getValue(),
460 AMDGPUAS::REGION_ADDRESS));
463 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
464 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
467 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
468 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
471 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
473 return checkType(N->getMemOperand()->getValue(),
474 AMDGPUAS::CONSTANT_ADDRESS);
476 return checkType(N->getMemOperand()->getValue(),
477 AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
480 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
481 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
482 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
483 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
484 N->getMemoryVT().bitsLT(MVT::i32)) {
488 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
491 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
492 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
495 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
496 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
499 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
500 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
503 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
504 MachineMemOperand *MMO = N->getMemOperand();
505 if (checkPrivateAddress(N->getMemOperand())) {
507 const PseudoSourceValue *PSV = MMO->getPseudoValue();
508 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
516 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
517 if (checkPrivateAddress(N->getMemOperand())) {
518 // Check to make sure we are not a constant pool load or a constant load
519 // that is marked as a private load
520 if (isCPLoad(N) || isConstantLoad(N, -1)) {
524 if (!checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS)
525 && !checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS)
526 && !checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS)
527 && !checkType(N->getMemOperand()->getValue(), AMDGPUAS::CONSTANT_ADDRESS)
528 && !checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_D_ADDRESS)
529 && !checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS)){
535 const char *AMDGPUDAGToDAGISel::getPassName() const {
536 return "AMDGPU DAG->DAG Pattern Instruction Selection";
544 //===----------------------------------------------------------------------===//
546 //===----------------------------------------------------------------------===//
548 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
550 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
551 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
557 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
558 SDValue& BaseReg, SDValue &Offset) {
559 if (!dyn_cast<ConstantSDNode>(Addr)) {
561 Offset = CurDAG->getIntPtrConstant(0, true);
567 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
569 ConstantSDNode * IMMOffset;
571 if (Addr.getOpcode() == ISD::ADD
572 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
573 && isInt<16>(IMMOffset->getZExtValue())) {
575 Base = Addr.getOperand(0);
576 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
578 // If the pointer address is constant, we can move it to the offset field.
579 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
580 && isInt<16>(IMMOffset->getZExtValue())) {
581 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
582 SDLoc(CurDAG->getEntryNode()),
583 AMDGPU::ZERO, MVT::i32);
584 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
588 // Default case, no offset
590 Offset = CurDAG->getTargetConstant(0, MVT::i32);
594 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
598 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
599 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
600 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
601 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
602 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
603 Base = Addr.getOperand(0);
604 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
607 Offset = CurDAG->getTargetConstant(0, MVT::i32);
613 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
614 const AMDGPUTargetLowering& Lowering =
615 (*(const AMDGPUTargetLowering*)getTargetLowering());
616 bool IsModified = false;
619 // Go over all selected nodes and try to fold them a bit more
620 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
621 E = CurDAG->allnodes_end(); I != E; ++I) {
625 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
629 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
630 if (ResNode != Node) {
631 ReplaceUses(Node, ResNode);
635 CurDAG->RemoveDeadNodes();
636 } while (IsModified);