lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19 #include "AMDGPUAsmPrinter.h"
  20 #include "InstPrinter/AMDGPUInstPrinter.h"
  21 #include "AMDGPU.h"
  22 #include "AMDKernelCodeT.h"
  23 #include "AMDGPUSubtarget.h"
  24 #include "R600Defines.h"
  25 #include "R600MachineFunctionInfo.h"
  26 #include "R600RegisterInfo.h"
  27 #include "SIDefines.h"
  28 #include "SIMachineFunctionInfo.h"
  29 #include "SIRegisterInfo.h"
  30 #include "llvm/CodeGen/MachineFrameInfo.h"
  31 #include "llvm/MC/MCContext.h"
  32 #include "llvm/MC/MCSectionELF.h"
  33 #include "llvm/MC/MCStreamer.h"
  34 #include "llvm/Support/ELF.h"
  35 #include "llvm/Support/MathExtras.h"
  36 #include "llvm/Support/TargetRegistry.h"
  37 #include "llvm/Target/TargetLoweringObjectFile.h"
  38
  39 using namespace llvm;
  40
  41 // TODO: This should get the default rounding mode from the kernel. We just set
  42 // the default here, but this could change if the OpenCL rounding mode pragmas
  43 // are used.
  44 //
  45 // The denormal mode here should match what is reported by the OpenCL runtime
  46 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
  47 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
  48 //
  49 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
  50 // precision, and leaves single precision to flush all and does not report
  51 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
  52 // CL_FP_DENORM for both.
  53 //
  54 // FIXME: It seems some instructions do not support single precision denormals
  55 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
  56 // and sin_f32, cos_f32 on most parts).
  57
  58 // We want to use these instructions, and using fp32 denormals also causes
  59 // instructions to run at the double precision rate for the device so it's
  60 // probably best to just report no single precision denormals.
  61 static uint32_t getFPMode(const MachineFunction &F) {
  62   const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
  63   // TODO: Is there any real use for the flush in only / flush out only modes?
  64
  65   uint32_t FP32Denormals =
  66     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  67
  68   uint32_t FP64Denormals =
  69     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  70
  71   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
  72          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
  73          FP_DENORM_MODE_SP(FP32Denormals) |
  74          FP_DENORM_MODE_DP(FP64Denormals);
  75 }
  76
  77 static AsmPrinter *
  78 createAMDGPUAsmPrinterPass(TargetMachine &tm,
  79                            std::unique_ptr<MCStreamer> &&Streamer) {
  80   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
  81 }
  82
  83 extern "C" void LLVMInitializeR600AsmPrinter() {
  84   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  85   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
  86 }
  87
  88 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
  89                                    std::unique_ptr<MCStreamer> Streamer)
  90     : AsmPrinter(TM, std::move(Streamer)) {}
  91
  92 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
  93
  94   // This label is used to mark the end of the .text section.
  95   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
  96   OutStreamer.SwitchSection(TLOF.getTextSection());
  97   MCSymbol *EndOfTextLabel =
  98       OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
  99   OutStreamer.EmitLabel(EndOfTextLabel);
 100 }
 101
 102 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 103
 104   // The starting address of all shader programs must be 256 bytes aligned.
 105   MF.setAlignment(8);
 106
 107   SetupMachineFunction(MF);
 108
 109   MCContext &Context = getObjFileLowering().getContext();
 110   const MCSectionELF *ConfigSection =
 111       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
 112   OutStreamer.SwitchSection(ConfigSection);
 113
 114   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 115   SIProgramInfo KernelInfo;
 116   if (STM.isAmdHsaOS()) {
 117     getSIProgramInfo(KernelInfo, MF);
 118     EmitAmdKernelCodeT(MF, KernelInfo);
 119     OutStreamer.EmitCodeAlignment(2 << (MF.getAlignment() - 1));
 120   } else if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 121     getSIProgramInfo(KernelInfo, MF);
 122     EmitProgramInfoSI(MF, KernelInfo);
 123   } else {
 124     EmitProgramInfoR600(MF);
 125   }
 126
 127   DisasmLines.clear();
 128   HexLines.clear();
 129   DisasmLineMaxLen = 0;
 130
 131   EmitFunctionBody();
 132
 133   if (isVerbose()) {
 134     const MCSectionELF *CommentSection =
 135         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
 136     OutStreamer.SwitchSection(CommentSection);
 137
 138     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 139       OutStreamer.emitRawComment(" Kernel info:", false);
 140       OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
 141                                  false);
 142       OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
 143                                  false);
 144       OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
 145                                  false);
 146       OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
 147                                  false);
 148       OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
 149                                  false);
 150       OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
 151                                  false);
 152     } else {
 153       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 154       OutStreamer.emitRawComment(
 155         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 156     }
 157   }
 158
 159   if (STM.dumpCode()) {
 160
 161     OutStreamer.SwitchSection(
 162         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
 163
 164     for (size_t i = 0; i < DisasmLines.size(); ++i) {
 165       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 166       Comment += " ; " + HexLines[i] + "\n";
 167
 168       OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 169       OutStreamer.EmitBytes(StringRef(Comment));
 170     }
 171   }
 172
 173   return false;
 174 }
 175
 176 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
 177   unsigned MaxGPR = 0;
 178   bool killPixel = false;
 179   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 180   const R600RegisterInfo *RI =
 181       static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
 182   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 183
 184   for (const MachineBasicBlock &MBB : MF) {
 185     for (const MachineInstr &MI : MBB) {
 186       if (MI.getOpcode() == AMDGPU::KILLGT)
 187         killPixel = true;
 188       unsigned numOperands = MI.getNumOperands();
 189       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 190         const MachineOperand &MO = MI.getOperand(op_idx);
 191         if (!MO.isReg())
 192           continue;
 193         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 194
 195         // Register with value > 127 aren't GPR
 196         if (HWReg > 127)
 197           continue;
 198         MaxGPR = std::max(MaxGPR, HWReg);
 199       }
 200     }
 201   }
 202
 203   unsigned RsrcReg;
 204   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 205     // Evergreen / Northern Islands
 206     switch (MFI->getShaderType()) {
 207     default: // Fall through
 208     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 209     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 210     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 211     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 212     }
 213   } else {
 214     // R600 / R700
 215     switch (MFI->getShaderType()) {
 216     default: // Fall through
 217     case ShaderType::GEOMETRY: // Fall through
 218     case ShaderType::COMPUTE:  // Fall through
 219     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 220     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 221     }
 222   }
 223
 224   OutStreamer.EmitIntValue(RsrcReg, 4);
 225   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 226                            S_STACK_SIZE(MFI->StackSize), 4);
 227   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 228   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 229
 230   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 231     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 232     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 233   }
 234 }
 235
 236 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 237                                         const MachineFunction &MF) const {
 238   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 239   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 240   uint64_t CodeSize = 0;
 241   unsigned MaxSGPR = 0;
 242   unsigned MaxVGPR = 0;
 243   bool VCCUsed = false;
 244   bool FlatUsed = false;
 245   const SIRegisterInfo *RI =
 246       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
 247
 248   for (const MachineBasicBlock &MBB : MF) {
 249     for (const MachineInstr &MI : MBB) {
 250       // TODO: CodeSize should account for multiple functions.
 251       CodeSize += MI.getDesc().Size;
 252
 253       unsigned numOperands = MI.getNumOperands();
 254       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 255         const MachineOperand &MO = MI.getOperand(op_idx);
 256         unsigned width = 0;
 257         bool isSGPR = false;
 258
 259         if (!MO.isReg()) {
 260           continue;
 261         }
 262         unsigned reg = MO.getReg();
 263         if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
 264             reg == AMDGPU::VCC_HI) {
 265           VCCUsed = true;
 266           continue;
 267         } else if (reg == AMDGPU::FLAT_SCR ||
 268                    reg == AMDGPU::FLAT_SCR_LO ||
 269                    reg == AMDGPU::FLAT_SCR_HI) {
 270           FlatUsed = true;
 271           continue;
 272         }
 273
 274         switch (reg) {
 275         default: break;
 276         case AMDGPU::SCC:
 277         case AMDGPU::EXEC:
 278         case AMDGPU::M0:
 279           continue;
 280         }
 281
 282         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 283           isSGPR = true;
 284           width = 1;
 285         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
 286           isSGPR = false;
 287           width = 1;
 288         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 289           isSGPR = true;
 290           width = 2;
 291         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 292           isSGPR = false;
 293           width = 2;
 294         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 295           isSGPR = false;
 296           width = 3;
 297         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 298           isSGPR = true;
 299           width = 4;
 300         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 301           isSGPR = false;
 302           width = 4;
 303         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 304           isSGPR = true;
 305           width = 8;
 306         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 307           isSGPR = false;
 308           width = 8;
 309         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 310           isSGPR = true;
 311           width = 16;
 312         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 313           isSGPR = false;
 314           width = 16;
 315         } else {
 316           llvm_unreachable("Unknown register class");
 317         }
 318         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 319         unsigned maxUsed = hwReg + width - 1;
 320         if (isSGPR) {
 321           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 322         } else {
 323           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 324         }
 325       }
 326     }
 327   }
 328
 329   if (VCCUsed)
 330     MaxSGPR += 2;
 331
 332   if (FlatUsed)
 333     MaxSGPR += 2;
 334
 335   // We found the maximum register index. They start at 0, so add one to get the
 336   // number of registers.
 337   ProgInfo.NumVGPR = MaxVGPR + 1;
 338   ProgInfo.NumSGPR = MaxSGPR + 1;
 339
 340   if (STM.hasSGPRInitBug()) {
 341     if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG)
 342       llvm_unreachable("Too many SGPRs used with the SGPR init bug");
 343
 344     ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
 345   }
 346
 347   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
 348   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
 349   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
 350   // register.
 351   ProgInfo.FloatMode = getFPMode(MF);
 352
 353   // XXX: Not quite sure what this does, but sc seems to unset this.
 354   ProgInfo.IEEEMode = 0;
 355
 356   // Do not clamp NAN to 0.
 357   ProgInfo.DX10Clamp = 0;
 358
 359   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
 360   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
 361
 362   ProgInfo.FlatUsed = FlatUsed;
 363   ProgInfo.VCCUsed = VCCUsed;
 364   ProgInfo.CodeLen = CodeSize;
 365
 366   unsigned LDSAlignShift;
 367   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 368     // LDS is allocated in 64 dword blocks.
 369     LDSAlignShift = 8;
 370   } else {
 371     // LDS is allocated in 128 dword blocks.
 372     LDSAlignShift = 9;
 373   }
 374
 375   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
 376                           MFI->getMaximumWorkGroupSize(MF);
 377
 378   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
 379   ProgInfo.LDSBlocks =
 380      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 381
 382   // Scratch is allocated in 256 dword blocks.
 383   unsigned ScratchAlignShift = 10;
 384   // We need to program the hardware with the amount of scratch memory that
 385   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
 386   // scratch memory used per thread.
 387   ProgInfo.ScratchBlocks =
 388     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
 389                        1 << ScratchAlignShift) >> ScratchAlignShift;
 390
 391   ProgInfo.ComputePGMRSrc1 =
 392       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
 393       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
 394       S_00B848_PRIORITY(ProgInfo.Priority) |
 395       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
 396       S_00B848_PRIV(ProgInfo.Priv) |
 397       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
 398       S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
 399       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
 400
 401   ProgInfo.ComputePGMRSrc2 =
 402       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
 403       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
 404       S_00B84C_TGID_X_EN(1) |
 405       S_00B84C_TGID_Y_EN(1) |
 406       S_00B84C_TGID_Z_EN(1) |
 407       S_00B84C_TG_SIZE_EN(1) |
 408       S_00B84C_TIDIG_COMP_CNT(2) |
 409       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
 410 }
 411
 412 static unsigned getRsrcReg(unsigned ShaderType) {
 413   switch (ShaderType) {
 414   default: // Fall through
 415   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
 416   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
 417   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
 418   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
 419   }
 420 }
 421
 422 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
 423                                          const SIProgramInfo &KernelInfo) {
 424   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 425   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 426   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
 427
 428   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 429     OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
 430
 431     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
 432
 433     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 434     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
 435
 436     OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
 437     OutStreamer.EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 438
 439     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
 440     // 0" comment but I don't see a corresponding field in the register spec.
 441   } else {
 442     OutStreamer.EmitIntValue(RsrcReg, 4);
 443     OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
 444                              S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
 445     if (STM.isVGPRSpillingEnabled(MFI)) {
 446       OutStreamer.EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
 447       OutStreamer.EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 448     }
 449   }
 450
 451   if (MFI->getShaderType() == ShaderType::PIXEL) {
 452     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 453     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
 454     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 455     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 456   }
 457 }
 458
 459 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
 460                                         const SIProgramInfo &KernelInfo) const {
 461   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 462   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 463   amd_kernel_code_t header;
 464
 465   memset(&header, 0, sizeof(header));
 466
 467   header.amd_code_version_major = AMD_CODE_VERSION_MAJOR;
 468   header.amd_code_version_minor = AMD_CODE_VERSION_MINOR;
 469
 470   header.struct_byte_size = sizeof(amd_kernel_code_t);
 471
 472   header.target_chip = STM.getAmdKernelCodeChipID();
 473
 474   header.kernel_code_entry_byte_offset = (1ULL << MF.getAlignment());
 475
 476   header.compute_pgm_resource_registers =
 477       KernelInfo.ComputePGMRSrc1 |
 478       (KernelInfo.ComputePGMRSrc2 << 32);
 479
 480   // Code Properties:
 481   header.code_properties = AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
 482                            AMD_CODE_PROPERTY_IS_PTR64;
 483
 484   if (KernelInfo.FlatUsed)
 485     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
 486
 487   if (KernelInfo.ScratchBlocks)
 488     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE;
 489
 490   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
 491   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
 492
 493   // MFI->ABIArgOffset is the number of bytes for the kernel arguments
 494   // plus 36.  36 is the number of bytes reserved at the begining of the
 495   // input buffer to store work-group size information.
 496   // FIXME: We should be adding the size of the implicit arguments
 497   // to this value.
 498   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
 499
 500   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
 501   header.workitem_vgpr_count = KernelInfo.NumVGPR;
 502
 503   // FIXME: What values do I put for these alignments
 504   header.kernarg_segment_alignment = 0;
 505   header.group_segment_alignment = 0;
 506   header.private_segment_alignment = 0;
 507
 508   header.code_type = 1; // HSA_EXT_CODE_KERNEL
 509
 510   header.wavefront_size = STM.getWavefrontSize();
 511
 512   const MCSectionELF *VersionSection =
 513       OutContext.getELFSection(".hsa.version", ELF::SHT_PROGBITS, 0);
 514   OutStreamer.SwitchSection(VersionSection);
 515   OutStreamer.EmitBytes(Twine("HSA Code Unit:" +
 516                         Twine(header.hsail_version_major) + "." +
 517                         Twine(header.hsail_version_minor) + ":" +
 518                         "AMD:" +
 519                         Twine(header.amd_code_version_major) + "." +
 520                         Twine(header.amd_code_version_minor) +  ":" +
 521                         "GFX8.1:0").str());
 522
 523   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 524
 525   if (isVerbose()) {
 526     OutStreamer.emitRawComment("amd_code_version_major = " +
 527                                Twine(header.amd_code_version_major), false);
 528     OutStreamer.emitRawComment("amd_code_version_minor = " +
 529                                Twine(header.amd_code_version_minor), false);
 530     OutStreamer.emitRawComment("struct_byte_size = " +
 531                                Twine(header.struct_byte_size), false);
 532     OutStreamer.emitRawComment("target_chip = " +
 533                                Twine(header.target_chip), false);
 534     OutStreamer.emitRawComment(" compute_pgm_rsrc1: " +
 535                                Twine::utohexstr(KernelInfo.ComputePGMRSrc1), false);
 536     OutStreamer.emitRawComment(" compute_pgm_rsrc2: " +
 537                                Twine::utohexstr(KernelInfo.ComputePGMRSrc2), false);
 538     OutStreamer.emitRawComment("enable_sgpr_private_segment_buffer = " +
 539       Twine((bool)(header.code_properties &
 540                    AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE)), false);
 541     OutStreamer.emitRawComment("enable_sgpr_kernarg_segment_ptr = " +
 542       Twine((bool)(header.code_properties &
 543                    AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)), false);
 544     OutStreamer.emitRawComment("private_element_size = 2 ", false);
 545     OutStreamer.emitRawComment("is_ptr64 = " +
 546         Twine((bool)(header.code_properties & AMD_CODE_PROPERTY_IS_PTR64)), false);
 547     OutStreamer.emitRawComment("workitem_private_segment_byte_size = " +
 548                                Twine(header.workitem_private_segment_byte_size),
 549                                false);
 550     OutStreamer.emitRawComment("workgroup_group_segment_byte_size = " +
 551                                Twine(header.workgroup_group_segment_byte_size),
 552                                false);
 553     OutStreamer.emitRawComment("gds_segment_byte_size = " +
 554                                Twine(header.gds_segment_byte_size), false);
 555     OutStreamer.emitRawComment("kernarg_segment_byte_size = " +
 556                                Twine(header.kernarg_segment_byte_size), false);
 557     OutStreamer.emitRawComment("wavefront_sgpr_count = " +
 558                                Twine(header.wavefront_sgpr_count), false);
 559     OutStreamer.emitRawComment("workitem_vgpr_count = " +
 560                                Twine(header.workitem_vgpr_count), false);
 561     OutStreamer.emitRawComment("code_type = " + Twine(header.code_type), false);
 562     OutStreamer.emitRawComment("wavefront_size = " +
 563                                Twine((int)header.wavefront_size), false);
 564     OutStreamer.emitRawComment("optimization_level = " +
 565                                Twine(header.optimization_level), false);
 566     OutStreamer.emitRawComment("hsail_profile = " +
 567                                Twine(header.hsail_profile), false);
 568     OutStreamer.emitRawComment("hsail_machine_model = " +
 569                                Twine(header.hsail_machine_model), false);
 570     OutStreamer.emitRawComment("hsail_version_major = " +
 571                                Twine(header.hsail_version_major), false);
 572     OutStreamer.emitRawComment("hsail_version_minor = " +
 573                                Twine(header.hsail_version_minor), false);
 574   }
 575
 576   OutStreamer.EmitBytes(StringRef((char*)&header, sizeof(header)));
 577 }
 578
 579 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
 580                                        unsigned AsmVariant,
 581                                        const char *ExtraCode, raw_ostream &O) {
 582   if (ExtraCode && ExtraCode[0]) {
 583     if (ExtraCode[1] != 0)
 584       return true; // Unknown modifier.
 585
 586     switch (ExtraCode[0]) {
 587     default:
 588       // See if this is a generic print operand
 589       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
 590     case 'r':
 591       break;
 592     }
 593   }
 594
 595   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
 596                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
 597   return false;
 598 }