lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19 #include "AMDGPUAsmPrinter.h"
  20 #include "AMDGPU.h"
  21 #include "AMDKernelCodeT.h"
  22 #include "AMDGPUSubtarget.h"
  23 #include "R600Defines.h"
  24 #include "R600MachineFunctionInfo.h"
  25 #include "R600RegisterInfo.h"
  26 #include "SIDefines.h"
  27 #include "SIMachineFunctionInfo.h"
  28 #include "SIRegisterInfo.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/MC/MCContext.h"
  31 #include "llvm/MC/MCSectionELF.h"
  32 #include "llvm/MC/MCStreamer.h"
  33 #include "llvm/Support/ELF.h"
  34 #include "llvm/Support/MathExtras.h"
  35 #include "llvm/Support/TargetRegistry.h"
  36 #include "llvm/Target/TargetLoweringObjectFile.h"
  37
  38 using namespace llvm;
  39
  40 // TODO: This should get the default rounding mode from the kernel. We just set
  41 // the default here, but this could change if the OpenCL rounding mode pragmas
  42 // are used.
  43 //
  44 // The denormal mode here should match what is reported by the OpenCL runtime
  45 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
  46 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
  47 //
  48 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
  49 // precision, and leaves single precision to flush all and does not report
  50 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
  51 // CL_FP_DENORM for both.
  52 //
  53 // FIXME: It seems some instructions do not support single precision denormals
  54 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
  55 // and sin_f32, cos_f32 on most parts).
  56
  57 // We want to use these instructions, and using fp32 denormals also causes
  58 // instructions to run at the double precision rate for the device so it's
  59 // probably best to just report no single precision denormals.
  60 static uint32_t getFPMode(const MachineFunction &F) {
  61   const AMDGPUSubtarget& ST = F.getTarget().getSubtarget<AMDGPUSubtarget>();
  62   // TODO: Is there any real use for the flush in only / flush out only modes?
  63
  64   uint32_t FP32Denormals =
  65     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  66
  67   uint32_t FP64Denormals =
  68     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  69
  70   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
  71          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
  72          FP_DENORM_MODE_SP(FP32Denormals) |
  73          FP_DENORM_MODE_DP(FP64Denormals);
  74 }
  75
  76 static AsmPrinter *
  77 createAMDGPUAsmPrinterPass(TargetMachine &tm,
  78                            std::unique_ptr<MCStreamer> &&Streamer) {
  79   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
  80 }
  81
  82 extern "C" void LLVMInitializeR600AsmPrinter() {
  83   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  84   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
  85 }
  86
  87 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
  88                                    std::unique_ptr<MCStreamer> Streamer)
  89     : AsmPrinter(TM, std::move(Streamer)) {
  90   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
  91 }
  92
  93 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
  94
  95   // This label is used to mark the end of the .text section.
  96   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
  97   OutStreamer.SwitchSection(TLOF.getTextSection());
  98   MCSymbol *EndOfTextLabel =
  99       OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
 100   OutStreamer.EmitLabel(EndOfTextLabel);
 101 }
 102
 103 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 104
 105   // The starting address of all shader programs must be 256 bytes aligned.
 106   MF.setAlignment(8);
 107
 108   SetupMachineFunction(MF);
 109
 110   EmitFunctionHeader();
 111
 112   MCContext &Context = getObjFileLowering().getContext();
 113   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
 114                                               ELF::SHT_PROGBITS, 0,
 115                                               SectionKind::getReadOnly());
 116   OutStreamer.SwitchSection(ConfigSection);
 117
 118   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 119   SIProgramInfo KernelInfo;
 120   if (STM.isAmdHsaOS()) {
 121     getSIProgramInfo(KernelInfo, MF);
 122     EmitAmdKernelCodeT(MF, KernelInfo);
 123     OutStreamer.EmitCodeAlignment(2 << (MF.getAlignment() - 1));
 124   } else if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 125     getSIProgramInfo(KernelInfo, MF);
 126     EmitProgramInfoSI(MF, KernelInfo);
 127   } else {
 128     EmitProgramInfoR600(MF);
 129   }
 130
 131   DisasmLines.clear();
 132   HexLines.clear();
 133   DisasmLineMaxLen = 0;
 134
 135   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 136   EmitFunctionBody();
 137
 138   if (isVerbose()) {
 139     const MCSectionELF *CommentSection
 140       = Context.getELFSection(".AMDGPU.csdata",
 141                               ELF::SHT_PROGBITS, 0,
 142                               SectionKind::getReadOnly());
 143     OutStreamer.SwitchSection(CommentSection);
 144
 145     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 146       OutStreamer.emitRawComment(" Kernel info:", false);
 147       OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
 148                                  false);
 149       OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
 150                                  false);
 151       OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
 152                                  false);
 153       OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
 154                                  false);
 155       OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
 156                                  false);
 157       OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
 158                                  false);
 159     } else {
 160       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 161       OutStreamer.emitRawComment(
 162         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 163     }
 164   }
 165
 166   if (STM.dumpCode() && DisasmEnabled) {
 167
 168     OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
 169                                                 ELF::SHT_NOTE, 0,
 170                                                 SectionKind::getReadOnly()));
 171
 172     for (size_t i = 0; i < DisasmLines.size(); ++i) {
 173       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 174       Comment += " ; " + HexLines[i] + "\n";
 175
 176       OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 177       OutStreamer.EmitBytes(StringRef(Comment));
 178     }
 179   }
 180
 181   return false;
 182 }
 183
 184 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
 185   unsigned MaxGPR = 0;
 186   bool killPixel = false;
 187   const R600RegisterInfo *RI = static_cast<const R600RegisterInfo *>(
 188       TM.getSubtargetImpl()->getRegisterInfo());
 189   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 190   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 191
 192   for (const MachineBasicBlock &MBB : MF) {
 193     for (const MachineInstr &MI : MBB) {
 194       if (MI.getOpcode() == AMDGPU::KILLGT)
 195         killPixel = true;
 196       unsigned numOperands = MI.getNumOperands();
 197       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 198         const MachineOperand &MO = MI.getOperand(op_idx);
 199         if (!MO.isReg())
 200           continue;
 201         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 202
 203         // Register with value > 127 aren't GPR
 204         if (HWReg > 127)
 205           continue;
 206         MaxGPR = std::max(MaxGPR, HWReg);
 207       }
 208     }
 209   }
 210
 211   unsigned RsrcReg;
 212   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 213     // Evergreen / Northern Islands
 214     switch (MFI->getShaderType()) {
 215     default: // Fall through
 216     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 217     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 218     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 219     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 220     }
 221   } else {
 222     // R600 / R700
 223     switch (MFI->getShaderType()) {
 224     default: // Fall through
 225     case ShaderType::GEOMETRY: // Fall through
 226     case ShaderType::COMPUTE:  // Fall through
 227     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 228     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 229     }
 230   }
 231
 232   OutStreamer.EmitIntValue(RsrcReg, 4);
 233   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 234                            S_STACK_SIZE(MFI->StackSize), 4);
 235   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 236   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 237
 238   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 239     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 240     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 241   }
 242 }
 243
 244 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 245                                         const MachineFunction &MF) const {
 246   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 247   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 248   uint64_t CodeSize = 0;
 249   unsigned MaxSGPR = 0;
 250   unsigned MaxVGPR = 0;
 251   bool VCCUsed = false;
 252   bool FlatUsed = false;
 253   const SIRegisterInfo *RI = static_cast<const SIRegisterInfo *>(
 254       TM.getSubtargetImpl()->getRegisterInfo());
 255
 256   for (const MachineBasicBlock &MBB : MF) {
 257     for (const MachineInstr &MI : MBB) {
 258       // TODO: CodeSize should account for multiple functions.
 259       CodeSize += MI.getDesc().Size;
 260
 261       unsigned numOperands = MI.getNumOperands();
 262       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 263         const MachineOperand &MO = MI.getOperand(op_idx);
 264         unsigned width = 0;
 265         bool isSGPR = false;
 266
 267         if (!MO.isReg()) {
 268           continue;
 269         }
 270         unsigned reg = MO.getReg();
 271         if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
 272             reg == AMDGPU::VCC_HI) {
 273           VCCUsed = true;
 274           continue;
 275         } else if (reg == AMDGPU::FLAT_SCR ||
 276                    reg == AMDGPU::FLAT_SCR_LO ||
 277                    reg == AMDGPU::FLAT_SCR_HI) {
 278           FlatUsed = true;
 279           continue;
 280         }
 281
 282         switch (reg) {
 283         default: break;
 284         case AMDGPU::SCC:
 285         case AMDGPU::EXEC:
 286         case AMDGPU::M0:
 287           continue;
 288         }
 289
 290         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 291           isSGPR = true;
 292           width = 1;
 293         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
 294           isSGPR = false;
 295           width = 1;
 296         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 297           isSGPR = true;
 298           width = 2;
 299         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 300           isSGPR = false;
 301           width = 2;
 302         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 303           isSGPR = false;
 304           width = 3;
 305         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 306           isSGPR = true;
 307           width = 4;
 308         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 309           isSGPR = false;
 310           width = 4;
 311         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 312           isSGPR = true;
 313           width = 8;
 314         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 315           isSGPR = false;
 316           width = 8;
 317         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 318           isSGPR = true;
 319           width = 16;
 320         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 321           isSGPR = false;
 322           width = 16;
 323         } else {
 324           llvm_unreachable("Unknown register class");
 325         }
 326         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 327         unsigned maxUsed = hwReg + width - 1;
 328         if (isSGPR) {
 329           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 330         } else {
 331           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 332         }
 333       }
 334     }
 335   }
 336
 337   if (VCCUsed)
 338     MaxSGPR += 2;
 339
 340   if (FlatUsed)
 341     MaxSGPR += 2;
 342
 343   // We found the maximum register index. They start at 0, so add one to get the
 344   // number of registers.
 345   ProgInfo.NumVGPR = MaxVGPR + 1;
 346   ProgInfo.NumSGPR = MaxSGPR + 1;
 347
 348   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
 349   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
 350   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
 351   // register.
 352   ProgInfo.FloatMode = getFPMode(MF);
 353
 354   // XXX: Not quite sure what this does, but sc seems to unset this.
 355   ProgInfo.IEEEMode = 0;
 356
 357   // Do not clamp NAN to 0.
 358   ProgInfo.DX10Clamp = 0;
 359
 360   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
 361   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
 362
 363   ProgInfo.FlatUsed = FlatUsed;
 364   ProgInfo.VCCUsed = VCCUsed;
 365   ProgInfo.CodeLen = CodeSize;
 366
 367   unsigned LDSAlignShift;
 368   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 369     // LDS is allocated in 64 dword blocks.
 370     LDSAlignShift = 8;
 371   } else {
 372     // LDS is allocated in 128 dword blocks.
 373     LDSAlignShift = 9;
 374   }
 375
 376   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
 377                           MFI->getMaximumWorkGroupSize(MF);
 378
 379   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
 380   ProgInfo.LDSBlocks =
 381      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 382
 383   // Scratch is allocated in 256 dword blocks.
 384   unsigned ScratchAlignShift = 10;
 385   // We need to program the hardware with the amount of scratch memory that
 386   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
 387   // scratch memory used per thread.
 388   ProgInfo.ScratchBlocks =
 389     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
 390                        1 << ScratchAlignShift) >> ScratchAlignShift;
 391
 392   ProgInfo.ComputePGMRSrc1 =
 393       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
 394       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
 395       S_00B848_PRIORITY(ProgInfo.Priority) |
 396       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
 397       S_00B848_PRIV(ProgInfo.Priv) |
 398       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
 399       S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
 400       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
 401
 402   ProgInfo.ComputePGMRSrc2 =
 403       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
 404       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
 405       S_00B84C_TGID_X_EN(1) |
 406       S_00B84C_TGID_Y_EN(1) |
 407       S_00B84C_TGID_Z_EN(1) |
 408       S_00B84C_TG_SIZE_EN(1) |
 409       S_00B84C_TIDIG_COMP_CNT(2) |
 410       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
 411 }
 412
 413 static unsigned getRsrcReg(unsigned ShaderType) {
 414   switch (ShaderType) {
 415   default: // Fall through
 416   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
 417   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
 418   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
 419   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
 420   }
 421 }
 422
 423 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
 424                                          const SIProgramInfo &KernelInfo) {
 425   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 426   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 427   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
 428
 429   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 430     OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
 431
 432     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
 433
 434     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 435     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
 436
 437     OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
 438     OutStreamer.EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 439
 440     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
 441     // 0" comment but I don't see a corresponding field in the register spec.
 442   } else {
 443     OutStreamer.EmitIntValue(RsrcReg, 4);
 444     OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
 445                              S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
 446     if (STM.isVGPRSpillingEnabled(MFI)) {
 447       OutStreamer.EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
 448       OutStreamer.EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 449     }
 450   }
 451
 452   if (MFI->getShaderType() == ShaderType::PIXEL) {
 453     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 454     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
 455     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 456     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 457   }
 458 }
 459
 460 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
 461                                         const SIProgramInfo &KernelInfo) const {
 462   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 463   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 464   amd_kernel_code_t header;
 465
 466   memset(&header, 0, sizeof(header));
 467
 468   header.amd_code_version_major = AMD_CODE_VERSION_MAJOR;
 469   header.amd_code_version_minor = AMD_CODE_VERSION_MINOR;
 470
 471   header.struct_byte_size = sizeof(amd_kernel_code_t);
 472
 473   header.target_chip = STM.getAmdKernelCodeChipID();
 474
 475   header.kernel_code_entry_byte_offset = (1ULL << MF.getAlignment());
 476
 477   header.compute_pgm_resource_registers =
 478       KernelInfo.ComputePGMRSrc1 |
 479       (KernelInfo.ComputePGMRSrc2 << 32);
 480
 481   // Code Properties:
 482   header.code_properties = AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
 483                            AMD_CODE_PROPERTY_IS_PTR64;
 484
 485   if (KernelInfo.FlatUsed)
 486     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
 487
 488   if (KernelInfo.ScratchBlocks)
 489     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE;
 490
 491   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
 492   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
 493
 494   // MFI->ABIArgOffset is the number of bytes for the kernel arguments
 495   // plus 36.  36 is the number of bytes reserved at the begining of the
 496   // input buffer to store work-group size information.
 497   // FIXME: We should be adding the size of the implicit arguments
 498   // to this value.
 499   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
 500
 501   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
 502   header.workitem_vgpr_count = KernelInfo.NumVGPR;
 503
 504   // FIXME: What values do I put for these alignments
 505   header.kernarg_segment_alignment = 0;
 506   header.group_segment_alignment = 0;
 507   header.private_segment_alignment = 0;
 508
 509   header.code_type = 1; // HSA_EXT_CODE_KERNEL
 510
 511   header.wavefront_size = STM.getWavefrontSize();
 512
 513   const MCSectionELF *VersionSection = OutContext.getELFSection(".hsa.version",
 514       ELF::SHT_PROGBITS, 0, SectionKind::getReadOnly());
 515   OutStreamer.SwitchSection(VersionSection);
 516   OutStreamer.EmitBytes(Twine("HSA Code Unit:" +
 517                         Twine(header.hsail_version_major) + "." +
 518                         Twine(header.hsail_version_minor) + ":" +
 519                         "AMD:" +
 520                         Twine(header.amd_code_version_major) + "." +
 521                         Twine(header.amd_code_version_minor) +  ":" +
 522                         "GFX8.1:0").str());
 523
 524   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 525
 526   if (isVerbose()) {
 527     OutStreamer.emitRawComment("amd_code_version_major = " +
 528                                Twine(header.amd_code_version_major), false);
 529     OutStreamer.emitRawComment("amd_code_version_minor = " +
 530                                Twine(header.amd_code_version_minor), false);
 531     OutStreamer.emitRawComment("struct_byte_size = " +
 532                                Twine(header.struct_byte_size), false);
 533     OutStreamer.emitRawComment("target_chip = " +
 534                                Twine(header.target_chip), false);
 535     OutStreamer.emitRawComment(" compute_pgm_rsrc1: " +
 536                                Twine::utohexstr(KernelInfo.ComputePGMRSrc1), false);
 537     OutStreamer.emitRawComment(" compute_pgm_rsrc2: " +
 538                                Twine::utohexstr(KernelInfo.ComputePGMRSrc2), false);
 539     OutStreamer.emitRawComment("enable_sgpr_private_segment_buffer = " +
 540       Twine((bool)(header.code_properties &
 541                    AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE)), false);
 542     OutStreamer.emitRawComment("enable_sgpr_kernarg_segment_ptr = " +
 543       Twine((bool)(header.code_properties &
 544                    AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)), false);
 545     OutStreamer.emitRawComment("private_element_size = 2 ", false);
 546     OutStreamer.emitRawComment("is_ptr64 = " +
 547         Twine((bool)(header.code_properties & AMD_CODE_PROPERTY_IS_PTR64)), false);
 548     OutStreamer.emitRawComment("workitem_private_segment_byte_size = " +
 549                                Twine(header.workitem_private_segment_byte_size),
 550                                false);
 551     OutStreamer.emitRawComment("workgroup_group_segment_byte_size = " +
 552                                Twine(header.workgroup_group_segment_byte_size),
 553                                false);
 554     OutStreamer.emitRawComment("gds_segment_byte_size = " +
 555                                Twine(header.gds_segment_byte_size), false);
 556     OutStreamer.emitRawComment("kernarg_segment_byte_size = " +
 557                                Twine(header.kernarg_segment_byte_size), false);
 558     OutStreamer.emitRawComment("wavefront_sgpr_count = " +
 559                                Twine(header.wavefront_sgpr_count), false);
 560     OutStreamer.emitRawComment("workitem_vgpr_count = " +
 561                                Twine(header.workitem_vgpr_count), false);
 562     OutStreamer.emitRawComment("code_type = " + Twine(header.code_type), false);
 563     OutStreamer.emitRawComment("wavefront_size = " +
 564                                Twine((int)header.wavefront_size), false);
 565     OutStreamer.emitRawComment("optimization_level = " +
 566                                Twine(header.optimization_level), false);
 567     OutStreamer.emitRawComment("hsail_profile = " +
 568                                Twine(header.hsail_profile), false);
 569     OutStreamer.emitRawComment("hsail_machine_model = " +
 570                                Twine(header.hsail_machine_model), false);
 571     OutStreamer.emitRawComment("hsail_version_major = " +
 572                                Twine(header.hsail_version_major), false);
 573     OutStreamer.emitRawComment("hsail_version_minor = " +
 574                                Twine(header.hsail_version_minor), false);
 575   }
 576
 577   OutStreamer.EmitBytes(StringRef((char*)&header, sizeof(header)));
 578 }