lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19 #include "AMDGPUAsmPrinter.h"
  20 #include "AMDGPU.h"
  21 #include "AMDKernelCodeT.h"
  22 #include "AMDGPUSubtarget.h"
  23 #include "R600Defines.h"
  24 #include "R600MachineFunctionInfo.h"
  25 #include "R600RegisterInfo.h"
  26 #include "SIDefines.h"
  27 #include "SIMachineFunctionInfo.h"
  28 #include "SIRegisterInfo.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/MC/MCContext.h"
  31 #include "llvm/MC/MCSectionELF.h"
  32 #include "llvm/MC/MCStreamer.h"
  33 #include "llvm/Support/ELF.h"
  34 #include "llvm/Support/MathExtras.h"
  35 #include "llvm/Support/TargetRegistry.h"
  36 #include "llvm/Target/TargetLoweringObjectFile.h"
  37
  38 using namespace llvm;
  39
  40 // TODO: This should get the default rounding mode from the kernel. We just set
  41 // the default here, but this could change if the OpenCL rounding mode pragmas
  42 // are used.
  43 //
  44 // The denormal mode here should match what is reported by the OpenCL runtime
  45 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
  46 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
  47 //
  48 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
  49 // precision, and leaves single precision to flush all and does not report
  50 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
  51 // CL_FP_DENORM for both.
  52 //
  53 // FIXME: It seems some instructions do not support single precision denormals
  54 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
  55 // and sin_f32, cos_f32 on most parts).
  56
  57 // We want to use these instructions, and using fp32 denormals also causes
  58 // instructions to run at the double precision rate for the device so it's
  59 // probably best to just report no single precision denormals.
  60 static uint32_t getFPMode(const MachineFunction &F) {
  61   const AMDGPUSubtarget& ST = F.getTarget().getSubtarget<AMDGPUSubtarget>();
  62   // TODO: Is there any real use for the flush in only / flush out only modes?
  63
  64   uint32_t FP32Denormals =
  65     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  66
  67   uint32_t FP64Denormals =
  68     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  69
  70   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
  71          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
  72          FP_DENORM_MODE_SP(FP32Denormals) |
  73          FP_DENORM_MODE_DP(FP64Denormals);
  74 }
  75
  76 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
  77                                               MCStreamer &Streamer) {
  78   return new AMDGPUAsmPrinter(tm, Streamer);
  79 }
  80
  81 extern "C" void LLVMInitializeR600AsmPrinter() {
  82   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  83 }
  84
  85 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
  86     : AsmPrinter(TM, Streamer) {
  87   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
  88 }
  89
  90 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
  91
  92   // This label is used to mark the end of the .text section.
  93   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
  94   OutStreamer.SwitchSection(TLOF.getTextSection());
  95   MCSymbol *EndOfTextLabel =
  96       OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
  97   OutStreamer.EmitLabel(EndOfTextLabel);
  98 }
  99
 100 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 101
 102   // The starting address of all shader programs must be 256 bytes aligned.
 103   MF.setAlignment(8);
 104
 105   SetupMachineFunction(MF);
 106
 107   EmitFunctionHeader();
 108
 109   MCContext &Context = getObjFileLowering().getContext();
 110   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
 111                                               ELF::SHT_PROGBITS, 0,
 112                                               SectionKind::getReadOnly());
 113   OutStreamer.SwitchSection(ConfigSection);
 114
 115   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 116   SIProgramInfo KernelInfo;
 117   if (STM.isAmdHsaOS()) {
 118     OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 119     getSIProgramInfo(KernelInfo, MF);
 120     EmitAmdKernelCodeT(MF, KernelInfo);
 121     OutStreamer.EmitCodeAlignment(2 << (MF.getAlignment() - 1));
 122   } else if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 123     getSIProgramInfo(KernelInfo, MF);
 124     EmitProgramInfoSI(MF, KernelInfo);
 125   } else {
 126     EmitProgramInfoR600(MF);
 127   }
 128
 129   DisasmLines.clear();
 130   HexLines.clear();
 131   DisasmLineMaxLen = 0;
 132
 133   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 134   EmitFunctionBody();
 135
 136   if (isVerbose()) {
 137     const MCSectionELF *CommentSection
 138       = Context.getELFSection(".AMDGPU.csdata",
 139                               ELF::SHT_PROGBITS, 0,
 140                               SectionKind::getReadOnly());
 141     OutStreamer.SwitchSection(CommentSection);
 142
 143     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 144       OutStreamer.emitRawComment(" Kernel info:", false);
 145       OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
 146                                  false);
 147       OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
 148                                  false);
 149       OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
 150                                  false);
 151       OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
 152                                  false);
 153       OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
 154                                  false);
 155       OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
 156                                  false);
 157     } else {
 158       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 159       OutStreamer.emitRawComment(
 160         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 161     }
 162   }
 163
 164   if (STM.dumpCode()) {
 165 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 166     MF.dump();
 167 #endif
 168
 169     if (DisasmEnabled) {
 170       OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
 171                                                   ELF::SHT_NOTE, 0,
 172                                                   SectionKind::getReadOnly()));
 173
 174       for (size_t i = 0; i < DisasmLines.size(); ++i) {
 175         std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 176         Comment += " ; " + HexLines[i] + "\n";
 177
 178         OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 179         OutStreamer.EmitBytes(StringRef(Comment));
 180       }
 181     }
 182   }
 183
 184   return false;
 185 }
 186
 187 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
 188   unsigned MaxGPR = 0;
 189   bool killPixel = false;
 190   const R600RegisterInfo *RI = static_cast<const R600RegisterInfo *>(
 191       TM.getSubtargetImpl()->getRegisterInfo());
 192   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 193   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 194
 195   for (const MachineBasicBlock &MBB : MF) {
 196     for (const MachineInstr &MI : MBB) {
 197       if (MI.getOpcode() == AMDGPU::KILLGT)
 198         killPixel = true;
 199       unsigned numOperands = MI.getNumOperands();
 200       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 201         const MachineOperand &MO = MI.getOperand(op_idx);
 202         if (!MO.isReg())
 203           continue;
 204         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 205
 206         // Register with value > 127 aren't GPR
 207         if (HWReg > 127)
 208           continue;
 209         MaxGPR = std::max(MaxGPR, HWReg);
 210       }
 211     }
 212   }
 213
 214   unsigned RsrcReg;
 215   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 216     // Evergreen / Northern Islands
 217     switch (MFI->getShaderType()) {
 218     default: // Fall through
 219     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 220     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 221     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 222     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 223     }
 224   } else {
 225     // R600 / R700
 226     switch (MFI->getShaderType()) {
 227     default: // Fall through
 228     case ShaderType::GEOMETRY: // Fall through
 229     case ShaderType::COMPUTE:  // Fall through
 230     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 231     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 232     }
 233   }
 234
 235   OutStreamer.EmitIntValue(RsrcReg, 4);
 236   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 237                            S_STACK_SIZE(MFI->StackSize), 4);
 238   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 239   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 240
 241   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 242     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 243     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 244   }
 245 }
 246
 247 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 248                                         const MachineFunction &MF) const {
 249   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 250   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 251   uint64_t CodeSize = 0;
 252   unsigned MaxSGPR = 0;
 253   unsigned MaxVGPR = 0;
 254   bool VCCUsed = false;
 255   bool FlatUsed = false;
 256   const SIRegisterInfo *RI = static_cast<const SIRegisterInfo *>(
 257       TM.getSubtargetImpl()->getRegisterInfo());
 258
 259   for (const MachineBasicBlock &MBB : MF) {
 260     for (const MachineInstr &MI : MBB) {
 261       // TODO: CodeSize should account for multiple functions.
 262       CodeSize += MI.getDesc().Size;
 263
 264       unsigned numOperands = MI.getNumOperands();
 265       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 266         const MachineOperand &MO = MI.getOperand(op_idx);
 267         unsigned width = 0;
 268         bool isSGPR = false;
 269
 270         if (!MO.isReg()) {
 271           continue;
 272         }
 273         unsigned reg = MO.getReg();
 274         if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
 275             reg == AMDGPU::VCC_HI) {
 276           VCCUsed = true;
 277           continue;
 278         } else if (reg == AMDGPU::FLAT_SCR ||
 279                    reg == AMDGPU::FLAT_SCR_LO ||
 280                    reg == AMDGPU::FLAT_SCR_HI) {
 281           FlatUsed = true;
 282           continue;
 283         }
 284
 285         switch (reg) {
 286         default: break;
 287         case AMDGPU::SCC:
 288         case AMDGPU::EXEC:
 289         case AMDGPU::M0:
 290           continue;
 291         }
 292
 293         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 294           isSGPR = true;
 295           width = 1;
 296         } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
 297           isSGPR = false;
 298           width = 1;
 299         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 300           isSGPR = true;
 301           width = 2;
 302         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 303           isSGPR = false;
 304           width = 2;
 305         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 306           isSGPR = false;
 307           width = 3;
 308         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 309           isSGPR = true;
 310           width = 4;
 311         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 312           isSGPR = false;
 313           width = 4;
 314         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 315           isSGPR = true;
 316           width = 8;
 317         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 318           isSGPR = false;
 319           width = 8;
 320         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 321           isSGPR = true;
 322           width = 16;
 323         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 324           isSGPR = false;
 325           width = 16;
 326         } else {
 327           llvm_unreachable("Unknown register class");
 328         }
 329         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 330         unsigned maxUsed = hwReg + width - 1;
 331         if (isSGPR) {
 332           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 333         } else {
 334           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 335         }
 336       }
 337     }
 338   }
 339
 340   if (VCCUsed)
 341     MaxSGPR += 2;
 342
 343   if (FlatUsed)
 344     MaxSGPR += 2;
 345
 346   // We found the maximum register index. They start at 0, so add one to get the
 347   // number of registers.
 348   ProgInfo.NumVGPR = MaxVGPR + 1;
 349   ProgInfo.NumSGPR = MaxSGPR + 1;
 350
 351   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
 352   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
 353   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
 354   // register.
 355   ProgInfo.FloatMode = getFPMode(MF);
 356
 357   // XXX: Not quite sure what this does, but sc seems to unset this.
 358   ProgInfo.IEEEMode = 0;
 359
 360   // Do not clamp NAN to 0.
 361   ProgInfo.DX10Clamp = 0;
 362
 363   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
 364   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
 365
 366   ProgInfo.FlatUsed = FlatUsed;
 367   ProgInfo.VCCUsed = VCCUsed;
 368   ProgInfo.CodeLen = CodeSize;
 369
 370   unsigned LDSAlignShift;
 371   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 372     // LDS is allocated in 64 dword blocks.
 373     LDSAlignShift = 8;
 374   } else {
 375     // LDS is allocated in 128 dword blocks.
 376     LDSAlignShift = 9;
 377   }
 378
 379   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
 380                           MFI->getMaximumWorkGroupSize(MF);
 381
 382   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
 383   ProgInfo.LDSBlocks =
 384      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 385
 386   // Scratch is allocated in 256 dword blocks.
 387   unsigned ScratchAlignShift = 10;
 388   // We need to program the hardware with the amount of scratch memory that
 389   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
 390   // scratch memory used per thread.
 391   ProgInfo.ScratchBlocks =
 392     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
 393                        1 << ScratchAlignShift) >> ScratchAlignShift;
 394
 395   ProgInfo.ComputePGMRSrc1 =
 396       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
 397       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
 398       S_00B848_PRIORITY(ProgInfo.Priority) |
 399       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
 400       S_00B848_PRIV(ProgInfo.Priv) |
 401       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
 402       S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
 403       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
 404
 405   ProgInfo.ComputePGMRSrc2 =
 406       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
 407       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
 408       S_00B84C_TGID_X_EN(1) |
 409       S_00B84C_TGID_Y_EN(1) |
 410       S_00B84C_TGID_Z_EN(1) |
 411       S_00B84C_TG_SIZE_EN(1) |
 412       S_00B84C_TIDIG_COMP_CNT(2) |
 413       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
 414 }
 415
 416 static unsigned getRsrcReg(unsigned ShaderType) {
 417   switch (ShaderType) {
 418   default: // Fall through
 419   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
 420   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
 421   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
 422   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
 423   }
 424 }
 425
 426 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
 427                                          const SIProgramInfo &KernelInfo) {
 428   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 429   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
 430
 431   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 432     OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
 433
 434     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
 435
 436     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 437     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
 438
 439     OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
 440     OutStreamer.EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 441
 442     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
 443     // 0" comment but I don't see a corresponding field in the register spec.
 444   } else {
 445     OutStreamer.EmitIntValue(RsrcReg, 4);
 446     OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
 447                              S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
 448   }
 449
 450   if (MFI->getShaderType() == ShaderType::PIXEL) {
 451     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 452     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
 453     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 454     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 455   }
 456 }
 457
 458 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
 459                                         const SIProgramInfo &KernelInfo) const {
 460   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 461   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 462   amd_kernel_code_t header;
 463
 464   memset(&header, 0, sizeof(header));
 465
 466   header.amd_code_version_major = AMD_CODE_VERSION_MAJOR;
 467   header.amd_code_version_minor = AMD_CODE_VERSION_MINOR;
 468
 469   header.struct_byte_size = sizeof(amd_kernel_code_t);
 470
 471   header.target_chip = STM.getAmdKernelCodeChipID();
 472
 473   header.kernel_code_entry_byte_offset = (1 << MF.getAlignment());
 474
 475   header.compute_pgm_resource_registers =
 476       KernelInfo.ComputePGMRSrc1 |
 477       (KernelInfo.ComputePGMRSrc2 << 32);
 478
 479   // Code Properties:
 480   header.code_properties = AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
 481                            AMD_CODE_PROPERTY_IS_PTR64;
 482
 483   if (KernelInfo.FlatUsed)
 484     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
 485
 486   if (KernelInfo.ScratchBlocks)
 487     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE;
 488
 489   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
 490   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
 491
 492   // MFI->ABIArgOffset is the number of bytes for the kernel arguments
 493   // plus 36.  36 is the number of bytes reserved at the begining of the
 494   // input buffer to store work-group size information.
 495   // FIXME: We should be adding the size of the implicit arguments
 496   // to this value.
 497   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
 498
 499   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
 500   header.workitem_vgpr_count = KernelInfo.NumVGPR;
 501
 502   // FIXME: What values do I put for these alignments
 503   header.kernarg_segment_alignment = 0;
 504   header.group_segment_alignment = 0;
 505   header.private_segment_alignment = 0;
 506
 507   header.code_type = 1; // HSA_EXT_CODE_KERNEL
 508
 509   header.wavefront_size = STM.getWavefrontSize();
 510
 511   if (isVerbose()) {
 512     OutStreamer.emitRawComment("amd_code_version_major = " +
 513                                Twine(header.amd_code_version_major), false);
 514     OutStreamer.emitRawComment("amd_code_version_minor = " +
 515                                Twine(header.amd_code_version_minor), false);
 516     OutStreamer.emitRawComment("struct_byte_size = " +
 517                                Twine(header.struct_byte_size), false);
 518     OutStreamer.emitRawComment("target_chip = " +
 519                                Twine(header.target_chip), false);
 520     OutStreamer.emitRawComment(" compute_pgm_rsrc1: " +
 521                                Twine::utohexstr(KernelInfo.ComputePGMRSrc1), false);
 522     OutStreamer.emitRawComment(" compute_pgm_rsrc2: " +
 523                                Twine::utohexstr(KernelInfo.ComputePGMRSrc2), false);
 524     OutStreamer.emitRawComment("enable_sgpr_private_segment_buffer = " +
 525       Twine((bool)(header.code_properties &
 526                    AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE)), false);
 527     OutStreamer.emitRawComment("enable_sgpr_kernarg_segment_ptr = " +
 528       Twine((bool)(header.code_properties &
 529                    AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)), false);
 530     OutStreamer.emitRawComment("private_element_size = 2 ", false);
 531     OutStreamer.emitRawComment("is_ptr64 = " +
 532         Twine((bool)(header.code_properties & AMD_CODE_PROPERTY_IS_PTR64)), false);
 533     OutStreamer.emitRawComment("workitem_private_segment_byte_size = " +
 534                                Twine(header.workitem_private_segment_byte_size),
 535                                false);
 536     OutStreamer.emitRawComment("workgroup_group_segment_byte_size = " +
 537                                Twine(header.workgroup_group_segment_byte_size),
 538                                false);
 539     OutStreamer.emitRawComment("gds_segment_byte_size = " +
 540                                Twine(header.gds_segment_byte_size), false);
 541     OutStreamer.emitRawComment("kernarg_segment_byte_size = " +
 542                                Twine(header.kernarg_segment_byte_size), false);
 543     OutStreamer.emitRawComment("wavefront_sgpr_count = " +
 544                                Twine(header.wavefront_sgpr_count), false);
 545     OutStreamer.emitRawComment("workitem_vgpr_count = " +
 546                                Twine(header.workitem_vgpr_count), false);
 547     OutStreamer.emitRawComment("code_type = " + Twine(header.code_type), false);
 548     OutStreamer.emitRawComment("wavefront_size = " +
 549                                Twine((int)header.wavefront_size), false);
 550     OutStreamer.emitRawComment("optimization_level = " +
 551                                Twine(header.optimization_level), false);
 552     OutStreamer.emitRawComment("hsail_profile = " +
 553                                Twine(header.hsail_profile), false);
 554     OutStreamer.emitRawComment("hsail_machine_model = " +
 555                                Twine(header.hsail_machine_model), false);
 556     OutStreamer.emitRawComment("hsail_version_major = " +
 557                                Twine(header.hsail_version_major), false);
 558     OutStreamer.emitRawComment("hsail_version_minor = " +
 559                                Twine(header.hsail_version_minor), false);
 560   }
 561
 562   OutStreamer.EmitBytes(StringRef((char*)&header, sizeof(header)));
 563 }