lib/Target/R600/AMDGPU.td

   1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // Subtarget Features
  14 //===----------------------------------------------------------------------===//
  15
  16 // Debugging Features
  17
  18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
  19         "DumpCode",
  20         "true",
  21         "Dump MachineInstrs in the CodeEmitter">;
  22
  23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
  24         "EnableIRStructurizer",
  25         "false",
  26         "Disable IR Structurizer">;
  27
  28 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
  29         "EnablePromoteAlloca",
  30         "true",
  31         "Enable promote alloca pass">;
  32
  33 // Target features
  34
  35 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
  36         "EnableIfCvt",
  37         "false",
  38         "Disable the if conversion pass">;
  39
  40 def FeatureFP64 : SubtargetFeature<"fp64",
  41         "FP64",
  42         "true",
  43         "Enable double precision operations">;
  44
  45 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
  46         "FP64Denormals",
  47         "true",
  48         "Enable double precision denormal handling",
  49         [FeatureFP64]>;
  50
  51 // Some instructions do not support denormals despite this flag. Using
  52 // fp32 denormals also causes instructions to run at the double
  53 // precision rate for the device.
  54 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
  55         "FP32Denormals",
  56         "true",
  57         "Enable single precision denormal handling">;
  58
  59 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
  60         "Is64bit",
  61         "true",
  62         "Specify if 64-bit addressing should be used">;
  63
  64 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
  65         "R600ALUInst",
  66         "false",
  67         "Older version of ALU instructions encoding">;
  68
  69 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
  70         "HasVertexCache",
  71         "true",
  72         "Specify use of dedicated vertex cache">;
  73
  74 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
  75         "CaymanISA",
  76         "true",
  77         "Use Cayman ISA">;
  78
  79 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
  80         "CFALUBug",
  81         "true",
  82         "GPU has CF_ALU bug">;
  83
  84 // XXX - This should probably be removed once enabled by default
  85 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
  86         "EnableLoadStoreOpt",
  87         "true",
  88         "Enable SI load/store optimizer pass">;
  89
  90 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  91         "FlatAddressSpace",
  92         "true",
  93         "Support flat address space">;
  94
  95 class SubtargetFeatureFetchLimit <string Value> :
  96                           SubtargetFeature <"fetch"#Value,
  97         "TexVTXClauseSize",
  98         Value,
  99         "Limit the maximum number of fetches in a clause to "#Value>;
 100
 101 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
 102 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
 103
 104 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
 105         "wavefrontsize"#Value,
 106         "WavefrontSize",
 107         !cast<string>(Value),
 108         "The number of threads per wavefront">;
 109
 110 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
 111 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
 112 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
 113
 114 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
 115         "localmemorysize"#Value,
 116         "LocalMemorySize",
 117         !cast<string>(Value),
 118         "The size of local memory in bytes">;
 119
 120 class SubtargetFeatureGeneration <string Value,
 121                                   list<SubtargetFeature> Implies> :
 122         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
 123                           Value#" GPU generation", Implies>;
 124
 125 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
 126 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
 127 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
 128
 129 def FeatureR600 : SubtargetFeatureGeneration<"R600",
 130         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
 131
 132 def FeatureR700 : SubtargetFeatureGeneration<"R700",
 133         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
 134
 135 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
 136         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
 137
 138 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
 139         [FeatureFetchLimit16, FeatureWavefrontSize64,
 140          FeatureLocalMemorySize32768]
 141 >;
 142
 143 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 144         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
 145          FeatureWavefrontSize64]>;
 146
 147 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
 148         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 149          FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
 150 //===----------------------------------------------------------------------===//
 151
 152 def AMDGPUInstrInfo : InstrInfo {
 153   let guessInstructionProperties = 1;
 154 }
 155
 156 def AMDGPU : Target {
 157   // Pull in Instruction Info:
 158   let InstructionSet = AMDGPUInstrInfo;
 159 }
 160
 161 // Dummy Instruction itineraries for pseudo instructions
 162 def ALU_NULL : FuncUnit;
 163 def NullALU : InstrItinClass;
 164
 165 //===----------------------------------------------------------------------===//
 166 // Predicate helper class
 167 //===----------------------------------------------------------------------===//
 168
 169 class PredicateControl {
 170   Predicate SubtargetPredicate;
 171   list<Predicate> OtherPredicates = [];
 172   list<Predicate> Predicates = !listconcat([SubtargetPredicate],
 173                                             OtherPredicates);
 174 }
 175
 176 // Include AMDGPU TD files
 177 include "R600Schedule.td"
 178 include "SISchedule.td"
 179 include "Processors.td"
 180 include "AMDGPUInstrInfo.td"
 181 include "AMDGPUIntrinsics.td"
 182 include "AMDGPURegisterInfo.td"
 183 include "AMDGPUInstructions.td"
 184 include "AMDGPUCallingConv.td"