lib/Target/R600/AMDGPU.td

   1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // Subtarget Features
  14 //===----------------------------------------------------------------------===//
  15
  16 // Debugging Features
  17
  18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
  19         "DumpCode",
  20         "true",
  21         "Dump MachineInstrs in the CodeEmitter">;
  22
  23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
  24         "EnableIRStructurizer",
  25         "false",
  26         "Disable IR Structurizer">;
  27
  28 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
  29         "EnablePromoteAlloca",
  30         "true",
  31         "Enable promote alloca pass">;
  32
  33 // Target features
  34
  35 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
  36         "EnableIfCvt",
  37         "false",
  38         "Disable the if conversion pass">;
  39
  40 def FeatureFP64 : SubtargetFeature<"fp64",
  41         "FP64",
  42         "true",
  43         "Enable double precision operations">;
  44
  45 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
  46         "FP64Denormals",
  47         "true",
  48         "Enable double precision denormal handling",
  49         [FeatureFP64]>;
  50
  51 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  52         "FastFMAF32",
  53         "true",
  54         "Assuming f32 fma is at least as fast as mul + add",
  55         []>;
  56
  57 // Some instructions do not support denormals despite this flag. Using
  58 // fp32 denormals also causes instructions to run at the double
  59 // precision rate for the device.
  60 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
  61         "FP32Denormals",
  62         "true",
  63         "Enable single precision denormal handling">;
  64
  65 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
  66         "Is64bit",
  67         "true",
  68         "Specify if 64-bit addressing should be used">;
  69
  70 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
  71         "R600ALUInst",
  72         "false",
  73         "Older version of ALU instructions encoding">;
  74
  75 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
  76         "HasVertexCache",
  77         "true",
  78         "Specify use of dedicated vertex cache">;
  79
  80 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
  81         "CaymanISA",
  82         "true",
  83         "Use Cayman ISA">;
  84
  85 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
  86         "CFALUBug",
  87         "true",
  88         "GPU has CF_ALU bug">;
  89
  90 // XXX - This should probably be removed once enabled by default
  91 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
  92         "EnableLoadStoreOpt",
  93         "true",
  94         "Enable SI load/store optimizer pass">;
  95
  96 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  97         "FlatAddressSpace",
  98         "true",
  99         "Support flat address space">;
 100
 101 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
 102         "EnableVGPRSpilling",
 103         "true",
 104         "Enable spilling of VGPRs to scratch memory">;
 105
 106 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 107         "SGPRInitBug",
 108         "true",
 109         "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
 110
 111 class SubtargetFeatureFetchLimit <string Value> :
 112                           SubtargetFeature <"fetch"#Value,
 113         "TexVTXClauseSize",
 114         Value,
 115         "Limit the maximum number of fetches in a clause to "#Value>;
 116
 117 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
 118 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
 119
 120 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
 121         "wavefrontsize"#Value,
 122         "WavefrontSize",
 123         !cast<string>(Value),
 124         "The number of threads per wavefront">;
 125
 126 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
 127 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
 128 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
 129
 130 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
 131         "localmemorysize"#Value,
 132         "LocalMemorySize",
 133         !cast<string>(Value),
 134         "The size of local memory in bytes">;
 135
 136 def FeatureGCN : SubtargetFeature<"gcn",
 137         "IsGCN",
 138         "true",
 139         "GCN or newer GPU">;
 140
 141 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
 142         "GCN1Encoding",
 143         "true",
 144         "Encoding format for SI and CI">;
 145
 146 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 147         "GCN3Encoding",
 148         "true",
 149         "Encoding format for VI">;
 150 class SubtargetFeatureGeneration <string Value,
 151                                   list<SubtargetFeature> Implies> :
 152         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
 153                           Value#" GPU generation", Implies>;
 154
 155 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
 156 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
 157 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
 158
 159 def FeatureR600 : SubtargetFeatureGeneration<"R600",
 160         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
 161
 162 def FeatureR700 : SubtargetFeatureGeneration<"R700",
 163         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
 164
 165 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
 166         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
 167
 168 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
 169         [FeatureFetchLimit16, FeatureWavefrontSize64,
 170          FeatureLocalMemorySize32768]
 171 >;
 172
 173 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 174         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
 175          FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding]>;
 176
 177 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
 178         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 179          FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
 180          FeatureGCN1Encoding]>;
 181
 182 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 183         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 184          FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 185          FeatureGCN3Encoding]>;
 186
 187 //===----------------------------------------------------------------------===//
 188
 189 def AMDGPUInstrInfo : InstrInfo {
 190   let guessInstructionProperties = 1;
 191   let noNamedPositionallyEncodedOperands = 1;
 192 }
 193
 194 def AMDGPUAsmParser : AsmParser {
 195   // Some of the R600 registers have the same name, so this crashes.
 196   // For example T0_XYZW and T0_XY both have the asm name T0.
 197   let ShouldEmitMatchRegisterName = 0;
 198 }
 199
 200 def AMDGPU : Target {
 201   // Pull in Instruction Info:
 202   let InstructionSet = AMDGPUInstrInfo;
 203   let AssemblyParsers = [AMDGPUAsmParser];
 204 }
 205
 206 // Dummy Instruction itineraries for pseudo instructions
 207 def ALU_NULL : FuncUnit;
 208 def NullALU : InstrItinClass;
 209
 210 //===----------------------------------------------------------------------===//
 211 // Predicate helper class
 212 //===----------------------------------------------------------------------===//
 213
 214 class PredicateControl {
 215   Predicate SubtargetPredicate;
 216   list<Predicate> AssemblerPredicates = [];
 217   list<Predicate> OtherPredicates = [];
 218   list<Predicate> Predicates = !listconcat([SubtargetPredicate],
 219                                             AssemblerPredicates,
 220                                             OtherPredicates);
 221 }
 222
 223 // Include AMDGPU TD files
 224 include "R600Schedule.td"
 225 include "SISchedule.td"
 226 include "Processors.td"
 227 include "AMDGPUInstrInfo.td"
 228 include "AMDGPUIntrinsics.td"
 229 include "AMDGPURegisterInfo.td"
 230 include "AMDGPUInstructions.td"
 231 include "AMDGPUCallingConv.td"