1 //===- PowerPCRegisterInfo.cpp - PowerPC Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCRegisterInfo.h"
17 #include "PowerPCInstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "Support/CommandLine.h"
28 #include "Support/Debug.h"
29 #include "Support/STLExtras.h"
34 // Switch toggling compilation for AIX
35 extern cl::opt<bool> AIX;
38 PowerPCRegisterInfo::PowerPCRegisterInfo(bool is64b)
39 : PowerPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
41 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
42 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
43 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
44 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
45 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
46 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
47 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
48 ImmToIdxMap[PPC::ADDI] = PPC::ADD;
51 static unsigned getIdx(const TargetRegisterClass *RC) {
52 if (RC == PowerPC::GPRCRegisterClass) {
53 switch (RC->getSize()) {
54 default: assert(0 && "Invalid data size!");
60 } else if (RC == PowerPC::FPRCRegisterClass) {
61 switch (RC->getSize()) {
62 default: assert(0 && "Invalid data size!");
67 std::cerr << "Invalid register class to getIdx()!\n";
72 PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MI,
74 unsigned SrcReg, int FrameIdx) const {
75 const TargetRegisterClass *RC = getRegClass(SrcReg);
76 static const unsigned Opcode[] = {
77 PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
80 unsigned OC = Opcode[getIdx(RC)];
81 if (SrcReg == PPC::LR) {
82 BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
83 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
84 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
86 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
87 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
92 PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator MI,
94 unsigned DestReg, int FrameIdx) const{
95 static const unsigned Opcode[] = {
96 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
98 const TargetRegisterClass *RC = getRegClass(DestReg);
99 unsigned OC = Opcode[getIdx(RC)];
100 if (DestReg == PPC::LR) {
101 BuildMI(MBB, MI, PPC::IMPLCICIT_DEF, 0, PPC::R0);
102 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
103 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
105 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
106 addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
110 void PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator MI,
112 unsigned DestReg, unsigned SrcReg,
113 const TargetRegisterClass *RC) const {
116 if (RC == PowerPC::GPRCRegisterClass) {
117 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
118 } else if (RC == PowerPC::FPRCRegisterClass) {
119 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
121 std::cerr << "Attempt to copy register that is not GPR or FPR";
126 //===----------------------------------------------------------------------===//
127 // Stack Frame Processing methods
128 //===----------------------------------------------------------------------===//
130 // hasFP - Return true if the specified function should have a dedicated frame
131 // pointer register. This is true if the function has variable sized allocas or
132 // if frame pointer elimination is disabled.
134 static bool hasFP(MachineFunction &MF) {
135 MachineFrameInfo *MFI = MF.getFrameInfo();
136 return MFI->hasVarSizedObjects();
139 void PowerPCRegisterInfo::
140 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
141 MachineBasicBlock::iterator I) const {
143 // If we have a frame pointer, convert as follows:
144 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
145 // ADJCALLSTACKUP -> addi, r1, r1, amount
146 MachineInstr *Old = I;
147 unsigned Amount = Old->getOperand(0).getImmedValue();
149 // We need to keep the stack aligned properly. To do this, we round the
150 // amount of space needed for the outgoing arguments up to the next
151 // alignment boundary.
152 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
153 Amount = (Amount+Align-1)/Align*Align;
155 // Replace the pseudo instruction with a new instruction...
156 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
157 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
160 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
161 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
170 PowerPCRegisterInfo::
171 eliminateFrameIndex(MachineBasicBlock::iterator II) const {
173 MachineInstr &MI = *II;
174 MachineBasicBlock &MBB = *MI.getParent();
175 MachineFunction &MF = *MBB.getParent();
177 while (!MI.getOperand(i).isFrameIndex()) {
179 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
182 int FrameIndex = MI.getOperand(i).getFrameIndex();
184 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
185 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
187 // Take into account whether it's an add or mem instruction
188 unsigned OffIdx = (i == 2) ? 1 : 2;
190 // Now add the frame object offset to the offset from r1.
191 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
192 MI.getOperand(OffIdx).getImmedValue();
194 // If we're not using a Frame Pointer that has been set to the value of the
195 // SP before having the stack size subtracted from it, then add the stack size
196 // to Offset to get the correct offset.
197 Offset += MF.getFrameInfo()->getStackSize();
199 if (Offset > 32767 || Offset < -32768) {
200 // Insert a set of r0 with the full offset value before the ld, st, or add
201 MachineBasicBlock *MBB = MI.getParent();
202 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
203 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
205 // convert into indexed form of the instruction
206 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
207 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
208 unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
209 assert(NewOpcode && "No indexed form of load or store available!");
210 MI.setOpcode(NewOpcode);
211 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
212 MI.SetMachineOperandReg(2, PPC::R0);
214 MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
219 void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
220 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
221 MachineBasicBlock::iterator MBBI = MBB.begin();
222 MachineFrameInfo *MFI = MF.getFrameInfo();
225 // Get the number of bytes to allocate from the FrameInfo
226 unsigned NumBytes = MFI->getStackSize();
228 // If we have calls, we cannot use the red zone to store callee save registers
229 // and we must set up a stack frame, so calculate the necessary size here.
230 if (MFI->hasCalls()) {
231 // We reserve argument space for call sites in the function immediately on
232 // entry to the current function. This eliminates the need for add/sub
233 // brackets around call sites.
234 NumBytes += MFI->getMaxCallFrameSize();
237 // Do we need to allocate space on the stack?
238 if (NumBytes == 0) return;
240 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
241 // of the stack and round the size to a multiple of the alignment.
242 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
243 unsigned R1Size = getRegClass(PPC::R1)->getSize();
244 unsigned R31Size = getRegClass(PPC::R31)->getSize();
245 unsigned Size = (hasFP(MF)) ? R1Size + R31Size : R1Size;
246 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
248 // Update frame info to pretend that this is part of the stack...
249 MFI->setStackSize(NumBytes);
251 // adjust stack pointer: r1 -= numbytes
252 if (NumBytes <= 32768) {
253 unsigned StoreOp = is64bit ? PPC::STDU : PPC::STWU;
254 MI = BuildMI(StoreOp, 3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
255 MBB.insert(MBBI, MI);
257 int NegNumbytes = -NumBytes;
258 unsigned StoreOp = is64bit ? PPC::STDUX : PPC::STWUX;
259 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
260 MBB.insert(MBBI, MI);
261 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
262 .addImm(NegNumbytes & 0xFFFF);
263 MBB.insert(MBBI, MI);
264 MI = BuildMI(StoreOp, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
265 MBB.insert(MBBI, MI);
269 unsigned StoreOp = is64bit ? PPC::STD : PPC::STW;
270 MI = BuildMI(StoreOp, 3).addReg(PPC::R31).addSImm(R1Size).addReg(PPC::R1);
271 MBB.insert(MBBI, MI);
272 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
273 MBB.insert(MBBI, MI);
277 void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
278 MachineBasicBlock &MBB) const {
279 const MachineFrameInfo *MFI = MF.getFrameInfo();
280 MachineBasicBlock::iterator MBBI = prior(MBB.end());
282 assert(MBBI->getOpcode() == PPC::BLR &&
283 "Can only insert epilog into returning blocks");
285 // Get the number of bytes allocated from the FrameInfo...
286 unsigned NumBytes = MFI->getStackSize();
289 unsigned Opcode = is64bit ? PPC::LD : PPC::LWZ;
290 unsigned Offset = is64bit ? 8 : 4;
292 MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31);
293 MBB.insert(MBBI, MI);
294 MI = BuildMI(Opcode, 2, PPC::R31).addSImm(Offset).addReg(PPC::R31);
295 MBB.insert(MBBI, MI);
297 MI = BuildMI(Opcode, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
298 MBB.insert(MBBI, MI);
302 #include "PowerPCGenRegisterInfo.inc"
304 const TargetRegisterClass*
305 PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
306 switch (Ty->getTypeID()) {
307 default: assert(0 && "Invalid type to getClass!");
309 case Type::ULongTyID:
310 if (!is64bit) assert(0 && "Long values can't fit in registers!");
312 case Type::SByteTyID:
313 case Type::UByteTyID:
314 case Type::ShortTyID:
315 case Type::UShortTyID:
318 case Type::PointerTyID: return &GPRCInstance;
320 case Type::FloatTyID:
321 case Type::DoubleTyID: return &FPRCInstance;