1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
29 extern "C" void LLVMInitializePowerPCTarget() {
30 // Register the targets
31 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
38 const Triple &T = ST.getTargetTriple();
41 std::string Ret = "E";
43 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
45 if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
48 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
49 // documentation are wrong; these are correct (i.e. "what gcc does").
50 if (ST.isPPC64() || ST.isSVR4ABI())
55 // Set support for 128 floats depending on the ABI.
56 if (!ST.isPPC64() && ST.isSVR4ABI())
57 Ret += "-f128:64:128";
59 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
68 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
69 StringRef CPU, StringRef FS,
70 const TargetOptions &Options,
71 Reloc::Model RM, CodeModel::Model CM,
74 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
75 Subtarget(TT, CPU, FS, is64Bit),
76 DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
77 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
78 TLInfo(*this), TSInfo(*this),
79 InstrItins(Subtarget.getInstrItineraryData()) {
81 // The binutils for the BG/P are too old for CFI.
82 if (Subtarget.isBGP())
87 void PPC32TargetMachine::anchor() { }
89 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
90 StringRef CPU, StringRef FS,
91 const TargetOptions &Options,
92 Reloc::Model RM, CodeModel::Model CM,
94 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
97 void PPC64TargetMachine::anchor() { }
99 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
100 StringRef CPU, StringRef FS,
101 const TargetOptions &Options,
102 Reloc::Model RM, CodeModel::Model CM,
103 CodeGenOpt::Level OL)
104 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
108 //===----------------------------------------------------------------------===//
109 // Pass Pipeline Configuration
110 //===----------------------------------------------------------------------===//
113 /// PPC Code Generator Pass Configuration Options.
114 class PPCPassConfig : public TargetPassConfig {
116 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
117 : TargetPassConfig(TM, PM) {}
119 PPCTargetMachine &getPPCTargetMachine() const {
120 return getTM<PPCTargetMachine>();
123 const PPCSubtarget &getPPCSubtarget() const {
124 return *getPPCTargetMachine().getSubtargetImpl();
127 virtual bool addPreISel();
128 virtual bool addILPOpts();
129 virtual bool addInstSelector();
130 virtual bool addPreSched2();
131 virtual bool addPreEmitPass();
135 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
136 return new PPCPassConfig(this, PM);
139 bool PPCPassConfig::addPreISel() {
140 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
141 addPass(createPPCCTRLoops(getPPCTargetMachine()));
146 bool PPCPassConfig::addILPOpts() {
147 if (getPPCSubtarget().hasISEL()) {
148 addPass(&EarlyIfConverterID);
155 bool PPCPassConfig::addInstSelector() {
156 // Install an instruction selector.
157 addPass(createPPCISelDag(getPPCTargetMachine()));
160 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
161 addPass(createPPCCTRLoopsVerify());
167 bool PPCPassConfig::addPreSched2() {
168 if (getOptLevel() != CodeGenOpt::None)
169 addPass(&IfConverterID);
174 bool PPCPassConfig::addPreEmitPass() {
175 if (getOptLevel() != CodeGenOpt::None)
176 addPass(createPPCEarlyReturnPass());
177 // Must run branch selection immediately preceding the asm printer.
178 addPass(createPPCBranchSelectionPass());
182 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
183 JITCodeEmitter &JCE) {
184 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
186 Subtarget.SetJITMode();
188 // Machine code emitter pass for PowerPC.
189 PM.add(createPPCJITCodeEmitterPass(*this, JCE));
194 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
195 // Add first the target-independent BasicTTI pass, then our PPC pass. This
196 // allows the PPC pass to delegate to the target independent layer when
198 PM.add(createBasicTargetTransformInfoPass(this));
199 PM.add(createPPCTargetTransformInfoPass(this));