1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31 cl::desc("Disable CTR loops for PPC"));
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35 cl::desc("Disable PPC loop preinc prep"));
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
42 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
43 cl::desc("Enable optimizations on complex GEPs"),
47 EnablePrefetch("enable-ppc-prefetching",
48 cl::desc("disable software prefetching on PPC"),
49 cl::init(false), cl::Hidden);
51 extern "C" void LLVMInitializePowerPCTarget() {
52 // Register the targets
53 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
54 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
55 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
58 /// Return the datalayout string of a subtarget.
59 static std::string getDataLayoutString(const Triple &T) {
60 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
63 // Most PPC* platforms are big endian, PPC64LE is little endian.
64 if (T.getArch() == Triple::ppc64le)
69 Ret += DataLayout::getManglingComponent(T);
71 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
73 if (!is64Bit || T.getOS() == Triple::Lv2)
76 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
77 // documentation are wrong; these are correct (i.e. "what gcc does").
78 if (is64Bit || !T.isOSDarwin())
83 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
92 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
93 std::string FullFS = FS;
94 Triple TargetTriple(TT);
96 // Make sure 64-bit features are available when CPUname is generic
97 if (TargetTriple.getArch() == Triple::ppc64 ||
98 TargetTriple.getArch() == Triple::ppc64le) {
100 FullFS = "+64bit," + FullFS;
105 if (OL >= CodeGenOpt::Default) {
107 FullFS = "+crbits," + FullFS;
112 if (OL != CodeGenOpt::None) {
114 FullFS = "+invariant-function-descriptors," + FullFS;
116 FullFS = "+invariant-function-descriptors";
122 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
123 // If it isn't a Mach-O file then it's going to be a linux ELF
126 return make_unique<TargetLoweringObjectFileMachO>();
128 return make_unique<PPC64LinuxTargetObjectFile>();
131 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
132 const TargetOptions &Options) {
133 if (Options.MCOptions.getABIName().startswith("elfv1"))
134 return PPCTargetMachine::PPC_ABI_ELFv1;
135 else if (Options.MCOptions.getABIName().startswith("elfv2"))
136 return PPCTargetMachine::PPC_ABI_ELFv2;
138 assert(Options.MCOptions.getABIName().empty() &&
139 "Unknown target-abi option!");
141 if (!TT.isMacOSX()) {
142 switch (TT.getArch()) {
143 case Triple::ppc64le:
144 return PPCTargetMachine::PPC_ABI_ELFv2;
146 return PPCTargetMachine::PPC_ABI_ELFv1;
152 return PPCTargetMachine::PPC_ABI_UNKNOWN;
155 // The FeatureString here is a little subtle. We are modifying the feature string
156 // with what are (currently) non-function specific overrides as it goes into the
157 // LLVMTargetMachine constructor and then using the stored value in the
158 // Subtarget constructor below it.
159 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
160 StringRef FS, const TargetOptions &Options,
161 Reloc::Model RM, CodeModel::Model CM,
162 CodeGenOpt::Level OL)
163 : LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU,
164 computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
165 TLOF(createTLOF(Triple(getTargetTriple()))),
166 TargetABI(computeTargetABI(Triple(TT), Options)) {
170 PPCTargetMachine::~PPCTargetMachine() {}
172 void PPC32TargetMachine::anchor() { }
174 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
175 StringRef CPU, StringRef FS,
176 const TargetOptions &Options,
177 Reloc::Model RM, CodeModel::Model CM,
178 CodeGenOpt::Level OL)
179 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
182 void PPC64TargetMachine::anchor() { }
184 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
185 StringRef CPU, StringRef FS,
186 const TargetOptions &Options,
187 Reloc::Model RM, CodeModel::Model CM,
188 CodeGenOpt::Level OL)
189 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
193 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
194 Attribute CPUAttr = F.getFnAttribute("target-cpu");
195 Attribute FSAttr = F.getFnAttribute("target-features");
197 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
198 ? CPUAttr.getValueAsString().str()
200 std::string FS = !FSAttr.hasAttribute(Attribute::None)
201 ? FSAttr.getValueAsString().str()
204 auto &I = SubtargetMap[CPU + FS];
206 // This needs to be done before we create a new subtarget since any
207 // creation will depend on the TM and the code generation flags on the
208 // function that reside in TargetOptions.
209 resetTargetOptions(F);
210 I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
215 //===----------------------------------------------------------------------===//
216 // Pass Pipeline Configuration
217 //===----------------------------------------------------------------------===//
220 /// PPC Code Generator Pass Configuration Options.
221 class PPCPassConfig : public TargetPassConfig {
223 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
224 : TargetPassConfig(TM, PM) {}
226 PPCTargetMachine &getPPCTargetMachine() const {
227 return getTM<PPCTargetMachine>();
230 void addIRPasses() override;
231 bool addPreISel() override;
232 bool addILPOpts() override;
233 bool addInstSelector() override;
234 void addPreRegAlloc() override;
235 void addPreSched2() override;
236 void addPreEmitPass() override;
240 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
241 return new PPCPassConfig(this, PM);
244 void PPCPassConfig::addIRPasses() {
245 addPass(createAtomicExpandPass(&getPPCTargetMachine()));
247 // For the BG/Q (or if explicitly requested), add explicit data prefetch
249 bool UsePrefetching =
250 Triple(TM->getTargetTriple()).getVendor() == Triple::BGQ &&
251 getOptLevel() != CodeGenOpt::None;
252 if (EnablePrefetch.getNumOccurrences() > 0)
253 UsePrefetching = EnablePrefetch;
255 addPass(createPPCLoopDataPrefetchPass());
257 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
258 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
259 // and lower a GEP with multiple indices to either arithmetic operations or
260 // multiple GEPs with single index.
261 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
262 // Call EarlyCSE pass to find and remove subexpressions in the lowered
264 addPass(createEarlyCSEPass());
265 // Do loop invariant code motion in case part of the lowered result is
267 addPass(createLICMPass());
270 TargetPassConfig::addIRPasses();
273 bool PPCPassConfig::addPreISel() {
274 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
275 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
277 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
278 addPass(createPPCCTRLoops(getPPCTargetMachine()));
283 bool PPCPassConfig::addILPOpts() {
284 addPass(&EarlyIfConverterID);
288 bool PPCPassConfig::addInstSelector() {
289 // Install an instruction selector.
290 addPass(createPPCISelDag(getPPCTargetMachine()));
293 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
294 addPass(createPPCCTRLoopsVerify());
297 addPass(createPPCVSXCopyPass());
301 void PPCPassConfig::addPreRegAlloc() {
302 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
303 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
305 if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
306 addPass(createPPCTLSDynamicCallPass());
309 void PPCPassConfig::addPreSched2() {
310 if (getOptLevel() != CodeGenOpt::None)
311 addPass(&IfConverterID);
314 void PPCPassConfig::addPreEmitPass() {
315 if (getOptLevel() != CodeGenOpt::None)
316 addPass(createPPCEarlyReturnPass(), false);
317 // Must run branch selection immediately preceding the asm printer.
318 addPass(createPPCBranchSelectionPass(), false);
321 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
322 return TargetIRAnalysis(
323 [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });