1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
15 #include "PPCMCAsmInfo.h"
16 #include "PPCTargetMachine.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Support/FormattedStream.h"
24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
26 bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
27 if (TheTriple.isOSDarwin())
28 return new PPCMCAsmInfoDarwin(isPPC64);
29 return new PPCLinuxMCAsmInfo(isPPC64);
33 // This is duplicated code. Refactor this.
34 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
35 MCContext &Ctx, TargetAsmBackend &TAB,
37 MCCodeEmitter *Emitter,
40 if (Triple(TT).isOSDarwin())
41 return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
46 extern "C" void LLVMInitializePowerPCTarget() {
47 // Register the targets
48 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
49 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
51 RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo);
52 RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo);
54 // Register the MC Code Emitter
55 TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
56 TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
59 // Register the asm backend.
60 TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
61 TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
63 // Register the object streamer.
64 TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
65 TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
69 PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
70 const std::string &FS, bool is64Bit)
71 : LLVMTargetMachine(T, TT),
72 Subtarget(TT, FS, is64Bit),
73 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
74 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
75 TLInfo(*this), TSInfo(*this),
76 InstrItins(Subtarget.getInstrItineraryData()) {
78 if (getRelocationModel() == Reloc::Default) {
79 if (Subtarget.isDarwin())
80 setRelocationModel(Reloc::DynamicNoPIC);
82 setRelocationModel(Reloc::Static);
86 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
87 /// groups, which typically degrades performance.
88 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
90 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
91 const std::string &FS)
92 : PPCTargetMachine(T, TT, FS, false) {
96 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
97 const std::string &FS)
98 : PPCTargetMachine(T, TT, FS, true) {
102 //===----------------------------------------------------------------------===//
103 // Pass Pipeline Configuration
104 //===----------------------------------------------------------------------===//
106 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
107 CodeGenOpt::Level OptLevel) {
108 // Install an instruction selector.
109 PM.add(createPPCISelDag(*this));
113 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
114 CodeGenOpt::Level OptLevel) {
115 // Must run branch selection immediately preceding the asm printer.
116 PM.add(createPPCBranchSelectionPass());
120 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
121 CodeGenOpt::Level OptLevel,
122 JITCodeEmitter &JCE) {
123 // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
124 // FIXME: This should be moved to TargetJITInfo!!
125 if (Subtarget.isPPC64()) {
126 // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
127 // instructions to materialize arbitrary global variable + function +
128 // constant pool addresses.
129 setRelocationModel(Reloc::PIC_);
130 // Temporary workaround for the inability of PPC64 JIT to handle jump
132 DisableJumpTables = true;
134 setRelocationModel(Reloc::Static);
137 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
139 Subtarget.SetJITMode();
141 // Machine code emitter pass for PowerPC.
142 PM.add(createPPCJITCodeEmitterPass(*this, JCE));