1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
15 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/Target/TargetOptions.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Support/TargetRegistry.h"
23 extern "C" void LLVMInitializePowerPCTarget() {
24 // Register the targets
25 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
26 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
29 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
30 StringRef CPU, StringRef FS,
31 const TargetOptions &Options,
32 Reloc::Model RM, CodeModel::Model CM,
35 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
36 Subtarget(TT, CPU, FS, is64Bit),
37 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
38 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
39 TLInfo(*this), TSInfo(*this),
40 InstrItins(Subtarget.getInstrItineraryData()) {
43 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
44 /// groups, which typically degrades performance.
45 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
47 void PPC32TargetMachine::anchor() { }
49 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
50 StringRef CPU, StringRef FS,
51 const TargetOptions &Options,
52 Reloc::Model RM, CodeModel::Model CM,
54 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
57 void PPC64TargetMachine::anchor() { }
59 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
60 StringRef CPU, StringRef FS,
61 const TargetOptions &Options,
62 Reloc::Model RM, CodeModel::Model CM,
64 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
68 //===----------------------------------------------------------------------===//
69 // Pass Pipeline Configuration
70 //===----------------------------------------------------------------------===//
72 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM) {
73 // Install an instruction selector.
74 PM.add(createPPCISelDag(*this));
78 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM) {
79 // Must run branch selection immediately preceding the asm printer.
80 PM.add(createPPCBranchSelectionPass());
84 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
85 JITCodeEmitter &JCE) {
86 // FIXME: This should be moved to TargetJITInfo!!
87 if (Subtarget.isPPC64())
88 // Temporary workaround for the inability of PPC64 JIT to handle jump
90 Options.DisableJumpTables = true;
92 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
94 Subtarget.SetJITMode();
96 // Machine code emitter pass for PowerPC.
97 PM.add(createPPCJITCodeEmitterPass(*this, JCE));