1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
29 extern "C" void LLVMInitializePowerPCTarget() {
30 // Register the targets
31 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
38 const Triple &T = ST.getTargetTriple();
41 std::string Ret = "E";
43 // PPC64 has 64 bit pointers, PPC32 has 32 bit pointers.
49 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
50 // documentation are wrong; these are correct (i.e. "what gcc does").
51 Ret += "-f64:64:64-i64:64:64";
53 // Set support for 128 floats depending on the ABI.
54 if (ST.isPPC64() && ST.isSVR4ABI()) {
55 if (T.getOS() != llvm::Triple::FreeBSD)
56 Ret += "-f128:128:128";
58 Ret += "-f128:64:128";
61 // Some ABIs support 128 bit vectors.
62 if (ST.isPPC64() && ST.isSVR4ABI())
63 Ret += "-v128:128:128";
65 // PPC64 has 32 and 64 bit register, PPC32 has only 32 bit ones.
74 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
75 StringRef CPU, StringRef FS,
76 const TargetOptions &Options,
77 Reloc::Model RM, CodeModel::Model CM,
80 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
81 Subtarget(TT, CPU, FS, is64Bit),
82 DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
83 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
84 TLInfo(*this), TSInfo(*this),
85 InstrItins(Subtarget.getInstrItineraryData()) {
87 // The binutils for the BG/P are too old for CFI.
88 if (Subtarget.isBGP())
93 void PPC32TargetMachine::anchor() { }
95 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
96 StringRef CPU, StringRef FS,
97 const TargetOptions &Options,
98 Reloc::Model RM, CodeModel::Model CM,
100 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
103 void PPC64TargetMachine::anchor() { }
105 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
106 StringRef CPU, StringRef FS,
107 const TargetOptions &Options,
108 Reloc::Model RM, CodeModel::Model CM,
109 CodeGenOpt::Level OL)
110 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
114 //===----------------------------------------------------------------------===//
115 // Pass Pipeline Configuration
116 //===----------------------------------------------------------------------===//
119 /// PPC Code Generator Pass Configuration Options.
120 class PPCPassConfig : public TargetPassConfig {
122 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
123 : TargetPassConfig(TM, PM) {}
125 PPCTargetMachine &getPPCTargetMachine() const {
126 return getTM<PPCTargetMachine>();
129 const PPCSubtarget &getPPCSubtarget() const {
130 return *getPPCTargetMachine().getSubtargetImpl();
133 virtual bool addPreISel();
134 virtual bool addILPOpts();
135 virtual bool addInstSelector();
136 virtual bool addPreSched2();
137 virtual bool addPreEmitPass();
141 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
142 return new PPCPassConfig(this, PM);
145 bool PPCPassConfig::addPreISel() {
146 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
147 addPass(createPPCCTRLoops(getPPCTargetMachine()));
152 bool PPCPassConfig::addILPOpts() {
153 if (getPPCSubtarget().hasISEL()) {
154 addPass(&EarlyIfConverterID);
161 bool PPCPassConfig::addInstSelector() {
162 // Install an instruction selector.
163 addPass(createPPCISelDag(getPPCTargetMachine()));
166 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
167 addPass(createPPCCTRLoopsVerify());
173 bool PPCPassConfig::addPreSched2() {
174 if (getOptLevel() != CodeGenOpt::None)
175 addPass(&IfConverterID);
180 bool PPCPassConfig::addPreEmitPass() {
181 if (getOptLevel() != CodeGenOpt::None)
182 addPass(createPPCEarlyReturnPass());
183 // Must run branch selection immediately preceding the asm printer.
184 addPass(createPPCBranchSelectionPass());
188 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
189 JITCodeEmitter &JCE) {
190 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
192 Subtarget.SetJITMode();
194 // Machine code emitter pass for PowerPC.
195 PM.add(createPPCJITCodeEmitterPass(*this, JCE));
200 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
201 // Add first the target-independent BasicTTI pass, then our PPC pass. This
202 // allows the PPC pass to delegate to the target independent layer when
204 PM.add(createBasicTargetTransformInfoPass(this));
205 PM.add(createPPCTargetTransformInfoPass(this));