1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31 cl::desc("Disable CTR loops for PPC"));
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35 cl::desc("Disable PPC loop preinc prep"));
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
42 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
43 cl::desc("Disable VSX Swap Removal for PPC"));
46 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
47 cl::desc("Enable optimizations on complex GEPs"),
51 EnablePrefetch("enable-ppc-prefetching",
52 cl::desc("disable software prefetching on PPC"),
53 cl::init(false), cl::Hidden);
56 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
57 cl::desc("Add extra TOC register dependencies"),
58 cl::init(true), cl::Hidden);
60 extern "C" void LLVMInitializePowerPCTarget() {
61 // Register the targets
62 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
63 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
64 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
67 /// Return the datalayout string of a subtarget.
68 static std::string getDataLayoutString(const Triple &T) {
69 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
72 // Most PPC* platforms are big endian, PPC64LE is little endian.
73 if (T.getArch() == Triple::ppc64le)
78 Ret += DataLayout::getManglingComponent(T);
80 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
82 if (!is64Bit || T.getOS() == Triple::Lv2)
85 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
86 // documentation are wrong; these are correct (i.e. "what gcc does").
87 if (is64Bit || !T.isOSDarwin())
92 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
101 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
103 std::string FullFS = FS;
105 // Make sure 64-bit features are available when CPUname is generic
106 if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
108 FullFS = "+64bit," + FullFS;
113 if (OL >= CodeGenOpt::Default) {
115 FullFS = "+crbits," + FullFS;
120 if (OL != CodeGenOpt::None) {
122 FullFS = "+invariant-function-descriptors," + FullFS;
124 FullFS = "+invariant-function-descriptors";
130 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
131 // If it isn't a Mach-O file then it's going to be a linux ELF
134 return make_unique<TargetLoweringObjectFileMachO>();
136 return make_unique<PPC64LinuxTargetObjectFile>();
139 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
140 const TargetOptions &Options) {
141 if (Options.MCOptions.getABIName().startswith("elfv1"))
142 return PPCTargetMachine::PPC_ABI_ELFv1;
143 else if (Options.MCOptions.getABIName().startswith("elfv2"))
144 return PPCTargetMachine::PPC_ABI_ELFv2;
146 assert(Options.MCOptions.getABIName().empty() &&
147 "Unknown target-abi option!");
149 if (!TT.isMacOSX()) {
150 switch (TT.getArch()) {
151 case Triple::ppc64le:
152 return PPCTargetMachine::PPC_ABI_ELFv2;
154 return PPCTargetMachine::PPC_ABI_ELFv1;
160 return PPCTargetMachine::PPC_ABI_UNKNOWN;
163 // The FeatureString here is a little subtle. We are modifying the feature string
164 // with what are (currently) non-function specific overrides as it goes into the
165 // LLVMTargetMachine constructor and then using the stored value in the
166 // Subtarget constructor below it.
167 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
168 StringRef CPU, StringRef FS,
169 const TargetOptions &Options,
170 Reloc::Model RM, CodeModel::Model CM,
171 CodeGenOpt::Level OL)
172 : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
173 computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
174 TLOF(createTLOF(Triple(getTargetTriple()))),
175 TargetABI(computeTargetABI(TT, Options)) {
179 PPCTargetMachine::~PPCTargetMachine() {}
181 void PPC32TargetMachine::anchor() { }
183 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Triple &TT,
184 StringRef CPU, StringRef FS,
185 const TargetOptions &Options,
186 Reloc::Model RM, CodeModel::Model CM,
187 CodeGenOpt::Level OL)
188 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
190 void PPC64TargetMachine::anchor() { }
192 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Triple &TT,
193 StringRef CPU, StringRef FS,
194 const TargetOptions &Options,
195 Reloc::Model RM, CodeModel::Model CM,
196 CodeGenOpt::Level OL)
197 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
200 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
201 Attribute CPUAttr = F.getFnAttribute("target-cpu");
202 Attribute FSAttr = F.getFnAttribute("target-features");
204 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
205 ? CPUAttr.getValueAsString().str()
207 std::string FS = !FSAttr.hasAttribute(Attribute::None)
208 ? FSAttr.getValueAsString().str()
211 auto &I = SubtargetMap[CPU + FS];
213 // This needs to be done before we create a new subtarget since any
214 // creation will depend on the TM and the code generation flags on the
215 // function that reside in TargetOptions.
216 resetTargetOptions(F);
217 I = llvm::make_unique<PPCSubtarget>(
218 Triple(TargetTriple), CPU,
219 // FIXME: It would be good to have the subtarget additions here
220 // not necessary. Anything that turns them on/off (overrides) ends
221 // up being put at the end of the feature string, but the defaults
222 // shouldn't require adding them. Fixing this means pulling Feature64Bit
223 // out of most of the target cpus in the .td file and making it set only
224 // as part of initialization via the TargetTriple.
225 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
230 //===----------------------------------------------------------------------===//
231 // Pass Pipeline Configuration
232 //===----------------------------------------------------------------------===//
235 /// PPC Code Generator Pass Configuration Options.
236 class PPCPassConfig : public TargetPassConfig {
238 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
239 : TargetPassConfig(TM, PM) {}
241 PPCTargetMachine &getPPCTargetMachine() const {
242 return getTM<PPCTargetMachine>();
245 void addIRPasses() override;
246 bool addPreISel() override;
247 bool addILPOpts() override;
248 bool addInstSelector() override;
249 void addMachineSSAOptimization() override;
250 void addPreRegAlloc() override;
251 void addPreSched2() override;
252 void addPreEmitPass() override;
256 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
257 return new PPCPassConfig(this, PM);
260 void PPCPassConfig::addIRPasses() {
261 addPass(createAtomicExpandPass(&getPPCTargetMachine()));
263 // For the BG/Q (or if explicitly requested), add explicit data prefetch
265 bool UsePrefetching =
266 Triple(TM->getTargetTriple()).getVendor() == Triple::BGQ &&
267 getOptLevel() != CodeGenOpt::None;
268 if (EnablePrefetch.getNumOccurrences() > 0)
269 UsePrefetching = EnablePrefetch;
271 addPass(createPPCLoopDataPrefetchPass());
273 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
274 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
275 // and lower a GEP with multiple indices to either arithmetic operations or
276 // multiple GEPs with single index.
277 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
278 // Call EarlyCSE pass to find and remove subexpressions in the lowered
280 addPass(createEarlyCSEPass());
281 // Do loop invariant code motion in case part of the lowered result is
283 addPass(createLICMPass());
286 TargetPassConfig::addIRPasses();
289 bool PPCPassConfig::addPreISel() {
290 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
291 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
293 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
294 addPass(createPPCCTRLoops(getPPCTargetMachine()));
299 bool PPCPassConfig::addILPOpts() {
300 addPass(&EarlyIfConverterID);
304 bool PPCPassConfig::addInstSelector() {
305 // Install an instruction selector.
306 addPass(createPPCISelDag(getPPCTargetMachine()));
309 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
310 addPass(createPPCCTRLoopsVerify());
313 addPass(createPPCVSXCopyPass());
317 void PPCPassConfig::addMachineSSAOptimization() {
318 TargetPassConfig::addMachineSSAOptimization();
319 // For little endian, remove where possible the vector swap instructions
320 // introduced at code generation to normalize vector element order.
321 if (Triple(TM->getTargetTriple()).getArch() == Triple::ppc64le &&
322 !DisableVSXSwapRemoval)
323 addPass(createPPCVSXSwapRemovalPass());
326 void PPCPassConfig::addPreRegAlloc() {
327 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
328 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
330 if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
331 addPass(createPPCTLSDynamicCallPass());
332 if (EnableExtraTOCRegDeps)
333 addPass(createPPCTOCRegDepsPass());
336 void PPCPassConfig::addPreSched2() {
337 if (getOptLevel() != CodeGenOpt::None)
338 addPass(&IfConverterID);
341 void PPCPassConfig::addPreEmitPass() {
342 if (getOptLevel() != CodeGenOpt::None)
343 addPass(createPPCEarlyReturnPass(), false);
344 // Must run branch selection immediately preceding the asm printer.
345 addPass(createPPCBranchSelectionPass(), false);
348 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
349 return TargetIRAnalysis(
350 [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });