1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef POWERPCSUBTARGET_H
15 #define POWERPCSUBTARGET_H
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "PPCISelLowering.h"
20 #include "PPCJITInfo.h"
21 #include "PPCSelectionDAGInfo.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "PPCGenSubtargetInfo.inc"
31 // GCC #defines PPC on Linux but we use it as our namespace name
38 // -m directive values.
67 class PPCSubtarget : public PPCGenSubtargetInfo {
69 /// stackAlignment - The minimum alignment known to hold of the stack frame on
70 /// entry to the function and which must be maintained by every function.
71 unsigned StackAlignment;
73 /// Selected instruction itineraries (one entry per itinerary class.)
74 InstrItineraryData InstrItins;
76 /// Which cpu directive was used.
77 unsigned DarwinDirective;
79 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
90 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
105 bool HasLazyResolverStubs;
109 /// TargetTriple - What processor and OS we're targeting.
112 /// OptLevel - What default optimization level we're emitting code for.
113 CodeGenOpt::Level OptLevel;
121 PPCFrameLowering FrameLowering;
123 PPCInstrInfo InstrInfo;
125 PPCTargetLowering TLInfo;
126 PPCSelectionDAGInfo TSInfo;
129 /// This constructor initializes the data members to match that
130 /// of the specified triple.
132 PPCSubtarget(const std::string &TT, const std::string &CPU,
133 const std::string &FS, PPCTargetMachine &TM, bool is64Bit,
134 CodeGenOpt::Level OptLevel);
136 /// ParseSubtargetFeatures - Parses features string setting specified
137 /// subtarget options. Definition of function is auto generated by tblgen.
138 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
140 /// SetJITMode - This is called to inform the subtarget info that we are
141 /// producing code for the JIT.
144 /// getStackAlignment - Returns the minimum alignment known to hold of the
145 /// stack frame on entry to the function and which must be maintained by every
146 /// function for this subtarget.
147 unsigned getStackAlignment() const { return StackAlignment; }
149 /// getDarwinDirective - Returns the -m directive specified for the cpu.
151 unsigned getDarwinDirective() const { return DarwinDirective; }
153 /// getInstrItins - Return the instruction itineraries based on subtarget
155 const InstrItineraryData *getInstrItineraryData() const override {
159 const PPCFrameLowering *getFrameLowering() const override {
160 return &FrameLowering;
162 const DataLayout *getDataLayout() const override { return &DL; }
163 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
164 PPCJITInfo *getJITInfo() override { return &JITInfo; }
165 const PPCTargetLowering *getTargetLowering() const override {
168 const PPCSelectionDAGInfo *getSelectionDAGInfo() const override {
171 const PPCRegisterInfo *getRegisterInfo() const override {
172 return &getInstrInfo()->getRegisterInfo();
175 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
176 /// so that we can use initializer lists for subtarget initialization.
177 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
179 /// \brief Reset the features for the PowerPC target.
180 void resetSubtargetFeatures(const MachineFunction *MF) override;
182 void initializeEnvironment();
183 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
186 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
188 bool isPPC64() const { return IsPPC64; }
190 /// has64BitSupport - Return true if the selected CPU supports 64-bit
191 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
192 bool has64BitSupport() const { return Has64BitSupport; }
194 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
195 /// registers in 32-bit mode when possible. This can only true if
196 /// has64BitSupport() returns true.
197 bool use64BitRegs() const { return Use64BitRegs; }
199 /// useCRBits - Return true if we should store and manipulate i1 values in
200 /// the individual condition register bits.
201 bool useCRBits() const { return UseCRBits; }
203 /// hasLazyResolverStub - Return true if accesses to the specified global have
204 /// to go through a dyld lazy resolution stub. This means that an extra load
205 /// is required to get the address of the global.
206 bool hasLazyResolverStub(const GlobalValue *GV,
207 const TargetMachine &TM) const;
209 // isJITCodeModel - True if we're generating code for the JIT
210 bool isJITCodeModel() const { return IsJITCodeModel; }
212 // isLittleEndian - True if generating little-endian code
213 bool isLittleEndian() const { return IsLittleEndian; }
215 // Specific obvious features.
216 bool hasFCPSGN() const { return HasFCPSGN; }
217 bool hasFSQRT() const { return HasFSQRT; }
218 bool hasFRE() const { return HasFRE; }
219 bool hasFRES() const { return HasFRES; }
220 bool hasFRSQRTE() const { return HasFRSQRTE; }
221 bool hasFRSQRTES() const { return HasFRSQRTES; }
222 bool hasRecipPrec() const { return HasRecipPrec; }
223 bool hasSTFIWX() const { return HasSTFIWX; }
224 bool hasLFIWAX() const { return HasLFIWAX; }
225 bool hasFPRND() const { return HasFPRND; }
226 bool hasFPCVT() const { return HasFPCVT; }
227 bool hasAltivec() const { return HasAltivec; }
228 bool hasQPX() const { return HasQPX; }
229 bool hasVSX() const { return HasVSX; }
230 bool hasMFOCRF() const { return HasMFOCRF; }
231 bool hasISEL() const { return HasISEL; }
232 bool hasPOPCNTD() const { return HasPOPCNTD; }
233 bool hasLDBRX() const { return HasLDBRX; }
234 bool isBookE() const { return IsBookE; }
235 bool isPPC4xx() const { return IsPPC4xx; }
236 bool isPPC6xx() const { return IsPPC6xx; }
237 bool isE500() const { return IsE500; }
238 bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
239 bool isDeprecatedDST() const { return DeprecatedDST; }
241 const Triple &getTargetTriple() const { return TargetTriple; }
243 /// isDarwin - True if this is any darwin platform.
244 bool isDarwin() const { return TargetTriple.isMacOSX(); }
245 /// isBGQ - True if this is a BG/Q platform.
246 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
248 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
249 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
251 bool isDarwinABI() const { return isDarwin(); }
252 bool isSVR4ABI() const { return !isDarwin(); }
253 bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
255 bool enableEarlyIfConversion() const override { return hasISEL(); }
257 // Scheduling customization.
258 bool enableMachineScheduler() const override;
259 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
260 bool enablePostMachineScheduler() const override;
261 AntiDepBreakMode getAntiDepBreakMode() const override;
262 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
264 void overrideSchedPolicy(MachineSchedPolicy &Policy,
267 unsigned NumRegionInstrs) const override;
268 bool useAA() const override;
270 } // End llvm namespace