1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef POWERPCSUBTARGET_H
15 #define POWERPCSUBTARGET_H
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "PPCISelLowering.h"
20 #include "PPCSelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "PPCGenSubtargetInfo.inc"
30 // GCC #defines PPC on Linux but we use it as our namespace name
37 // -m directive values.
66 class PPCSubtarget : public PPCGenSubtargetInfo {
68 /// stackAlignment - The minimum alignment known to hold of the stack frame on
69 /// entry to the function and which must be maintained by every function.
70 unsigned StackAlignment;
72 /// Selected instruction itineraries (one entry per itinerary class.)
73 InstrItineraryData InstrItins;
75 /// Which cpu directive was used.
76 unsigned DarwinDirective;
78 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
90 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
105 bool HasLazyResolverStubs;
108 /// TargetTriple - What processor and OS we're targeting.
111 /// OptLevel - What default optimization level we're emitting code for.
112 CodeGenOpt::Level OptLevel;
120 PPCFrameLowering FrameLowering;
122 PPCInstrInfo InstrInfo;
123 PPCTargetLowering TLInfo;
124 PPCSelectionDAGInfo TSInfo;
127 /// This constructor initializes the data members to match that
128 /// of the specified triple.
130 PPCSubtarget(const std::string &TT, const std::string &CPU,
131 const std::string &FS, PPCTargetMachine &TM, bool is64Bit,
132 CodeGenOpt::Level OptLevel);
134 /// ParseSubtargetFeatures - Parses features string setting specified
135 /// subtarget options. Definition of function is auto generated by tblgen.
136 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
138 /// getStackAlignment - Returns the minimum alignment known to hold of the
139 /// stack frame on entry to the function and which must be maintained by every
140 /// function for this subtarget.
141 unsigned getStackAlignment() const { return StackAlignment; }
143 /// getDarwinDirective - Returns the -m directive specified for the cpu.
145 unsigned getDarwinDirective() const { return DarwinDirective; }
147 /// getInstrItins - Return the instruction itineraries based on subtarget
149 const InstrItineraryData *getInstrItineraryData() const override {
153 const PPCFrameLowering *getFrameLowering() const override {
154 return &FrameLowering;
156 const DataLayout *getDataLayout() const override { return &DL; }
157 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
158 const PPCTargetLowering *getTargetLowering() const override {
161 const PPCSelectionDAGInfo *getSelectionDAGInfo() const override {
164 const PPCRegisterInfo *getRegisterInfo() const override {
165 return &getInstrInfo()->getRegisterInfo();
168 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
169 /// so that we can use initializer lists for subtarget initialization.
170 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
172 /// \brief Reset the features for the PowerPC target.
173 void resetSubtargetFeatures(const MachineFunction *MF) override;
175 void initializeEnvironment();
176 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
179 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
181 bool isPPC64() const { return IsPPC64; }
183 /// has64BitSupport - Return true if the selected CPU supports 64-bit
184 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
185 bool has64BitSupport() const { return Has64BitSupport; }
187 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
188 /// registers in 32-bit mode when possible. This can only true if
189 /// has64BitSupport() returns true.
190 bool use64BitRegs() const { return Use64BitRegs; }
192 /// useCRBits - Return true if we should store and manipulate i1 values in
193 /// the individual condition register bits.
194 bool useCRBits() const { return UseCRBits; }
196 /// hasLazyResolverStub - Return true if accesses to the specified global have
197 /// to go through a dyld lazy resolution stub. This means that an extra load
198 /// is required to get the address of the global.
199 bool hasLazyResolverStub(const GlobalValue *GV,
200 const TargetMachine &TM) const;
202 // isLittleEndian - True if generating little-endian code
203 bool isLittleEndian() const { return IsLittleEndian; }
205 // Specific obvious features.
206 bool hasFCPSGN() const { return HasFCPSGN; }
207 bool hasFSQRT() const { return HasFSQRT; }
208 bool hasFRE() const { return HasFRE; }
209 bool hasFRES() const { return HasFRES; }
210 bool hasFRSQRTE() const { return HasFRSQRTE; }
211 bool hasFRSQRTES() const { return HasFRSQRTES; }
212 bool hasRecipPrec() const { return HasRecipPrec; }
213 bool hasSTFIWX() const { return HasSTFIWX; }
214 bool hasLFIWAX() const { return HasLFIWAX; }
215 bool hasFPRND() const { return HasFPRND; }
216 bool hasFPCVT() const { return HasFPCVT; }
217 bool hasAltivec() const { return HasAltivec; }
218 bool hasSPE() const { return HasSPE; }
219 bool hasQPX() const { return HasQPX; }
220 bool hasVSX() const { return HasVSX; }
221 bool hasMFOCRF() const { return HasMFOCRF; }
222 bool hasISEL() const { return HasISEL; }
223 bool hasPOPCNTD() const { return HasPOPCNTD; }
224 bool hasLDBRX() const { return HasLDBRX; }
225 bool isBookE() const { return IsBookE; }
226 bool isPPC4xx() const { return IsPPC4xx; }
227 bool isPPC6xx() const { return IsPPC6xx; }
228 bool isE500() const { return IsE500; }
229 bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
230 bool isDeprecatedDST() const { return DeprecatedDST; }
232 const Triple &getTargetTriple() const { return TargetTriple; }
234 /// isDarwin - True if this is any darwin platform.
235 bool isDarwin() const { return TargetTriple.isMacOSX(); }
236 /// isBGQ - True if this is a BG/Q platform.
237 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
239 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
240 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
242 bool isDarwinABI() const { return isDarwin(); }
243 bool isSVR4ABI() const { return !isDarwin(); }
244 bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
246 bool enableEarlyIfConversion() const override { return hasISEL(); }
248 // Scheduling customization.
249 bool enableMachineScheduler() const override;
250 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
251 bool enablePostMachineScheduler() const override;
252 AntiDepBreakMode getAntiDepBreakMode() const override;
253 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
255 void overrideSchedPolicy(MachineSchedPolicy &Policy,
258 unsigned NumRegionInstrs) const override;
259 bool useAA() const override;
261 } // End llvm namespace