1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
29 #define DEBUG_TYPE "ppc-subtarget"
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
35 /// Return the datalayout string of a subtarget.
36 static std::string getDataLayoutString(const PPCSubtarget &ST) {
37 const Triple &T = ST.getTargetTriple();
41 // Most PPC* platforms are big endian, PPC64LE is little endian.
42 if (ST.isLittleEndian())
47 Ret += DataLayout::getManglingComponent(T);
49 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
51 if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
54 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
55 // documentation are wrong; these are correct (i.e. "what gcc does").
56 if (ST.isPPC64() || ST.isSVR4ABI())
61 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
70 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
72 initializeEnvironment();
73 resetSubtargetFeatures(CPU, FS);
77 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
78 const std::string &FS, PPCTargetMachine &TM,
79 CodeGenOpt::Level OptLevel)
80 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
81 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
82 TargetTriple.getArch() == Triple::ppc64le),
83 OptLevel(OptLevel), TargetABI(PPC_ABI_UNKNOWN),
84 FrameLowering(initializeSubtargetDependencies(CPU, FS)),
85 DL(getDataLayoutString(*this)), InstrInfo(*this), JITInfo(*this),
86 TLInfo(TM), TSInfo(&DL) {}
88 /// SetJITMode - This is called to inform the subtarget info that we are
89 /// producing code for the JIT.
90 void PPCSubtarget::SetJITMode() {
91 // JIT mode doesn't want lazy resolver stubs, it knows exactly where
92 // everything is. This matters for PPC64, which codegens in PIC mode without
94 HasLazyResolverStubs = false;
96 // Calls to external functions need to use indirect calls
97 IsJITCodeModel = true;
100 void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
101 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
102 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
104 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
107 !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
109 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
111 initializeEnvironment();
112 resetSubtargetFeatures(CPU, FS);
116 void PPCSubtarget::initializeEnvironment() {
118 DarwinDirective = PPC::DIR_NONE;
120 Has64BitSupport = false;
121 Use64BitRegs = false;
133 HasRecipPrec = false;
145 DeprecatedMFTB = false;
146 DeprecatedDST = false;
147 HasLazyResolverStubs = false;
148 IsJITCodeModel = false;
151 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
152 // Determine default and user specified characteristics
153 std::string CPUName = CPU;
156 #if (defined(__APPLE__) || defined(__linux__)) && \
157 (defined(__ppc__) || defined(__powerpc__))
158 if (CPUName == "generic")
159 CPUName = sys::getHostCPUName();
162 // Initialize scheduling itinerary for the specified CPU.
163 InstrItins = getInstrItineraryForCPU(CPUName);
165 // Make sure 64-bit features are available when CPUname is generic
166 std::string FullFS = FS;
168 // If we are generating code for ppc64, verify that options make sense.
170 Has64BitSupport = true;
171 // Silently force 64-bit register use on ppc64.
174 FullFS = "+64bit," + FullFS;
179 // At -O2 and above, track CR bits as individual registers.
180 if (OptLevel >= CodeGenOpt::Default) {
182 FullFS = "+crbits," + FullFS;
187 // Parse features string.
188 ParseSubtargetFeatures(CPUName, FullFS);
190 // If the user requested use of 64-bit regs, but the cpu selected doesn't
191 // support it, ignore.
192 if (use64BitRegs() && !has64BitSupport())
193 Use64BitRegs = false;
195 // Set up darwin-specific properties.
197 HasLazyResolverStubs = true;
199 // QPX requires a 32-byte aligned stack. Note that we need to do this if
200 // we're compiling for a BG/Q system regardless of whether or not QPX
201 // is enabled because external functions will assume this alignment.
202 if (hasQPX() || isBGQ())
205 // Determine endianness.
206 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
208 // FIXME: For now, we disable VSX in little-endian mode until endian
209 // issues in those instructions can be addressed.
213 // Determine default ABI.
214 if (TargetABI == PPC_ABI_UNKNOWN) {
215 if (!isDarwin() && IsPPC64) {
217 TargetABI = PPC_ABI_ELFv2;
219 TargetABI = PPC_ABI_ELFv1;
224 /// hasLazyResolverStub - Return true if accesses to the specified global have
225 /// to go through a dyld lazy resolution stub. This means that an extra load
226 /// is required to get the address of the global.
227 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
228 const TargetMachine &TM) const {
229 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
230 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
232 // If symbol visibility is hidden, the extra load is not needed if
233 // the symbol is definitely defined in the current translation unit.
234 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
235 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
237 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
238 GV->hasCommonLinkage() || isDecl;
241 // Embedded cores need aggressive scheduling (and some others also benefit).
242 static bool needsAggressiveScheduling(unsigned Directive) {
244 default: return false;
247 case PPC::DIR_E500mc:
255 bool PPCSubtarget::enableMachineScheduler() const {
256 // Enable MI scheduling for the embedded cores.
257 // FIXME: Enable this for all cores (some additional modeling
258 // may be necessary).
259 return needsAggressiveScheduling(DarwinDirective);
262 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
263 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
265 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
266 return TargetSubtargetInfo::ANTIDEP_ALL;
269 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
270 CriticalPathRCs.clear();
271 CriticalPathRCs.push_back(isPPC64() ?
272 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
275 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
278 unsigned NumRegionInstrs) const {
279 if (needsAggressiveScheduling(DarwinDirective)) {
280 Policy.OnlyTopDown = false;
281 Policy.OnlyBottomUp = false;
284 // Spilling is generally expensive on all PPC cores, so always enable
285 // register-pressure tracking.
286 Policy.ShouldTrackPressure = true;
289 bool PPCSubtarget::useAA() const {
290 // Use AA during code generation for the embedded cores.
291 return needsAggressiveScheduling(DarwinDirective);