lib/Target/PowerPC/PPCScheduleE5500.td

   1 //===-- PPCScheduleE500mc.td - e5500 Scheduling Defs -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the Freescale e5500 64-bit
  11 // Power processor.
  12 //
  13 // All information is derived from the "e5500 Core Reference Manual",
  14 // Freescale Document Number e5500RM, Rev. 1, 03/2012.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 // Relevant functional units in the Freescale e5500 core
  18 // (These are the same as for the e500mc)
  19 //
  20 //  * Decode & Dispatch
  21 //    Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
  22 //    queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
  23 def E5500_DIS0 : FuncUnit;
  24 def E5500_DIS1 : FuncUnit;
  25
  26 //  * Execute
  27 //    6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
  28 //    The CFX has a bypass path, allowing non-divide instructions to execute
  29 //    while a divide instruction is being executed.
  30 def E5500_SFX0  : FuncUnit; // Simple unit 0
  31 def E5500_SFX1  : FuncUnit; // Simple unit 1
  32 def E5500_BU    : FuncUnit; // Branch unit
  33 def E5500_CFX_DivBypass
  34                 : FuncUnit; // CFX divide bypass path
  35 def E5500_CFX_0 : FuncUnit; // CFX pipeline stage 0
  36
  37 def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 1
  38
  39 def E5500_LSU_0 : FuncUnit; // LSU pipeline
  40 def E5500_FPU_0 : FuncUnit; // FPU pipeline
  41
  42 def E5500_GPR_Bypass : Bypass;
  43 def E5500_FPR_Bypass : Bypass;
  44 def E5500_CR_Bypass  : Bypass;
  45
  46 def PPCE5500Itineraries : ProcessorItineraries<
  47   [E5500_DIS0, E5500_DIS1, E5500_SFX0, E5500_SFX1, E5500_BU,
  48    E5500_CFX_DivBypass, E5500_CFX_0, E5500_CFX_1,
  49    E5500_LSU_0, E5500_FPU_0],
  50   [E5500_CR_Bypass, E5500_GPR_Bypass, E5500_FPR_Bypass], [
  51   InstrItinData<IIC_IntSimple,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  52                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
  53                                  [5, 2, 2], // Latency = 1
  54                                  [E5500_GPR_Bypass,
  55                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  56   InstrItinData<IIC_IntGeneral,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  57                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
  58                                  [5, 2, 2], // Latency = 1
  59                                  [E5500_GPR_Bypass,
  60                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  61   InstrItinData<IIC_IntISEL,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  62                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
  63                                  [5, 2, 2, 2], // Latency = 1
  64                                  [E5500_GPR_Bypass,
  65                                   E5500_GPR_Bypass, E5500_GPR_Bypass,
  66                                   E5500_CR_Bypass]>,
  67   InstrItinData<IIC_IntCompare,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  68                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
  69                                  [6, 2, 2], // Latency = 1 or 2
  70                                  [E5500_CR_Bypass,
  71                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  72   InstrItinData<IIC_IntDivD,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  73                                   InstrStage<1, [E5500_CFX_0], 0>,
  74                                   InstrStage<26, [E5500_CFX_DivBypass]>],
  75                                  [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
  76                                  [E5500_GPR_Bypass,
  77                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  78   InstrItinData<IIC_IntDivW,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  79                                   InstrStage<1, [E5500_CFX_0], 0>,
  80                                   InstrStage<16, [E5500_CFX_DivBypass]>],
  81                                  [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
  82                                  [E5500_GPR_Bypass,
  83                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  84   InstrItinData<IIC_IntMFFS,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  85                                   InstrStage<1, [E5500_FPU_0]>],
  86                                  [11], // Latency = 7, Repeat rate = 1
  87                                  [E5500_FPR_Bypass]>,
  88   InstrItinData<IIC_IntMTFSB0,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  89                                   InstrStage<7, [E5500_FPU_0]>],
  90                                  [11, 2, 2], // Latency = 7, Repeat rate = 7
  91                                  [NoBypass, NoBypass, NoBypass]>,
  92   InstrItinData<IIC_IntMulHD,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  93                                   InstrStage<1, [E5500_CFX_0], 0>,
  94                                   InstrStage<2, [E5500_CFX_1]>],
  95                                  [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
  96                                  [E5500_GPR_Bypass,
  97                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  98   InstrItinData<IIC_IntMulHW,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  99                                   InstrStage<1, [E5500_CFX_0], 0>,
 100                                   InstrStage<1, [E5500_CFX_1]>],
 101                                  [8, 2, 2], // Latency = 4, Repeat rate = 1
 102                                  [E5500_GPR_Bypass,
 103                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 104   InstrItinData<IIC_IntMulHWU,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 105                                   InstrStage<1, [E5500_CFX_0], 0>,
 106                                   InstrStage<1, [E5500_CFX_1]>],
 107                                  [8, 2, 2], // Latency = 4, Repeat rate = 1
 108                                  [E5500_GPR_Bypass,
 109                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 110   InstrItinData<IIC_IntMulLI,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 111                                   InstrStage<1, [E5500_CFX_0], 0>,
 112                                   InstrStage<2, [E5500_CFX_1]>],
 113                                  [8, 2, 2], // Latency = 4 or 5, Repeat = 2
 114                                  [E5500_GPR_Bypass,
 115                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 116   InstrItinData<IIC_IntRotate,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 117                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
 118                                  [5, 2, 2], // Latency = 1
 119                                  [E5500_GPR_Bypass,
 120                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 121   InstrItinData<IIC_IntRotateD,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 122                                   InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
 123                                  [6, 2, 2], // Latency = 2, Repeat rate = 2
 124                                  [E5500_GPR_Bypass,
 125                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 126   InstrItinData<IIC_IntRotateDI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 127                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
 128                                  [5, 2, 2], // Latency = 1, Repeat rate = 1
 129                                  [E5500_GPR_Bypass,
 130                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 131   InstrItinData<IIC_IntShift,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 132                                   InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
 133                                  [6, 2, 2], // Latency = 2, Repeat rate = 2
 134                                  [E5500_GPR_Bypass,
 135                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 136   InstrItinData<IIC_IntTrapW,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 137                                   InstrStage<2, [E5500_SFX0]>],
 138                                  [6, 2], // Latency = 2, Repeat rate = 2
 139                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 140   InstrItinData<IIC_BrB,         [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 141                                   InstrStage<1, [E5500_BU]>],
 142                                  [5, 2], // Latency = 1
 143                                  [NoBypass, E5500_GPR_Bypass]>,
 144   InstrItinData<IIC_BrCR,        [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 145                                   InstrStage<1, [E5500_BU]>],
 146                                  [5, 2, 2], // Latency = 1
 147                                  [E5500_CR_Bypass,
 148                                   E5500_CR_Bypass, E5500_CR_Bypass]>,
 149   InstrItinData<IIC_BrMCR,       [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 150                                   InstrStage<1, [E5500_BU]>],
 151                                  [5, 2], // Latency = 1
 152                                  [E5500_CR_Bypass, E5500_CR_Bypass]>,
 153   InstrItinData<IIC_BrMCRX,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 154                                   InstrStage<1, [E5500_CFX_0]>],
 155                                  [5, 2, 2], // Latency = 1
 156                                  [E5500_CR_Bypass, E5500_GPR_Bypass]>,
 157   InstrItinData<IIC_LdStDCBA,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 158                                   InstrStage<1, [E5500_LSU_0]>],
 159                                  [7, 2], // Latency = 3, Repeat rate = 1
 160                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 161   InstrItinData<IIC_LdStDCBF,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 162                                   InstrStage<1, [E5500_LSU_0]>],
 163                                  [7, 2], // Latency = 3, Repeat rate = 1
 164                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 165   InstrItinData<IIC_LdStDCBI,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 166                                   InstrStage<1, [E5500_LSU_0]>],
 167                                  [7, 2], // Latency = 3, Repeat rate = 1
 168                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 169   InstrItinData<IIC_LdStLoad,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 170                                   InstrStage<1, [E5500_LSU_0]>],
 171                                  [7, 2], // Latency = 3
 172                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 173   InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 174                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 175                                   InstrStage<1, [E5500_LSU_0]>],
 176                                  [7, 2], // Latency = 3, Repeat rate = 1
 177                                  [E5500_GPR_Bypass, E5500_GPR_Bypass],
 178                                  2>, // 2 micro-ops
 179   InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 180                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 181                                   InstrStage<1, [E5500_LSU_0]>],
 182                                  [7, 2], // Latency = 3, Repeat rate = 1
 183                                  [E5500_GPR_Bypass, E5500_GPR_Bypass],
 184                                  2>, // 2 micro-ops
 185   InstrItinData<IIC_LdStLD,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 186                                   InstrStage<1, [E5500_LSU_0]>],
 187                                  [7, 2], // Latency = 3, Repeat rate = 1
 188                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 189   InstrItinData<IIC_LdStLDARX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 190                                   InstrStage<3, [E5500_LSU_0]>],
 191                                  [7, 2], // Latency = 3, Repeat rate = 3
 192                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 193   InstrItinData<IIC_LdStLDU,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 194                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 195                                   InstrStage<1, [E5500_LSU_0]>],
 196                                  [7, 2], // Latency = 3, Repeat rate = 1
 197                                  [E5500_GPR_Bypass, E5500_GPR_Bypass],
 198                                  2>, // 2 micro-ops
 199   InstrItinData<IIC_LdStLDUX,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 200                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 201                                   InstrStage<1, [E5500_LSU_0]>],
 202                                  [7, 2], // Latency = 3, Repeat rate = 1
 203                                  [E5500_GPR_Bypass, E5500_GPR_Bypass],
 204                                  2>, // 2 micro-ops
 205   InstrItinData<IIC_LdStStore,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 206                                   InstrStage<1, [E5500_LSU_0]>],
 207                                  [7, 2], // Latency = 3, Repeat rate = 1
 208                                  [NoBypass, E5500_GPR_Bypass]>,
 209   InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 210                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 211                                   InstrStage<1, [E5500_LSU_0]>],
 212                                  [7, 2], // Latency = 3, Repeat rate = 1
 213                                  [NoBypass, E5500_GPR_Bypass],
 214                                  2>, // 2 micro-ops
 215   InstrItinData<IIC_LdStICBI,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 216                                   InstrStage<1, [E5500_LSU_0]>],
 217                                  [7, 2], // Latency = 3, Repeat rate = 1
 218                                  [NoBypass, E5500_GPR_Bypass]>,
 219   InstrItinData<IIC_LdStSTFD,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 220                                   InstrStage<1, [E5500_LSU_0]>],
 221                                  [7, 2, 2], // Latency = 3, Repeat rate = 1
 222                                  [E5500_GPR_Bypass,
 223                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 224   InstrItinData<IIC_LdStSTFDU,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 225                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 226                                   InstrStage<1, [E5500_LSU_0]>],
 227                                  [7, 2, 2], // Latency = 3, Repeat rate = 1
 228                                  [E5500_GPR_Bypass,
 229                                   E5500_GPR_Bypass, E5500_GPR_Bypass],
 230                                  2>, // 2 micro-ops
 231   InstrItinData<IIC_LdStLFD,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 232                                   InstrStage<1, [E5500_LSU_0]>],
 233                                  [8, 2, 2], // Latency = 4, Repeat rate = 1
 234                                  [E5500_FPR_Bypass,
 235                                   E5500_GPR_Bypass, E5500_GPR_Bypass],
 236                                  2>, // 2 micro-ops
 237   InstrItinData<IIC_LdStLFDU,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 238                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 239                                   InstrStage<1, [E5500_LSU_0]>],
 240                                  [8, 2, 2], // Latency = 4, Repeat rate = 1
 241                                  [E5500_FPR_Bypass,
 242                                   E5500_GPR_Bypass, E5500_GPR_Bypass],
 243                                  2>, // 2 micro-ops
 244   InstrItinData<IIC_LdStLFDUX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 245                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 246                                   InstrStage<1, [E5500_LSU_0]>],
 247                                  [8, 2, 2], // Latency = 4, Repeat rate = 1
 248                                  [E5500_FPR_Bypass,
 249                                   E5500_GPR_Bypass, E5500_GPR_Bypass],
 250                                  2>, // 2 micro-ops
 251   InstrItinData<IIC_LdStLHA,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 252                                   InstrStage<1, [E5500_LSU_0]>],
 253                                  [7, 2], // Latency = 3
 254                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 255   InstrItinData<IIC_LdStLHAU,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 256                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 257                                   InstrStage<1, [E5500_LSU_0]>],
 258                                  [7, 2], // Latency = 3, Repeat rate = 1
 259                                  [E5500_GPR_Bypass, E5500_GPR_Bypass],
 260                                  2>, // 2 micro-ops
 261   InstrItinData<IIC_LdStLHAUX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 262                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 263                                   InstrStage<1, [E5500_LSU_0]>],
 264                                  [7, 2], // Latency = 3, Repeat rate = 1
 265                                  [E5500_GPR_Bypass, E5500_GPR_Bypass],
 266                                  2>, // 2 micro-ops
 267   InstrItinData<IIC_LdStLMW,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 268                                   InstrStage<4, [E5500_LSU_0]>],
 269                                  [8, 2], // Latency = r+3, Repeat rate = r+3
 270                                  [NoBypass, E5500_GPR_Bypass]>,
 271   InstrItinData<IIC_LdStLWARX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 272                                   InstrStage<3, [E5500_LSU_0]>],
 273                                  [7, 2, 2], // Latency = 3, Repeat rate = 3
 274                                  [E5500_GPR_Bypass,
 275                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 276   InstrItinData<IIC_LdStSTD,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 277                                   InstrStage<1, [E5500_LSU_0]>],
 278                                  [7, 2], // Latency = 3, Repeat rate = 1
 279                                  [NoBypass, E5500_GPR_Bypass]>,
 280   InstrItinData<IIC_LdStSTDCX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 281                                   InstrStage<1, [E5500_LSU_0]>],
 282                                  [7, 2], // Latency = 3, Repeat rate = 1
 283                                  [NoBypass, E5500_GPR_Bypass]>,
 284   InstrItinData<IIC_LdStSTDU,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 285                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 286                                   InstrStage<1, [E5500_LSU_0]>],
 287                                  [7, 2], // Latency = 3, Repeat rate = 1
 288                                  [NoBypass, E5500_GPR_Bypass],
 289                                  2>, // 2 micro-ops
 290   InstrItinData<IIC_LdStSTDUX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 291                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 292                                   InstrStage<1, [E5500_LSU_0]>],
 293                                  [7, 2], // Latency = 3, Repeat rate = 1
 294                                  [NoBypass, E5500_GPR_Bypass],
 295                                  2>, // 2 micro-ops
 296   InstrItinData<IIC_LdStSTWCX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 297                                   InstrStage<1, [E5500_LSU_0]>],
 298                                  [7, 2], // Latency = 3, Repeat rate = 1
 299                                  [NoBypass, E5500_GPR_Bypass]>,
 300   InstrItinData<IIC_LdStSync,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 301                                   InstrStage<1, [E5500_LSU_0]>]>,
 302   InstrItinData<IIC_SprMTMSR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 303                                   InstrStage<2, [E5500_CFX_0]>],
 304                                  [6, 2], // Latency = 2, Repeat rate = 4
 305                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 306   InstrItinData<IIC_SprTLBSYNC,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 307                                   InstrStage<1, [E5500_LSU_0], 0>]>,
 308   InstrItinData<IIC_SprMFCR,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 309                                   InstrStage<5, [E5500_CFX_0]>],
 310                                  [9, 2], // Latency = 5, Repeat rate = 5
 311                                  [E5500_GPR_Bypass, E5500_CR_Bypass]>,
 312   InstrItinData<IIC_SprMFCRF,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 313                                   InstrStage<5, [E5500_CFX_0]>],
 314                                  [9, 2], // Latency = 5, Repeat rate = 5
 315                                  [E5500_GPR_Bypass, E5500_CR_Bypass]>,
 316   InstrItinData<IIC_SprMFMSR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 317                                   InstrStage<4, [E5500_SFX0]>],
 318                                  [8, 2], // Latency = 4, Repeat rate = 4
 319                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 320   InstrItinData<IIC_SprMFSPR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 321                                   InstrStage<1, [E5500_CFX_0]>],
 322                                  [5], // Latency = 1, Repeat rate = 1
 323                                  [E5500_GPR_Bypass]>,
 324   InstrItinData<IIC_SprMFTB,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 325                                   InstrStage<4, [E5500_CFX_0]>],
 326                                  [8, 2], // Latency = 4, Repeat rate = 4
 327                                  [NoBypass, E5500_GPR_Bypass]>,
 328   InstrItinData<IIC_SprMTSPR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 329                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
 330                                  [5], // Latency = 1, Repeat rate = 1
 331                                  [E5500_GPR_Bypass]>,
 332   InstrItinData<IIC_FPGeneral,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 333                                   InstrStage<1, [E5500_FPU_0]>],
 334                                  [11, 2, 2], // Latency = 7, Repeat rate = 1
 335                                  [E5500_FPR_Bypass,
 336                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 337   InstrItinData<IIC_FPAddSub,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 338                                   InstrStage<1, [E5500_FPU_0]>],
 339                                  [11, 2, 2], // Latency = 7, Repeat rate = 1
 340                                  [E5500_FPR_Bypass,
 341                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 342   InstrItinData<IIC_FPCompare,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 343                                   InstrStage<1, [E5500_FPU_0]>],
 344                                  [11, 2, 2], // Latency = 7, Repeat rate = 1
 345                                  [E5500_CR_Bypass,
 346                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 347   InstrItinData<IIC_FPDivD,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 348                                   InstrStage<31, [E5500_FPU_0]>],
 349                                  [39, 2, 2], // Latency = 35, Repeat rate = 31
 350                                  [E5500_FPR_Bypass,
 351                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 352   InstrItinData<IIC_FPDivS,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 353                                   InstrStage<16, [E5500_FPU_0]>],
 354                                  [24, 2, 2], // Latency = 20, Repeat rate = 16
 355                                  [E5500_FPR_Bypass,
 356                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 357   InstrItinData<IIC_FPFused,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 358                                   InstrStage<1, [E5500_FPU_0]>],
 359                                  [11, 2, 2, 2], // Latency = 7, Repeat rate = 1
 360                                  [E5500_FPR_Bypass,
 361                                   E5500_FPR_Bypass, E5500_FPR_Bypass,
 362                                   E5500_FPR_Bypass]>,
 363   InstrItinData<IIC_FPRes,       [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 364                                   InstrStage<2, [E5500_FPU_0]>],
 365                                  [12, 2], // Latency = 8, Repeat rate = 2
 366                                  [E5500_FPR_Bypass, E5500_FPR_Bypass]>
 367 ]>;
 368
 369 // ===---------------------------------------------------------------------===//
 370 // e5500 machine model for scheduling and other instruction cost heuristics.
 371
 372 def PPCE5500Model : SchedMachineModel {
 373   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
 374   let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
 375   let LoadLatency = 6; // Optimistic load latency assuming bypass.
 376                        // This is overriden by OperandCycles if the
 377                        // Itineraries are queried instead.
 378
 379   let Itineraries = PPCE5500Itineraries;
 380 }