lib/Target/PowerPC/PPCSchedule440.td

   1 //===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // Primary reference:
  11 // PowerPC 440x6 Embedded Processor Core User's Manual.
  12 // IBM (as updated in) 2010.
  13
  14 // The basic PPC 440 does not include a floating-point unit; the pipeline
  15 // timings here are constructed to match the FP2 unit shipped with the
  16 // PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
  17 // References:
  18 // S. Chatterjee, et al. Design and exploitation of a high-performance
  19 // SIMD floating-point unit for Blue Gene/L.
  20 // IBM J. Res. & Dev. 49 (2/3) March/May 2005.
  21 // also:
  22 // Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
  23 // Blue Gene/P Application Development.
  24 // IBM (as updated in) 2009.
  25
  26 //===----------------------------------------------------------------------===//
  27 // Functional units on the PowerPC 440/450 chip sets
  28 //
  29 def P440_DISS1  : FuncUnit; // Issue unit 1
  30 def P440_DISS2  : FuncUnit; // Issue unit 2
  31 def P440_LRACC  : FuncUnit; // Register access and dispatch for
  32                             // the simple integer (J-pipe) and
  33                             // load/store (L-pipe) pipelines
  34 def P440_IRACC  : FuncUnit; // Register access and dispatch for
  35                             // the complex integer (I-pipe) pipeline
  36 def P440_FRACC  : FuncUnit; // Register access and dispatch for
  37                             // the floating-point execution (F-pipe) pipeline
  38 def P440_IEXE1  : FuncUnit; // Execution stage 1 for the I pipeline
  39 def P440_IEXE2  : FuncUnit; // Execution stage 2 for the I pipeline
  40 def P440_IWB    : FuncUnit; // Write-back unit for the I pipeline
  41 def P440_JEXE1  : FuncUnit; // Execution stage 1 for the J pipeline
  42 def P440_JEXE2  : FuncUnit; // Execution stage 2 for the J pipeline
  43 def P440_JWB    : FuncUnit; // Write-back unit for the J pipeline
  44 def P440_AGEN   : FuncUnit; // Address generation for the L pipeline
  45 def P440_CRD    : FuncUnit; // D-cache access for the L pipeline
  46 def P440_LWB    : FuncUnit; // Write-back unit for the L pipeline
  47 def P440_FEXE1  : FuncUnit; // Execution stage 1 for the F pipeline
  48 def P440_FEXE2  : FuncUnit; // Execution stage 2 for the F pipeline
  49 def P440_FEXE3  : FuncUnit; // Execution stage 3 for the F pipeline
  50 def P440_FEXE4  : FuncUnit; // Execution stage 4 for the F pipeline
  51 def P440_FEXE5  : FuncUnit; // Execution stage 5 for the F pipeline
  52 def P440_FEXE6  : FuncUnit; // Execution stage 6 for the F pipeline
  53 def P440_FWB    : FuncUnit; // Write-back unit for the F pipeline
  54
  55 def P440_LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
  56                                 // to make sure that no lwarx/stwcx.
  57                                 // instructions are issued while another
  58                                 // lwarx/stwcx. is in the L pipe.
  59
  60 def P440_GPR_Bypass : Bypass; // The bypass for general-purpose regs.
  61 def P440_FPR_Bypass : Bypass; // The bypass for floating-point regs.
  62
  63 // Notes:
  64 // Instructions are held in the FRACC, LRACC and IRACC pipeline
  65 // stages until their source operands become ready. Exceptions:
  66 //  - Store instructions will hold in the AGEN stage
  67 //  - The integer multiply-accumulate instruction will hold in
  68 //    the IEXE1 stage
  69 //
  70 // For most I-pipe operations, the result is available at the end of
  71 // the IEXE1 stage. Operations such as multiply and divide must
  72 // continue to execute in IEXE2 and IWB. Divide resides in IWB for
  73 // 33 cycles (multiply also calculates its result in IWB). For all
  74 // J-pipe instructions, the result is available
  75 // at the end of the JEXE1 stage. Loads have a 3-cycle latency
  76 // (data is not available until after the LWB stage).
  77 //
  78 // The L1 cache hit latency is four cycles for floating point loads
  79 // and three cycles for integer loads.
  80 //
  81 // The stwcx. instruction requires both the LRACC and the IRACC
  82 // dispatch stages. It must be issued from DISS0.
  83 //
  84 // All lwarx/stwcx. instructions hold in LRACC if another
  85 // uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
  86 //
  87 // msync (a.k.a. sync) and mbar will hold in LWB until all load/store
  88 // resources are empty. AGEN and CRD are held empty until the msync/mbar
  89 // commits.
  90 //
  91 // Most floating-point instructions, computational and move,
  92 // have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
  93 // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
  94 // loads take 4 cycles (for L1 hit).
  95
  96 //
  97 // This file defines the itinerary class data for the PPC 440 processor.
  98 //
  99 //===----------------------------------------------------------------------===//
 100
 101
 102 def PPC440Itineraries : ProcessorItineraries<
 103   [P440_DISS1, P440_DISS2, P440_FRACC, P440_IRACC, P440_IEXE1, P440_IEXE2,
 104    P440_IWB, P440_LRACC, P440_JEXE1, P440_JEXE2, P440_JWB, P440_AGEN, P440_CRD,
 105    P440_LWB, P440_FEXE1, P440_FEXE2, P440_FEXE3, P440_FEXE4, P440_FEXE5,
 106    P440_FEXE6, P440_FWB, P440_LWARX_Hold],
 107   [P440_GPR_Bypass, P440_FPR_Bypass], [
 108   InstrItinData<IIC_IntSimple,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 109                                  InstrStage<1, [P440_IRACC, P440_LRACC]>,
 110                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
 111                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
 112                                  InstrStage<1, [P440_IWB, P440_JWB]>],
 113                                 [2, 0, 0],
 114                                 [P440_GPR_Bypass,
 115                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
 116   InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 117                                  InstrStage<1, [P440_IRACC, P440_LRACC]>,
 118                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
 119                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
 120                                  InstrStage<1, [P440_IWB, P440_JWB]>],
 121                                 [2, 0, 0],
 122                                 [P440_GPR_Bypass,
 123                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
 124   InstrItinData<IIC_IntISEL,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 125                                  InstrStage<1, [P440_IRACC, P440_LRACC]>,
 126                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
 127                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
 128                                  InstrStage<1, [P440_IWB, P440_JWB]>],
 129                                 [2, 0, 0, 0],
 130                                 [P440_GPR_Bypass,
 131                                  P440_GPR_Bypass, P440_GPR_Bypass, NoBypass]>,
 132   InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 133                                  InstrStage<1, [P440_IRACC, P440_LRACC]>,
 134                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
 135                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
 136                                  InstrStage<1, [P440_IWB, P440_JWB]>],
 137                                 [2, 0, 0],
 138                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 139   InstrItinData<IIC_IntDivW,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 140                                  InstrStage<1, [P440_IRACC]>,
 141                                  InstrStage<1, [P440_IEXE1]>,
 142                                  InstrStage<1, [P440_IEXE2]>,
 143                                  InstrStage<33, [P440_IWB]>],
 144                                 [36, 0, 0],
 145                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 146   InstrItinData<IIC_IntMFFS,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 147                                  InstrStage<1, [P440_IRACC]>,
 148                                  InstrStage<1, [P440_IEXE1]>,
 149                                  InstrStage<1, [P440_IEXE2]>,
 150                                  InstrStage<1, [P440_IWB]>],
 151                                 [3, 0, 0],
 152                                 [P440_GPR_Bypass,
 153                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
 154   InstrItinData<IIC_IntMTFSB0,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 155                                  InstrStage<1, [P440_IRACC]>,
 156                                  InstrStage<1, [P440_IEXE1]>,
 157                                  InstrStage<1, [P440_IEXE2]>,
 158                                  InstrStage<1, [P440_IWB]>],
 159                                 [3, 0, 0],
 160                                 [P440_GPR_Bypass,
 161                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
 162   InstrItinData<IIC_IntMulHW,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 163                                  InstrStage<1, [P440_IRACC]>,
 164                                  InstrStage<1, [P440_IEXE1]>,
 165                                  InstrStage<1, [P440_IEXE2]>,
 166                                  InstrStage<1, [P440_IWB]>],
 167                                 [4, 0, 0],
 168                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 169   InstrItinData<IIC_IntMulHWU,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 170                                  InstrStage<1, [P440_IRACC]>,
 171                                  InstrStage<1, [P440_IEXE1]>,
 172                                  InstrStage<1, [P440_IEXE2]>,
 173                                  InstrStage<1, [P440_IWB]>],
 174                                 [4, 0, 0],
 175                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 176   InstrItinData<IIC_IntMulLI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 177                                  InstrStage<1, [P440_IRACC]>,
 178                                  InstrStage<1, [P440_IEXE1]>,
 179                                  InstrStage<1, [P440_IEXE2]>,
 180                                  InstrStage<1, [P440_IWB]>],
 181                                 [4, 0, 0],
 182                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 183   InstrItinData<IIC_IntRotate,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 184                                  InstrStage<1, [P440_IRACC, P440_LRACC]>,
 185                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
 186                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
 187                                  InstrStage<1, [P440_IWB, P440_JWB]>],
 188                                 [2, 0, 0],
 189                                 [P440_GPR_Bypass,
 190                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
 191   InstrItinData<IIC_IntShift,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 192                                  InstrStage<1, [P440_IRACC, P440_LRACC]>,
 193                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
 194                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
 195                                  InstrStage<1, [P440_IWB, P440_JWB]>],
 196                                 [2, 0, 0],
 197                                 [P440_GPR_Bypass,
 198                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
 199   InstrItinData<IIC_IntTrapW,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 200                                  InstrStage<1, [P440_IRACC]>,
 201                                  InstrStage<1, [P440_IEXE1]>,
 202                                  InstrStage<1, [P440_IEXE2]>,
 203                                  InstrStage<1, [P440_IWB]>],
 204                                 [2, 0],
 205                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
 206   InstrItinData<IIC_BrB,        [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 207                                  InstrStage<1, [P440_IRACC]>,
 208                                  InstrStage<1, [P440_IEXE1]>,
 209                                  InstrStage<1, [P440_IEXE2]>,
 210                                  InstrStage<1, [P440_IWB]>],
 211                                 [4, 0],
 212                                 [NoBypass, P440_GPR_Bypass]>,
 213   InstrItinData<IIC_BrCR,       [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 214                                  InstrStage<1, [P440_IRACC]>,
 215                                  InstrStage<1, [P440_IEXE1]>,
 216                                  InstrStage<1, [P440_IEXE2]>,
 217                                  InstrStage<1, [P440_IWB]>],
 218                                 [4, 0, 0],
 219                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 220   InstrItinData<IIC_BrMCR,      [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 221                                  InstrStage<1, [P440_IRACC]>,
 222                                  InstrStage<1, [P440_IEXE1]>,
 223                                  InstrStage<1, [P440_IEXE2]>,
 224                                  InstrStage<1, [P440_IWB]>],
 225                                 [4, 0, 0],
 226                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 227   InstrItinData<IIC_BrMCRX,     [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 228                                  InstrStage<1, [P440_IRACC]>,
 229                                  InstrStage<1, [P440_IEXE1]>,
 230                                  InstrStage<1, [P440_IEXE2]>,
 231                                  InstrStage<1, [P440_IWB]>],
 232                                 [4, 0, 0],
 233                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 234   InstrItinData<IIC_LdStDCBA,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 235                                  InstrStage<1, [P440_LRACC]>,
 236                                  InstrStage<1, [P440_AGEN]>,
 237                                  InstrStage<1, [P440_CRD]>,
 238                                  InstrStage<1, [P440_LWB]>],
 239                                 [1, 1],
 240                                 [NoBypass, P440_GPR_Bypass]>,
 241   InstrItinData<IIC_LdStDCBF,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 242                                  InstrStage<1, [P440_LRACC]>,
 243                                  InstrStage<1, [P440_AGEN]>,
 244                                  InstrStage<1, [P440_CRD]>,
 245                                  InstrStage<1, [P440_LWB]>],
 246                                 [1, 1],
 247                                 [NoBypass, P440_GPR_Bypass]>,
 248   InstrItinData<IIC_LdStDCBI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 249                                  InstrStage<1, [P440_LRACC]>,
 250                                  InstrStage<1, [P440_AGEN]>,
 251                                  InstrStage<1, [P440_CRD]>,
 252                                  InstrStage<1, [P440_LWB]>],
 253                                 [1, 1],
 254                                 [NoBypass, P440_GPR_Bypass]>,
 255   InstrItinData<IIC_LdStLoad,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 256                                  InstrStage<1, [P440_LRACC]>,
 257                                  InstrStage<1, [P440_AGEN]>,
 258                                  InstrStage<1, [P440_CRD]>,
 259                                  InstrStage<2, [P440_LWB]>],
 260                                 [5, 1, 1],
 261                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
 262   InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
 263                                  InstrStage<1, [P440_LRACC]>,
 264                                  InstrStage<1, [P440_AGEN]>,
 265                                  InstrStage<1, [P440_CRD]>,
 266                                  InstrStage<2, [P440_LWB]>],
 267                                 [5, 2, 1, 1],
 268                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
 269   InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
 270                                  InstrStage<1, [P440_LRACC]>,
 271                                  InstrStage<1, [P440_AGEN]>,
 272                                  InstrStage<1, [P440_CRD]>,
 273                                  InstrStage<2, [P440_LWB]>],
 274                                 [5, 2, 1, 1],
 275                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
 276   InstrItinData<IIC_LdStStore,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 277                                  InstrStage<1, [P440_LRACC]>,
 278                                  InstrStage<1, [P440_AGEN]>,
 279                                  InstrStage<1, [P440_CRD]>,
 280                                  InstrStage<2, [P440_LWB]>],
 281                                 [1, 1, 1],
 282                                 [NoBypass, P440_GPR_Bypass]>,
 283   InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
 284                                  InstrStage<1, [P440_LRACC]>,
 285                                  InstrStage<1, [P440_AGEN]>,
 286                                  InstrStage<1, [P440_CRD]>,
 287                                  InstrStage<2, [P440_LWB]>],
 288                                 [2, 1, 1, 1],
 289                                 [NoBypass, P440_GPR_Bypass]>,
 290   InstrItinData<IIC_LdStICBI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 291                                  InstrStage<1, [P440_LRACC]>,
 292                                  InstrStage<1, [P440_AGEN]>,
 293                                  InstrStage<1, [P440_CRD]>,
 294                                  InstrStage<1, [P440_LWB]>],
 295                                 [4, 1, 1],
 296                                 [NoBypass, P440_GPR_Bypass]>,
 297   InstrItinData<IIC_LdStSTFD,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 298                                  InstrStage<1, [P440_LRACC]>,
 299                                  InstrStage<1, [P440_AGEN]>,
 300                                  InstrStage<1, [P440_CRD]>,
 301                                  InstrStage<1, [P440_LWB]>],
 302                                 [1, 1, 1],
 303                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 304   InstrItinData<IIC_LdStSTFDU,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 305                                  InstrStage<1, [P440_LRACC]>,
 306                                  InstrStage<1, [P440_AGEN]>,
 307                                  InstrStage<1, [P440_CRD]>,
 308                                  InstrStage<1, [P440_LWB]>],
 309                                 [2, 1, 1, 1],
 310                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 311   InstrItinData<IIC_LdStLFD,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 312                                  InstrStage<1, [P440_LRACC]>,
 313                                  InstrStage<1, [P440_AGEN]>,
 314                                  InstrStage<1, [P440_CRD]>,
 315                                  InstrStage<2, [P440_LWB]>],
 316                                 [5, 1, 1],
 317                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 318   InstrItinData<IIC_LdStLFDU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 319                                  InstrStage<1, [P440_LRACC]>,
 320                                  InstrStage<1, [P440_AGEN]>,
 321                                  InstrStage<1, [P440_CRD]>,
 322                                  InstrStage<1, [P440_LWB]>],
 323                                 [5, 2, 1, 1],
 324                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 325   InstrItinData<IIC_LdStLFDUX,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 326                                  InstrStage<1, [P440_LRACC]>,
 327                                  InstrStage<1, [P440_AGEN]>,
 328                                  InstrStage<1, [P440_CRD]>,
 329                                  InstrStage<1, [P440_LWB]>],
 330                                 [5, 2, 1, 1],
 331                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
 332   InstrItinData<IIC_LdStLHA,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 333                                  InstrStage<1, [P440_LRACC]>,
 334                                  InstrStage<1, [P440_AGEN]>,
 335                                  InstrStage<1, [P440_CRD]>,
 336                                  InstrStage<1, [P440_LWB]>],
 337                                 [4, 1, 1],
 338                                 [NoBypass, P440_GPR_Bypass]>,
 339   InstrItinData<IIC_LdStLHAU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 340                                  InstrStage<1, [P440_LRACC]>,
 341                                  InstrStage<1, [P440_AGEN]>,
 342                                  InstrStage<1, [P440_CRD]>,
 343                                  InstrStage<1, [P440_LWB]>],
 344                                 [4, 1, 1],
 345                                 [NoBypass, P440_GPR_Bypass]>,
 346   InstrItinData<IIC_LdStLHAUX,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 347                                  InstrStage<1, [P440_LRACC]>,
 348                                  InstrStage<1, [P440_AGEN]>,
 349                                  InstrStage<1, [P440_CRD]>,
 350                                  InstrStage<1, [P440_LWB]>],
 351                                 [4, 1, 1],
 352                                 [NoBypass, P440_GPR_Bypass]>,
 353   InstrItinData<IIC_LdStLMW,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 354                                  InstrStage<1, [P440_LRACC]>,
 355                                  InstrStage<1, [P440_AGEN]>,
 356                                  InstrStage<1, [P440_CRD]>,
 357                                  InstrStage<1, [P440_LWB]>],
 358                                 [4, 1, 1],
 359                                 [NoBypass, P440_GPR_Bypass]>,
 360   InstrItinData<IIC_LdStLWARX,  [InstrStage<1, [P440_DISS1]>,
 361                                  InstrStage<1, [P440_IRACC], 0>,
 362                                  InstrStage<4, [P440_LWARX_Hold], 0>,
 363                                  InstrStage<1, [P440_LRACC]>,
 364                                  InstrStage<1, [P440_AGEN]>,
 365                                  InstrStage<1, [P440_CRD]>,
 366                                  InstrStage<1, [P440_LWB]>],
 367                                 [4, 1, 1],
 368                                 [NoBypass, P440_GPR_Bypass]>,
 369   InstrItinData<IIC_LdStSTD,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 370                                  InstrStage<1, [P440_LRACC]>,
 371                                  InstrStage<1, [P440_AGEN]>,
 372                                  InstrStage<1, [P440_CRD]>,
 373                                  InstrStage<2, [P440_LWB]>],
 374                                 [4, 1, 1],
 375                                 [NoBypass, P440_GPR_Bypass]>,
 376   InstrItinData<IIC_LdStSTDU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 377                                  InstrStage<1, [P440_LRACC]>,
 378                                  InstrStage<1, [P440_AGEN]>,
 379                                  InstrStage<1, [P440_CRD]>,
 380                                  InstrStage<2, [P440_LWB]>],
 381                                 [2, 1, 1, 1],
 382                                 [NoBypass, P440_GPR_Bypass]>,
 383   InstrItinData<IIC_LdStSTDUX,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 384                                  InstrStage<1, [P440_LRACC]>,
 385                                  InstrStage<1, [P440_AGEN]>,
 386                                  InstrStage<1, [P440_CRD]>,
 387                                  InstrStage<2, [P440_LWB]>],
 388                                 [2, 1, 1, 1],
 389                                 [NoBypass, P440_GPR_Bypass]>,
 390   InstrItinData<IIC_LdStSTDCX,  [InstrStage<1, [P440_DISS1]>,
 391                                  InstrStage<1, [P440_IRACC], 0>,
 392                                  InstrStage<4, [P440_LWARX_Hold], 0>,
 393                                  InstrStage<1, [P440_LRACC]>,
 394                                  InstrStage<1, [P440_AGEN]>,
 395                                  InstrStage<1, [P440_CRD]>,
 396                                  InstrStage<1, [P440_LWB]>],
 397                                 [4, 1, 1],
 398                                 [NoBypass, P440_GPR_Bypass]>,
 399   InstrItinData<IIC_LdStSTWCX,  [InstrStage<1, [P440_DISS1]>,
 400                                  InstrStage<1, [P440_IRACC], 0>,
 401                                  InstrStage<4, [P440_LWARX_Hold], 0>,
 402                                  InstrStage<1, [P440_LRACC]>,
 403                                  InstrStage<1, [P440_AGEN]>,
 404                                  InstrStage<1, [P440_CRD]>,
 405                                  InstrStage<1, [P440_LWB]>],
 406                                 [4, 1, 1],
 407                                 [NoBypass, P440_GPR_Bypass]>,
 408   InstrItinData<IIC_LdStSync,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 409                                  InstrStage<1, [P440_LRACC]>,
 410                                  InstrStage<3, [P440_AGEN], 1>,
 411                                  InstrStage<2, [P440_CRD],  1>,
 412                                  InstrStage<1, [P440_LWB]>]>,
 413   InstrItinData<IIC_SprISYNC,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 414                                  InstrStage<1, [P440_FRACC], 0>,
 415                                  InstrStage<1, [P440_LRACC], 0>,
 416                                  InstrStage<1, [P440_IRACC]>,
 417                                  InstrStage<1, [P440_FEXE1], 0>,
 418                                  InstrStage<1, [P440_AGEN],  0>,
 419                                  InstrStage<1, [P440_JEXE1], 0>,
 420                                  InstrStage<1, [P440_IEXE1]>,
 421                                  InstrStage<1, [P440_FEXE2], 0>,
 422                                  InstrStage<1, [P440_CRD],   0>,
 423                                  InstrStage<1, [P440_JEXE2], 0>,
 424                                  InstrStage<1, [P440_IEXE2]>,
 425                                  InstrStage<6, [P440_FEXE3], 0>,
 426                                  InstrStage<6, [P440_LWB],   0>,
 427                                  InstrStage<6, [P440_JWB],   0>,
 428                                  InstrStage<6, [P440_IWB]>]>,
 429   InstrItinData<IIC_SprMFSR,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 430                                  InstrStage<1, [P440_IRACC]>,
 431                                  InstrStage<1, [P440_IEXE1]>,
 432                                  InstrStage<1, [P440_IEXE2]>,
 433                                  InstrStage<1, [P440_IWB]>],
 434                                 [2, 0],
 435                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
 436   InstrItinData<IIC_SprMTMSR,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 437                                  InstrStage<1, [P440_IRACC]>,
 438                                  InstrStage<1, [P440_IEXE1]>,
 439                                  InstrStage<1, [P440_IEXE2]>,
 440                                  InstrStage<1, [P440_IWB]>],
 441                                 [2, 0],
 442                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
 443   InstrItinData<IIC_SprMTSR,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 444                                  InstrStage<1, [P440_IRACC]>,
 445                                  InstrStage<1, [P440_IEXE1]>,
 446                                  InstrStage<1, [P440_IEXE2]>,
 447                                  InstrStage<3, [P440_IWB]>],
 448                                 [5, 0],
 449                                 [NoBypass, P440_GPR_Bypass]>,
 450   InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 451                                  InstrStage<1, [P440_IRACC]>,
 452                                  InstrStage<1, [P440_IEXE1]>,
 453                                  InstrStage<1, [P440_IEXE2]>,
 454                                  InstrStage<1, [P440_IWB]>]>,
 455   InstrItinData<IIC_SprMFCR,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 456                                  InstrStage<1, [P440_IRACC]>,
 457                                  InstrStage<1, [P440_IEXE1]>,
 458                                  InstrStage<1, [P440_IEXE2]>,
 459                                  InstrStage<1, [P440_IWB]>],
 460                                 [4, 0],
 461                                 [NoBypass, P440_GPR_Bypass]>,
 462   InstrItinData<IIC_SprMFMSR,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 463                                  InstrStage<1, [P440_IRACC]>,
 464                                  InstrStage<1, [P440_IEXE1]>,
 465                                  InstrStage<1, [P440_IEXE2]>,
 466                                  InstrStage<1, [P440_IWB]>],
 467                                 [3, 0],
 468                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
 469   InstrItinData<IIC_SprMFSPR,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 470                                  InstrStage<1, [P440_IRACC]>,
 471                                  InstrStage<1, [P440_IEXE1]>,
 472                                  InstrStage<1, [P440_IEXE2]>,
 473                                  InstrStage<3, [P440_IWB]>],
 474                                 [6, 0],
 475                                 [NoBypass, P440_GPR_Bypass]>,
 476   InstrItinData<IIC_SprMFTB,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 477                                  InstrStage<1, [P440_IRACC]>,
 478                                  InstrStage<1, [P440_IEXE1]>,
 479                                  InstrStage<1, [P440_IEXE2]>,
 480                                  InstrStage<3, [P440_IWB]>],
 481                                 [6, 0],
 482                                 [NoBypass, P440_GPR_Bypass]>,
 483   InstrItinData<IIC_SprMTSPR,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 484                                  InstrStage<1, [P440_IRACC]>,
 485                                  InstrStage<1, [P440_IEXE1]>,
 486                                  InstrStage<1, [P440_IEXE2]>,
 487                                  InstrStage<3, [P440_IWB]>],
 488                                 [6, 0],
 489                                 [NoBypass, P440_GPR_Bypass]>,
 490   InstrItinData<IIC_SprMTSRIN,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 491                                  InstrStage<1, [P440_IRACC]>,
 492                                  InstrStage<1, [P440_IEXE1]>,
 493                                  InstrStage<1, [P440_IEXE2]>,
 494                                  InstrStage<3, [P440_IWB]>],
 495                                 [6, 0],
 496                                 [NoBypass, P440_GPR_Bypass]>,
 497   InstrItinData<IIC_SprRFI,     [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 498                                  InstrStage<1, [P440_IRACC]>,
 499                                  InstrStage<1, [P440_IEXE1]>,
 500                                  InstrStage<1, [P440_IEXE2]>,
 501                                  InstrStage<1, [P440_IWB]>],
 502                                 [4, 0],
 503                                 [NoBypass, P440_GPR_Bypass]>,
 504   InstrItinData<IIC_SprSC,      [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 505                                  InstrStage<1, [P440_IRACC]>,
 506                                  InstrStage<1, [P440_IEXE1]>,
 507                                  InstrStage<1, [P440_IEXE2]>,
 508                                  InstrStage<1, [P440_IWB]>],
 509                                 [4, 0],
 510                                 [NoBypass, P440_GPR_Bypass]>,
 511   InstrItinData<IIC_FPGeneral,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 512                                  InstrStage<1, [P440_FRACC]>,
 513                                  InstrStage<1, [P440_FEXE1]>,
 514                                  InstrStage<1, [P440_FEXE2]>,
 515                                  InstrStage<1, [P440_FEXE3]>,
 516                                  InstrStage<1, [P440_FEXE4]>,
 517                                  InstrStage<1, [P440_FEXE5]>,
 518                                  InstrStage<1, [P440_FEXE6]>,
 519                                  InstrStage<1, [P440_FWB]>],
 520                                 [6, 0, 0],
 521                                 [P440_FPR_Bypass,
 522                                  P440_FPR_Bypass, P440_FPR_Bypass]>,
 523   InstrItinData<IIC_FPAddSub,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 524                                  InstrStage<1, [P440_FRACC]>,
 525                                  InstrStage<1, [P440_FEXE1]>,
 526                                  InstrStage<1, [P440_FEXE2]>,
 527                                  InstrStage<1, [P440_FEXE3]>,
 528                                  InstrStage<1, [P440_FEXE4]>,
 529                                  InstrStage<1, [P440_FEXE5]>,
 530                                  InstrStage<1, [P440_FEXE6]>,
 531                                  InstrStage<1, [P440_FWB]>],
 532                                 [6, 0, 0],
 533                                 [P440_FPR_Bypass,
 534                                  P440_FPR_Bypass, P440_FPR_Bypass]>,
 535   InstrItinData<IIC_FPCompare,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 536                                  InstrStage<1, [P440_FRACC]>,
 537                                  InstrStage<1, [P440_FEXE1]>,
 538                                  InstrStage<1, [P440_FEXE2]>,
 539                                  InstrStage<1, [P440_FEXE3]>,
 540                                  InstrStage<1, [P440_FEXE4]>,
 541                                  InstrStage<1, [P440_FEXE5]>,
 542                                  InstrStage<1, [P440_FEXE6]>,
 543                                  InstrStage<1, [P440_FWB]>],
 544                                 [6, 0, 0],
 545                                 [P440_FPR_Bypass, P440_FPR_Bypass,
 546                                  P440_FPR_Bypass]>,
 547   InstrItinData<IIC_FPDivD,     [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 548                                  InstrStage<1, [P440_FRACC]>,
 549                                  InstrStage<1, [P440_FEXE1]>,
 550                                  InstrStage<1, [P440_FEXE2]>,
 551                                  InstrStage<1, [P440_FEXE3]>,
 552                                  InstrStage<1, [P440_FEXE4]>,
 553                                  InstrStage<1, [P440_FEXE5]>,
 554                                  InstrStage<1, [P440_FEXE6]>,
 555                                  InstrStage<25, [P440_FWB]>],
 556                                 [31, 0, 0],
 557                                 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
 558   InstrItinData<IIC_FPDivS,     [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 559                                  InstrStage<1, [P440_FRACC]>,
 560                                  InstrStage<1, [P440_FEXE1]>,
 561                                  InstrStage<1, [P440_FEXE2]>,
 562                                  InstrStage<1, [P440_FEXE3]>,
 563                                  InstrStage<1, [P440_FEXE4]>,
 564                                  InstrStage<1, [P440_FEXE5]>,
 565                                  InstrStage<1, [P440_FEXE6]>,
 566                                  InstrStage<13, [P440_FWB]>],
 567                                 [19, 0, 0],
 568                                 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
 569   InstrItinData<IIC_FPFused,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 570                                  InstrStage<1, [P440_FRACC]>,
 571                                  InstrStage<1, [P440_FEXE1]>,
 572                                  InstrStage<1, [P440_FEXE2]>,
 573                                  InstrStage<1, [P440_FEXE3]>,
 574                                  InstrStage<1, [P440_FEXE4]>,
 575                                  InstrStage<1, [P440_FEXE5]>,
 576                                  InstrStage<1, [P440_FEXE6]>,
 577                                  InstrStage<1, [P440_FWB]>],
 578                                 [6, 0, 0, 0],
 579                                 [P440_FPR_Bypass,
 580                                  P440_FPR_Bypass, P440_FPR_Bypass,
 581                                  P440_FPR_Bypass]>,
 582   InstrItinData<IIC_FPRes,      [InstrStage<1, [P440_DISS1, P440_DISS2]>,
 583                                  InstrStage<1, [P440_FRACC]>,
 584                                  InstrStage<1, [P440_FEXE1]>,
 585                                  InstrStage<1, [P440_FEXE2]>,
 586                                  InstrStage<1, [P440_FEXE3]>,
 587                                  InstrStage<1, [P440_FEXE4]>,
 588                                  InstrStage<1, [P440_FEXE5]>,
 589                                  InstrStage<1, [P440_FEXE6]>,
 590                                  InstrStage<1, [P440_FWB]>],
 591                                 [6, 0],
 592                                 [P440_FPR_Bypass, P440_FPR_Bypass]>
 593 ]>;
 594
 595 // ===---------------------------------------------------------------------===//
 596 // PPC440 machine model for scheduling and other instruction cost heuristics.
 597
 598 def PPC440Model : SchedMachineModel {
 599   let IssueWidth = 2;  // 2 instructions are dispatched per cycle.
 600   let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
 601   let LoadLatency = 5; // Optimistic load latency assuming bypass.
 602                        // This is overriden by OperandCycles if the
 603                        // Itineraries are queried instead.
 604
 605   let Itineraries = PPC440Itineraries;
 606 }
 607