1 //===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the VSX extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 // *********************************** NOTE ***********************************
15 // ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **
16 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
17 // ** A lane-sensitive instruction relies, implicitly or explicitly, on **
18 // ** whether lanes are numbered from left to right. An instruction like **
19 // ** VADDFP is not lane-sensitive, because each lane of the result vector **
20 // ** relies only on the corresponding lane of the source vectors. However, **
21 // ** an instruction like VMULESB is lane-sensitive, because "even" and **
22 // ** "odd" lanes are different for big-endian and little-endian numbering. **
24 // ** When adding new VMX and VSX instructions, please consider whether they **
25 // ** are lane-sensitive. If so, they must be added to a switch statement **
26 // ** in PPCVSXSwapRemoval::gatherVectorInstructions(). **
27 // ****************************************************************************
29 def PPCRegVSRCAsmOperand : AsmOperandClass {
30 let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber";
32 def vsrc : RegisterOperand<VSRC> {
33 let ParserMatchClass = PPCRegVSRCAsmOperand;
36 def PPCRegVSFRCAsmOperand : AsmOperandClass {
37 let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber";
39 def vsfrc : RegisterOperand<VSFRC> {
40 let ParserMatchClass = PPCRegVSFRCAsmOperand;
43 // Little-endian-specific nodes.
44 def SDT_PPClxvd2x : SDTypeProfile<1, 1, [
45 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
47 def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [
48 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
50 def SDT_PPCxxswapd : SDTypeProfile<1, 1, [
54 def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
55 [SDNPHasChain, SDNPMayLoad]>;
56 def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
57 [SDNPHasChain, SDNPMayStore]>;
58 def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
59 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
60 def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;
61 def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>;
63 multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, dag OOL, dag IOL,
64 string asmbase, string asmstr, InstrItinClass itin,
66 let BaseName = asmbase in {
67 def NAME : XX3Form_Rc<opcode, xo, OOL, IOL,
68 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
71 def o : XX3Form_Rc<opcode, xo, OOL, IOL,
72 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
77 def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;
78 def IsLittleEndian : Predicate<"PPCSubTarget->isLittleEndian()">;
79 def IsBigEndian : Predicate<"!PPCSubTarget->isLittleEndian()">;
81 let Predicates = [HasVSX] in {
82 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
83 let hasSideEffects = 0 in { // VSX instructions don't have side effects.
86 // Load indexed instructions
88 def LXSDX : XX1Form<31, 588,
89 (outs vsfrc:$XT), (ins memrr:$src),
90 "lxsdx $XT, $src", IIC_LdStLFD,
91 [(set f64:$XT, (load xoaddr:$src))]>;
93 def LXVD2X : XX1Form<31, 844,
94 (outs vsrc:$XT), (ins memrr:$src),
95 "lxvd2x $XT, $src", IIC_LdStLFD,
96 [(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>;
98 def LXVDSX : XX1Form<31, 332,
99 (outs vsrc:$XT), (ins memrr:$src),
100 "lxvdsx $XT, $src", IIC_LdStLFD, []>;
102 def LXVW4X : XX1Form<31, 780,
103 (outs vsrc:$XT), (ins memrr:$src),
104 "lxvw4x $XT, $src", IIC_LdStLFD,
105 [(set v4i32:$XT, (int_ppc_vsx_lxvw4x xoaddr:$src))]>;
108 // Store indexed instructions
109 let mayStore = 1 in {
110 def STXSDX : XX1Form<31, 716,
111 (outs), (ins vsfrc:$XT, memrr:$dst),
112 "stxsdx $XT, $dst", IIC_LdStSTFD,
113 [(store f64:$XT, xoaddr:$dst)]>;
115 def STXVD2X : XX1Form<31, 972,
116 (outs), (ins vsrc:$XT, memrr:$dst),
117 "stxvd2x $XT, $dst", IIC_LdStSTFD,
118 [(store v2f64:$XT, xoaddr:$dst)]>;
120 def STXVW4X : XX1Form<31, 908,
121 (outs), (ins vsrc:$XT, memrr:$dst),
122 "stxvw4x $XT, $dst", IIC_LdStSTFD,
123 [(store v4i32:$XT, xoaddr:$dst)]>;
126 // Add/Mul Instructions
127 let isCommutable = 1 in {
128 def XSADDDP : XX3Form<60, 32,
129 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
130 "xsadddp $XT, $XA, $XB", IIC_VecFP,
131 [(set f64:$XT, (fadd f64:$XA, f64:$XB))]>;
132 def XSMULDP : XX3Form<60, 48,
133 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
134 "xsmuldp $XT, $XA, $XB", IIC_VecFP,
135 [(set f64:$XT, (fmul f64:$XA, f64:$XB))]>;
137 def XVADDDP : XX3Form<60, 96,
138 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
139 "xvadddp $XT, $XA, $XB", IIC_VecFP,
140 [(set v2f64:$XT, (fadd v2f64:$XA, v2f64:$XB))]>;
142 def XVADDSP : XX3Form<60, 64,
143 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
144 "xvaddsp $XT, $XA, $XB", IIC_VecFP,
145 [(set v4f32:$XT, (fadd v4f32:$XA, v4f32:$XB))]>;
147 def XVMULDP : XX3Form<60, 112,
148 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
149 "xvmuldp $XT, $XA, $XB", IIC_VecFP,
150 [(set v2f64:$XT, (fmul v2f64:$XA, v2f64:$XB))]>;
152 def XVMULSP : XX3Form<60, 80,
153 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
154 "xvmulsp $XT, $XA, $XB", IIC_VecFP,
155 [(set v4f32:$XT, (fmul v4f32:$XA, v4f32:$XB))]>;
158 // Subtract Instructions
159 def XSSUBDP : XX3Form<60, 40,
160 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
161 "xssubdp $XT, $XA, $XB", IIC_VecFP,
162 [(set f64:$XT, (fsub f64:$XA, f64:$XB))]>;
164 def XVSUBDP : XX3Form<60, 104,
165 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
166 "xvsubdp $XT, $XA, $XB", IIC_VecFP,
167 [(set v2f64:$XT, (fsub v2f64:$XA, v2f64:$XB))]>;
168 def XVSUBSP : XX3Form<60, 72,
169 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
170 "xvsubsp $XT, $XA, $XB", IIC_VecFP,
171 [(set v4f32:$XT, (fsub v4f32:$XA, v4f32:$XB))]>;
174 let BaseName = "XSMADDADP" in {
175 let isCommutable = 1 in
176 def XSMADDADP : XX3Form<60, 33,
177 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
178 "xsmaddadp $XT, $XA, $XB", IIC_VecFP,
179 [(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>,
180 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
182 let IsVSXFMAAlt = 1 in
183 def XSMADDMDP : XX3Form<60, 41,
184 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
185 "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
186 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
190 let BaseName = "XSMSUBADP" in {
191 let isCommutable = 1 in
192 def XSMSUBADP : XX3Form<60, 49,
193 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
194 "xsmsubadp $XT, $XA, $XB", IIC_VecFP,
195 [(set f64:$XT, (fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
196 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
198 let IsVSXFMAAlt = 1 in
199 def XSMSUBMDP : XX3Form<60, 57,
200 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
201 "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
202 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
206 let BaseName = "XSNMADDADP" in {
207 let isCommutable = 1 in
208 def XSNMADDADP : XX3Form<60, 161,
209 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
210 "xsnmaddadp $XT, $XA, $XB", IIC_VecFP,
211 [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, f64:$XTi)))]>,
212 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
214 let IsVSXFMAAlt = 1 in
215 def XSNMADDMDP : XX3Form<60, 169,
216 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
217 "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
218 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
222 let BaseName = "XSNMSUBADP" in {
223 let isCommutable = 1 in
224 def XSNMSUBADP : XX3Form<60, 177,
225 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
226 "xsnmsubadp $XT, $XA, $XB", IIC_VecFP,
227 [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
228 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
230 let IsVSXFMAAlt = 1 in
231 def XSNMSUBMDP : XX3Form<60, 185,
232 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
233 "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
234 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
238 let BaseName = "XVMADDADP" in {
239 let isCommutable = 1 in
240 def XVMADDADP : XX3Form<60, 97,
241 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
242 "xvmaddadp $XT, $XA, $XB", IIC_VecFP,
243 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
244 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
246 let IsVSXFMAAlt = 1 in
247 def XVMADDMDP : XX3Form<60, 105,
248 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
249 "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
250 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
254 let BaseName = "XVMADDASP" in {
255 let isCommutable = 1 in
256 def XVMADDASP : XX3Form<60, 65,
257 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
258 "xvmaddasp $XT, $XA, $XB", IIC_VecFP,
259 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
260 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
262 let IsVSXFMAAlt = 1 in
263 def XVMADDMSP : XX3Form<60, 73,
264 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
265 "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
266 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
270 let BaseName = "XVMSUBADP" in {
271 let isCommutable = 1 in
272 def XVMSUBADP : XX3Form<60, 113,
273 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
274 "xvmsubadp $XT, $XA, $XB", IIC_VecFP,
275 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
276 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
278 let IsVSXFMAAlt = 1 in
279 def XVMSUBMDP : XX3Form<60, 121,
280 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
281 "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
282 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
286 let BaseName = "XVMSUBASP" in {
287 let isCommutable = 1 in
288 def XVMSUBASP : XX3Form<60, 81,
289 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
290 "xvmsubasp $XT, $XA, $XB", IIC_VecFP,
291 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
292 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
294 let IsVSXFMAAlt = 1 in
295 def XVMSUBMSP : XX3Form<60, 89,
296 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
297 "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
298 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
302 let BaseName = "XVNMADDADP" in {
303 let isCommutable = 1 in
304 def XVNMADDADP : XX3Form<60, 225,
305 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
306 "xvnmaddadp $XT, $XA, $XB", IIC_VecFP,
307 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
308 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
310 let IsVSXFMAAlt = 1 in
311 def XVNMADDMDP : XX3Form<60, 233,
312 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
313 "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
314 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
318 let BaseName = "XVNMADDASP" in {
319 let isCommutable = 1 in
320 def XVNMADDASP : XX3Form<60, 193,
321 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
322 "xvnmaddasp $XT, $XA, $XB", IIC_VecFP,
323 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
324 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
326 let IsVSXFMAAlt = 1 in
327 def XVNMADDMSP : XX3Form<60, 201,
328 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
329 "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
330 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
334 let BaseName = "XVNMSUBADP" in {
335 let isCommutable = 1 in
336 def XVNMSUBADP : XX3Form<60, 241,
337 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
338 "xvnmsubadp $XT, $XA, $XB", IIC_VecFP,
339 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
340 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
342 let IsVSXFMAAlt = 1 in
343 def XVNMSUBMDP : XX3Form<60, 249,
344 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
345 "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
346 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
350 let BaseName = "XVNMSUBASP" in {
351 let isCommutable = 1 in
352 def XVNMSUBASP : XX3Form<60, 209,
353 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
354 "xvnmsubasp $XT, $XA, $XB", IIC_VecFP,
355 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
356 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
358 let IsVSXFMAAlt = 1 in
359 def XVNMSUBMSP : XX3Form<60, 217,
360 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
361 "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
362 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
366 // Division Instructions
367 def XSDIVDP : XX3Form<60, 56,
368 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
369 "xsdivdp $XT, $XA, $XB", IIC_FPDivD,
370 [(set f64:$XT, (fdiv f64:$XA, f64:$XB))]>;
371 def XSSQRTDP : XX2Form<60, 75,
372 (outs vsfrc:$XT), (ins vsfrc:$XB),
373 "xssqrtdp $XT, $XB", IIC_FPSqrtD,
374 [(set f64:$XT, (fsqrt f64:$XB))]>;
376 def XSREDP : XX2Form<60, 90,
377 (outs vsfrc:$XT), (ins vsfrc:$XB),
378 "xsredp $XT, $XB", IIC_VecFP,
379 [(set f64:$XT, (PPCfre f64:$XB))]>;
380 def XSRSQRTEDP : XX2Form<60, 74,
381 (outs vsfrc:$XT), (ins vsfrc:$XB),
382 "xsrsqrtedp $XT, $XB", IIC_VecFP,
383 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
385 def XSTDIVDP : XX3Form_1<60, 61,
386 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
387 "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
388 def XSTSQRTDP : XX2Form_1<60, 106,
389 (outs crrc:$crD), (ins vsfrc:$XB),
390 "xstsqrtdp $crD, $XB", IIC_FPCompare, []>;
392 def XVDIVDP : XX3Form<60, 120,
393 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
394 "xvdivdp $XT, $XA, $XB", IIC_FPDivD,
395 [(set v2f64:$XT, (fdiv v2f64:$XA, v2f64:$XB))]>;
396 def XVDIVSP : XX3Form<60, 88,
397 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
398 "xvdivsp $XT, $XA, $XB", IIC_FPDivS,
399 [(set v4f32:$XT, (fdiv v4f32:$XA, v4f32:$XB))]>;
401 def XVSQRTDP : XX2Form<60, 203,
402 (outs vsrc:$XT), (ins vsrc:$XB),
403 "xvsqrtdp $XT, $XB", IIC_FPSqrtD,
404 [(set v2f64:$XT, (fsqrt v2f64:$XB))]>;
405 def XVSQRTSP : XX2Form<60, 139,
406 (outs vsrc:$XT), (ins vsrc:$XB),
407 "xvsqrtsp $XT, $XB", IIC_FPSqrtS,
408 [(set v4f32:$XT, (fsqrt v4f32:$XB))]>;
410 def XVTDIVDP : XX3Form_1<60, 125,
411 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
412 "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
413 def XVTDIVSP : XX3Form_1<60, 93,
414 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
415 "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>;
417 def XVTSQRTDP : XX2Form_1<60, 234,
418 (outs crrc:$crD), (ins vsrc:$XB),
419 "xvtsqrtdp $crD, $XB", IIC_FPCompare, []>;
420 def XVTSQRTSP : XX2Form_1<60, 170,
421 (outs crrc:$crD), (ins vsrc:$XB),
422 "xvtsqrtsp $crD, $XB", IIC_FPCompare, []>;
424 def XVREDP : XX2Form<60, 218,
425 (outs vsrc:$XT), (ins vsrc:$XB),
426 "xvredp $XT, $XB", IIC_VecFP,
427 [(set v2f64:$XT, (PPCfre v2f64:$XB))]>;
428 def XVRESP : XX2Form<60, 154,
429 (outs vsrc:$XT), (ins vsrc:$XB),
430 "xvresp $XT, $XB", IIC_VecFP,
431 [(set v4f32:$XT, (PPCfre v4f32:$XB))]>;
433 def XVRSQRTEDP : XX2Form<60, 202,
434 (outs vsrc:$XT), (ins vsrc:$XB),
435 "xvrsqrtedp $XT, $XB", IIC_VecFP,
436 [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>;
437 def XVRSQRTESP : XX2Form<60, 138,
438 (outs vsrc:$XT), (ins vsrc:$XB),
439 "xvrsqrtesp $XT, $XB", IIC_VecFP,
440 [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>;
442 // Compare Instructions
443 def XSCMPODP : XX3Form_1<60, 43,
444 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
445 "xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>;
446 def XSCMPUDP : XX3Form_1<60, 35,
447 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
448 "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
450 defm XVCMPEQDP : XX3Form_Rcr<60, 99,
451 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
452 "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
453 defm XVCMPEQSP : XX3Form_Rcr<60, 67,
454 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
455 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
456 defm XVCMPGEDP : XX3Form_Rcr<60, 115,
457 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
458 "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
459 defm XVCMPGESP : XX3Form_Rcr<60, 83,
460 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
461 "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
462 defm XVCMPGTDP : XX3Form_Rcr<60, 107,
463 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
464 "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
465 defm XVCMPGTSP : XX3Form_Rcr<60, 75,
466 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
467 "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
470 def XSABSDP : XX2Form<60, 345,
471 (outs vsfrc:$XT), (ins vsfrc:$XB),
472 "xsabsdp $XT, $XB", IIC_VecFP,
473 [(set f64:$XT, (fabs f64:$XB))]>;
474 def XSNABSDP : XX2Form<60, 361,
475 (outs vsfrc:$XT), (ins vsfrc:$XB),
476 "xsnabsdp $XT, $XB", IIC_VecFP,
477 [(set f64:$XT, (fneg (fabs f64:$XB)))]>;
478 def XSNEGDP : XX2Form<60, 377,
479 (outs vsfrc:$XT), (ins vsfrc:$XB),
480 "xsnegdp $XT, $XB", IIC_VecFP,
481 [(set f64:$XT, (fneg f64:$XB))]>;
482 def XSCPSGNDP : XX3Form<60, 176,
483 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
484 "xscpsgndp $XT, $XA, $XB", IIC_VecFP,
485 [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>;
487 def XVABSDP : XX2Form<60, 473,
488 (outs vsrc:$XT), (ins vsrc:$XB),
489 "xvabsdp $XT, $XB", IIC_VecFP,
490 [(set v2f64:$XT, (fabs v2f64:$XB))]>;
492 def XVABSSP : XX2Form<60, 409,
493 (outs vsrc:$XT), (ins vsrc:$XB),
494 "xvabssp $XT, $XB", IIC_VecFP,
495 [(set v4f32:$XT, (fabs v4f32:$XB))]>;
497 def XVCPSGNDP : XX3Form<60, 240,
498 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
499 "xvcpsgndp $XT, $XA, $XB", IIC_VecFP,
500 [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>;
501 def XVCPSGNSP : XX3Form<60, 208,
502 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
503 "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP,
504 [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>;
506 def XVNABSDP : XX2Form<60, 489,
507 (outs vsrc:$XT), (ins vsrc:$XB),
508 "xvnabsdp $XT, $XB", IIC_VecFP,
509 [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>;
510 def XVNABSSP : XX2Form<60, 425,
511 (outs vsrc:$XT), (ins vsrc:$XB),
512 "xvnabssp $XT, $XB", IIC_VecFP,
513 [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>;
515 def XVNEGDP : XX2Form<60, 505,
516 (outs vsrc:$XT), (ins vsrc:$XB),
517 "xvnegdp $XT, $XB", IIC_VecFP,
518 [(set v2f64:$XT, (fneg v2f64:$XB))]>;
519 def XVNEGSP : XX2Form<60, 441,
520 (outs vsrc:$XT), (ins vsrc:$XB),
521 "xvnegsp $XT, $XB", IIC_VecFP,
522 [(set v4f32:$XT, (fneg v4f32:$XB))]>;
524 // Conversion Instructions
525 def XSCVDPSP : XX2Form<60, 265,
526 (outs vsfrc:$XT), (ins vsfrc:$XB),
527 "xscvdpsp $XT, $XB", IIC_VecFP, []>;
528 def XSCVDPSXDS : XX2Form<60, 344,
529 (outs vsfrc:$XT), (ins vsfrc:$XB),
530 "xscvdpsxds $XT, $XB", IIC_VecFP,
531 [(set f64:$XT, (PPCfctidz f64:$XB))]>;
532 def XSCVDPSXWS : XX2Form<60, 88,
533 (outs vsfrc:$XT), (ins vsfrc:$XB),
534 "xscvdpsxws $XT, $XB", IIC_VecFP,
535 [(set f64:$XT, (PPCfctiwz f64:$XB))]>;
536 def XSCVDPUXDS : XX2Form<60, 328,
537 (outs vsfrc:$XT), (ins vsfrc:$XB),
538 "xscvdpuxds $XT, $XB", IIC_VecFP,
539 [(set f64:$XT, (PPCfctiduz f64:$XB))]>;
540 def XSCVDPUXWS : XX2Form<60, 72,
541 (outs vsfrc:$XT), (ins vsfrc:$XB),
542 "xscvdpuxws $XT, $XB", IIC_VecFP,
543 [(set f64:$XT, (PPCfctiwuz f64:$XB))]>;
544 def XSCVSPDP : XX2Form<60, 329,
545 (outs vsfrc:$XT), (ins vsfrc:$XB),
546 "xscvspdp $XT, $XB", IIC_VecFP, []>;
547 def XSCVSXDDP : XX2Form<60, 376,
548 (outs vsfrc:$XT), (ins vsfrc:$XB),
549 "xscvsxddp $XT, $XB", IIC_VecFP,
550 [(set f64:$XT, (PPCfcfid f64:$XB))]>;
551 def XSCVUXDDP : XX2Form<60, 360,
552 (outs vsfrc:$XT), (ins vsfrc:$XB),
553 "xscvuxddp $XT, $XB", IIC_VecFP,
554 [(set f64:$XT, (PPCfcfidu f64:$XB))]>;
556 def XVCVDPSP : XX2Form<60, 393,
557 (outs vsrc:$XT), (ins vsrc:$XB),
558 "xvcvdpsp $XT, $XB", IIC_VecFP, []>;
559 def XVCVDPSXDS : XX2Form<60, 472,
560 (outs vsrc:$XT), (ins vsrc:$XB),
561 "xvcvdpsxds $XT, $XB", IIC_VecFP,
562 [(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
563 def XVCVDPSXWS : XX2Form<60, 216,
564 (outs vsrc:$XT), (ins vsrc:$XB),
565 "xvcvdpsxws $XT, $XB", IIC_VecFP, []>;
566 def XVCVDPUXDS : XX2Form<60, 456,
567 (outs vsrc:$XT), (ins vsrc:$XB),
568 "xvcvdpuxds $XT, $XB", IIC_VecFP,
569 [(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
570 def XVCVDPUXWS : XX2Form<60, 200,
571 (outs vsrc:$XT), (ins vsrc:$XB),
572 "xvcvdpuxws $XT, $XB", IIC_VecFP, []>;
574 def XVCVSPDP : XX2Form<60, 457,
575 (outs vsrc:$XT), (ins vsrc:$XB),
576 "xvcvspdp $XT, $XB", IIC_VecFP, []>;
577 def XVCVSPSXDS : XX2Form<60, 408,
578 (outs vsrc:$XT), (ins vsrc:$XB),
579 "xvcvspsxds $XT, $XB", IIC_VecFP, []>;
580 def XVCVSPSXWS : XX2Form<60, 152,
581 (outs vsrc:$XT), (ins vsrc:$XB),
582 "xvcvspsxws $XT, $XB", IIC_VecFP, []>;
583 def XVCVSPUXDS : XX2Form<60, 392,
584 (outs vsrc:$XT), (ins vsrc:$XB),
585 "xvcvspuxds $XT, $XB", IIC_VecFP, []>;
586 def XVCVSPUXWS : XX2Form<60, 136,
587 (outs vsrc:$XT), (ins vsrc:$XB),
588 "xvcvspuxws $XT, $XB", IIC_VecFP, []>;
589 def XVCVSXDDP : XX2Form<60, 504,
590 (outs vsrc:$XT), (ins vsrc:$XB),
591 "xvcvsxddp $XT, $XB", IIC_VecFP,
592 [(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
593 def XVCVSXDSP : XX2Form<60, 440,
594 (outs vsrc:$XT), (ins vsrc:$XB),
595 "xvcvsxdsp $XT, $XB", IIC_VecFP, []>;
596 def XVCVSXWDP : XX2Form<60, 248,
597 (outs vsrc:$XT), (ins vsrc:$XB),
598 "xvcvsxwdp $XT, $XB", IIC_VecFP, []>;
599 def XVCVSXWSP : XX2Form<60, 184,
600 (outs vsrc:$XT), (ins vsrc:$XB),
601 "xvcvsxwsp $XT, $XB", IIC_VecFP, []>;
602 def XVCVUXDDP : XX2Form<60, 488,
603 (outs vsrc:$XT), (ins vsrc:$XB),
604 "xvcvuxddp $XT, $XB", IIC_VecFP,
605 [(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
606 def XVCVUXDSP : XX2Form<60, 424,
607 (outs vsrc:$XT), (ins vsrc:$XB),
608 "xvcvuxdsp $XT, $XB", IIC_VecFP, []>;
609 def XVCVUXWDP : XX2Form<60, 232,
610 (outs vsrc:$XT), (ins vsrc:$XB),
611 "xvcvuxwdp $XT, $XB", IIC_VecFP, []>;
612 def XVCVUXWSP : XX2Form<60, 168,
613 (outs vsrc:$XT), (ins vsrc:$XB),
614 "xvcvuxwsp $XT, $XB", IIC_VecFP, []>;
616 // Rounding Instructions
617 def XSRDPI : XX2Form<60, 73,
618 (outs vsfrc:$XT), (ins vsfrc:$XB),
619 "xsrdpi $XT, $XB", IIC_VecFP,
620 [(set f64:$XT, (frnd f64:$XB))]>;
621 def XSRDPIC : XX2Form<60, 107,
622 (outs vsfrc:$XT), (ins vsfrc:$XB),
623 "xsrdpic $XT, $XB", IIC_VecFP,
624 [(set f64:$XT, (fnearbyint f64:$XB))]>;
625 def XSRDPIM : XX2Form<60, 121,
626 (outs vsfrc:$XT), (ins vsfrc:$XB),
627 "xsrdpim $XT, $XB", IIC_VecFP,
628 [(set f64:$XT, (ffloor f64:$XB))]>;
629 def XSRDPIP : XX2Form<60, 105,
630 (outs vsfrc:$XT), (ins vsfrc:$XB),
631 "xsrdpip $XT, $XB", IIC_VecFP,
632 [(set f64:$XT, (fceil f64:$XB))]>;
633 def XSRDPIZ : XX2Form<60, 89,
634 (outs vsfrc:$XT), (ins vsfrc:$XB),
635 "xsrdpiz $XT, $XB", IIC_VecFP,
636 [(set f64:$XT, (ftrunc f64:$XB))]>;
638 def XVRDPI : XX2Form<60, 201,
639 (outs vsrc:$XT), (ins vsrc:$XB),
640 "xvrdpi $XT, $XB", IIC_VecFP,
641 [(set v2f64:$XT, (frnd v2f64:$XB))]>;
642 def XVRDPIC : XX2Form<60, 235,
643 (outs vsrc:$XT), (ins vsrc:$XB),
644 "xvrdpic $XT, $XB", IIC_VecFP,
645 [(set v2f64:$XT, (fnearbyint v2f64:$XB))]>;
646 def XVRDPIM : XX2Form<60, 249,
647 (outs vsrc:$XT), (ins vsrc:$XB),
648 "xvrdpim $XT, $XB", IIC_VecFP,
649 [(set v2f64:$XT, (ffloor v2f64:$XB))]>;
650 def XVRDPIP : XX2Form<60, 233,
651 (outs vsrc:$XT), (ins vsrc:$XB),
652 "xvrdpip $XT, $XB", IIC_VecFP,
653 [(set v2f64:$XT, (fceil v2f64:$XB))]>;
654 def XVRDPIZ : XX2Form<60, 217,
655 (outs vsrc:$XT), (ins vsrc:$XB),
656 "xvrdpiz $XT, $XB", IIC_VecFP,
657 [(set v2f64:$XT, (ftrunc v2f64:$XB))]>;
659 def XVRSPI : XX2Form<60, 137,
660 (outs vsrc:$XT), (ins vsrc:$XB),
661 "xvrspi $XT, $XB", IIC_VecFP,
662 [(set v4f32:$XT, (frnd v4f32:$XB))]>;
663 def XVRSPIC : XX2Form<60, 171,
664 (outs vsrc:$XT), (ins vsrc:$XB),
665 "xvrspic $XT, $XB", IIC_VecFP,
666 [(set v4f32:$XT, (fnearbyint v4f32:$XB))]>;
667 def XVRSPIM : XX2Form<60, 185,
668 (outs vsrc:$XT), (ins vsrc:$XB),
669 "xvrspim $XT, $XB", IIC_VecFP,
670 [(set v4f32:$XT, (ffloor v4f32:$XB))]>;
671 def XVRSPIP : XX2Form<60, 169,
672 (outs vsrc:$XT), (ins vsrc:$XB),
673 "xvrspip $XT, $XB", IIC_VecFP,
674 [(set v4f32:$XT, (fceil v4f32:$XB))]>;
675 def XVRSPIZ : XX2Form<60, 153,
676 (outs vsrc:$XT), (ins vsrc:$XB),
677 "xvrspiz $XT, $XB", IIC_VecFP,
678 [(set v4f32:$XT, (ftrunc v4f32:$XB))]>;
680 // Max/Min Instructions
681 let isCommutable = 1 in {
682 def XSMAXDP : XX3Form<60, 160,
683 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
684 "xsmaxdp $XT, $XA, $XB", IIC_VecFP,
686 (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>;
687 def XSMINDP : XX3Form<60, 168,
688 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
689 "xsmindp $XT, $XA, $XB", IIC_VecFP,
691 (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>;
693 def XVMAXDP : XX3Form<60, 224,
694 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
695 "xvmaxdp $XT, $XA, $XB", IIC_VecFP,
697 (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>;
698 def XVMINDP : XX3Form<60, 232,
699 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
700 "xvmindp $XT, $XA, $XB", IIC_VecFP,
702 (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>;
704 def XVMAXSP : XX3Form<60, 192,
705 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
706 "xvmaxsp $XT, $XA, $XB", IIC_VecFP,
708 (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>;
709 def XVMINSP : XX3Form<60, 200,
710 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
711 "xvminsp $XT, $XA, $XB", IIC_VecFP,
713 (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>;
717 // Logical Instructions
718 let isCommutable = 1 in
719 def XXLAND : XX3Form<60, 130,
720 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
721 "xxland $XT, $XA, $XB", IIC_VecGeneral,
722 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>;
723 def XXLANDC : XX3Form<60, 138,
724 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
725 "xxlandc $XT, $XA, $XB", IIC_VecGeneral,
726 [(set v4i32:$XT, (and v4i32:$XA,
727 (vnot_ppc v4i32:$XB)))]>;
728 let isCommutable = 1 in {
729 def XXLNOR : XX3Form<60, 162,
730 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
731 "xxlnor $XT, $XA, $XB", IIC_VecGeneral,
732 [(set v4i32:$XT, (vnot_ppc (or v4i32:$XA,
734 def XXLOR : XX3Form<60, 146,
735 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
736 "xxlor $XT, $XA, $XB", IIC_VecGeneral,
737 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>;
738 let isCodeGenOnly = 1 in
739 def XXLORf: XX3Form<60, 146,
740 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
741 "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;
742 def XXLXOR : XX3Form<60, 154,
743 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
744 "xxlxor $XT, $XA, $XB", IIC_VecGeneral,
745 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
748 // Permutation Instructions
749 def XXMRGHW : XX3Form<60, 18,
750 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
751 "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>;
752 def XXMRGLW : XX3Form<60, 50,
753 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
754 "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;
756 def XXPERMDI : XX3Form_2<60, 10,
757 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
758 "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, []>;
759 def XXSEL : XX4Form<60, 3,
760 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
761 "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
763 def XXSLDWI : XX3Form_2<60, 2,
764 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
765 "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, []>;
766 def XXSPLTW : XX2Form_2<60, 164,
767 (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
768 "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
771 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
772 // instruction selection into a branch sequence.
773 let usesCustomInserter = 1, // Expanded after instruction selection.
774 PPC970_Single = 1 in {
776 def SELECT_CC_VSRC: Pseudo<(outs vsrc:$dst),
777 (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC),
780 def SELECT_VSRC: Pseudo<(outs vsrc:$dst),
781 (ins crbitrc:$cond, vsrc:$T, vsrc:$F),
784 (select i1:$cond, v2f64:$T, v2f64:$F))]>;
785 def SELECT_CC_VSFRC: Pseudo<(outs f8rc:$dst),
786 (ins crrc:$cond, f8rc:$T, f8rc:$F,
787 i32imm:$BROPC), "#SELECT_CC_VSFRC",
789 def SELECT_VSFRC: Pseudo<(outs f8rc:$dst),
790 (ins crbitrc:$cond, f8rc:$T, f8rc:$F),
793 (select i1:$cond, f64:$T, f64:$F))]>;
794 } // usesCustomInserter
797 def : InstAlias<"xvmovdp $XT, $XB",
798 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
799 def : InstAlias<"xvmovsp $XT, $XB",
800 (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
802 def : InstAlias<"xxspltd $XT, $XB, 0",
803 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>;
804 def : InstAlias<"xxspltd $XT, $XB, 1",
805 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;
806 def : InstAlias<"xxmrghd $XT, $XA, $XB",
807 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>;
808 def : InstAlias<"xxmrgld $XT, $XA, $XB",
809 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;
810 def : InstAlias<"xxswapd $XT, $XB",
811 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
813 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
815 let Predicates = [IsBigEndian] in {
816 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
817 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
819 def : Pat<(f64 (vector_extract v2f64:$S, 0)),
820 (f64 (EXTRACT_SUBREG $S, sub_64))>;
821 def : Pat<(f64 (vector_extract v2f64:$S, 1)),
822 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
825 let Predicates = [IsLittleEndian] in {
826 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
827 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
828 (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;
830 def : Pat<(f64 (vector_extract v2f64:$S, 0)),
831 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
832 def : Pat<(f64 (vector_extract v2f64:$S, 1)),
833 (f64 (EXTRACT_SUBREG $S, sub_64))>;
836 // Additional fnmsub patterns: -a*c + b == -(a*c - b)
837 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
838 (XSNMSUBADP $B, $C, $A)>;
839 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
840 (XSNMSUBADP $B, $C, $A)>;
842 def : Pat<(fma (fneg v2f64:$A), v2f64:$C, v2f64:$B),
843 (XVNMSUBADP $B, $C, $A)>;
844 def : Pat<(fma v2f64:$A, (fneg v2f64:$C), v2f64:$B),
845 (XVNMSUBADP $B, $C, $A)>;
847 def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B),
848 (XVNMSUBASP $B, $C, $A)>;
849 def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B),
850 (XVNMSUBASP $B, $C, $A)>;
852 def : Pat<(v2f64 (bitconvert v4f32:$A)),
853 (COPY_TO_REGCLASS $A, VSRC)>;
854 def : Pat<(v2f64 (bitconvert v4i32:$A)),
855 (COPY_TO_REGCLASS $A, VSRC)>;
856 def : Pat<(v2f64 (bitconvert v8i16:$A)),
857 (COPY_TO_REGCLASS $A, VSRC)>;
858 def : Pat<(v2f64 (bitconvert v16i8:$A)),
859 (COPY_TO_REGCLASS $A, VSRC)>;
861 def : Pat<(v4f32 (bitconvert v2f64:$A)),
862 (COPY_TO_REGCLASS $A, VRRC)>;
863 def : Pat<(v4i32 (bitconvert v2f64:$A)),
864 (COPY_TO_REGCLASS $A, VRRC)>;
865 def : Pat<(v8i16 (bitconvert v2f64:$A)),
866 (COPY_TO_REGCLASS $A, VRRC)>;
867 def : Pat<(v16i8 (bitconvert v2f64:$A)),
868 (COPY_TO_REGCLASS $A, VRRC)>;
870 def : Pat<(v2i64 (bitconvert v4f32:$A)),
871 (COPY_TO_REGCLASS $A, VSRC)>;
872 def : Pat<(v2i64 (bitconvert v4i32:$A)),
873 (COPY_TO_REGCLASS $A, VSRC)>;
874 def : Pat<(v2i64 (bitconvert v8i16:$A)),
875 (COPY_TO_REGCLASS $A, VSRC)>;
876 def : Pat<(v2i64 (bitconvert v16i8:$A)),
877 (COPY_TO_REGCLASS $A, VSRC)>;
879 def : Pat<(v4f32 (bitconvert v2i64:$A)),
880 (COPY_TO_REGCLASS $A, VRRC)>;
881 def : Pat<(v4i32 (bitconvert v2i64:$A)),
882 (COPY_TO_REGCLASS $A, VRRC)>;
883 def : Pat<(v8i16 (bitconvert v2i64:$A)),
884 (COPY_TO_REGCLASS $A, VRRC)>;
885 def : Pat<(v16i8 (bitconvert v2i64:$A)),
886 (COPY_TO_REGCLASS $A, VRRC)>;
888 def : Pat<(v2f64 (bitconvert v2i64:$A)),
889 (COPY_TO_REGCLASS $A, VRRC)>;
890 def : Pat<(v2i64 (bitconvert v2f64:$A)),
891 (COPY_TO_REGCLASS $A, VRRC)>;
893 // sign extension patterns
894 // To extend "in place" from v2i32 to v2i64, we have input data like:
895 // | undef | i32 | undef | i32 |
896 // but xvcvsxwdp expects the input in big-Endian format:
897 // | i32 | undef | i32 | undef |
898 // so we need to shift everything to the left by one i32 (word) before
900 def : Pat<(sext_inreg v2i64:$C, v2i32),
901 (XVCVDPSXDS (XVCVSXWDP (XXSLDWI $C, $C, 1)))>;
902 def : Pat<(v2f64 (sint_to_fp (sext_inreg v2i64:$C, v2i32))),
903 (XVCVSXWDP (XXSLDWI $C, $C, 1))>;
906 def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
907 def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
908 def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
909 def : Pat<(v2f64 (PPClxvd2x xoaddr:$src)), (LXVD2X xoaddr:$src)>;
912 def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
913 (STXVD2X $rS, xoaddr:$dst)>;
914 def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
915 def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
916 (STXVW4X $rS, xoaddr:$dst)>;
917 def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
920 def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>;
921 def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>;
922 def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>;
923 def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>;
926 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),
927 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
928 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)),
929 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
930 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)),
931 (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>;
932 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),
933 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
934 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)),
935 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
936 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),
937 (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
939 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
940 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
941 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
942 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;
943 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
944 (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>;
945 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
946 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;
947 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
948 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
949 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
950 (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
953 def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
955 def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
961 // The following VSX instructions were introduced in Power ISA 2.07
962 /* FIXME: if the operands are v2i64, these patterns will not match.
963 we should define new patterns or otherwise match the same patterns
964 when the elements are larger than i32.
966 def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">;
967 def HasDirectMove : Predicate<"PPCSubTarget->hasDirectMove()">;
968 let Predicates = [HasP8Vector] in {
969 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
970 let isCommutable = 1 in {
971 def XXLEQV : XX3Form<60, 186,
972 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
973 "xxleqv $XT, $XA, $XB", IIC_VecGeneral,
974 [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>;
975 def XXLNAND : XX3Form<60, 178,
976 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
977 "xxlnand $XT, $XA, $XB", IIC_VecGeneral,
978 [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA,
981 def XXLORC : XX3Form<60, 170,
982 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
983 "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
984 [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
985 } // AddedComplexity = 500
988 let Predicates = [HasDirectMove, HasVSX] in {
989 // VSX direct move instructions
990 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
991 "mfvsrd $rA, $XT", IIC_VecGeneral,
992 [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
993 Requires<[In64BitMode]>;
994 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
995 "mfvsrwz $rA, $XT", IIC_VecGeneral,
996 [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
997 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
998 "mtvsrd $XT, $rA", IIC_VecGeneral,
999 [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
1000 Requires<[In64BitMode]>;
1001 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
1002 "mtvsrwa $XT, $rA", IIC_VecGeneral,
1003 [(set f64:$XT, (PPCmtvsra i32:$rA))]>;
1004 def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
1005 "mtvsrwz $XT, $rA", IIC_VecGeneral,
1006 [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
1007 } // HasDirectMove, HasVSX