1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
114 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
115 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
116 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
117 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
119 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
121 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
123 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
124 // amounts. These nodes are generated by the multi-precision shift code.
125 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
126 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
127 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
129 // These are target-independent nodes, but have target-specific formats.
130 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
131 [SDNPHasChain, SDNPOutGlue]>;
132 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
136 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
142 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
294 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
295 // zero extended field.
296 return isUInt<32>(Imm);
299 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
300 // restricted memrix (4-aligned) constants are alignment sensitive. If these
301 // offsets are hidden behind TOC entries than the values of the lower-order
302 // bits cannot be checked directly. As a result, we need to also incorporate
303 // an alignment check into the relevant patterns.
305 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
306 return cast<LoadSDNode>(N)->getAlignment() >= 4;
308 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
309 (store node:$val, node:$ptr), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
312 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
313 return cast<LoadSDNode>(N)->getAlignment() >= 4;
315 def aligned4pre_store : PatFrag<
316 (ops node:$val, node:$base, node:$offset),
317 (pre_store node:$val, node:$base, node:$offset), [{
318 return cast<StoreSDNode>(N)->getAlignment() >= 4;
321 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
322 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
325 (store node:$val, node:$ptr), [{
326 return cast<StoreSDNode>(N)->getAlignment() < 4;
328 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
329 return cast<LoadSDNode>(N)->getAlignment() < 4;
332 //===----------------------------------------------------------------------===//
333 // PowerPC Flag Definitions.
335 class isPPC64 { bit PPC64 = 1; }
336 class isDOT { bit RC = 1; }
338 class RegConstraint<string C> {
339 string Constraints = C;
341 class NoEncode<string E> {
342 string DisableEncoding = E;
346 //===----------------------------------------------------------------------===//
347 // PowerPC Operand Definitions.
349 // In the default PowerPC assembler syntax, registers are specified simply
350 // by number, so they cannot be distinguished from immediate values (without
351 // looking at the opcode). This means that the default operand matching logic
352 // for the asm parser does not work, and we need to specify custom matchers.
353 // Since those can only be specified with RegisterOperand classes and not
354 // directly on the RegisterClass, all instructions patterns used by the asm
355 // parser need to use a RegisterOperand (instead of a RegisterClass) for
356 // all their register operands.
357 // For this purpose, we define one RegisterOperand for each RegisterClass,
358 // using the same name as the class, just in lower case.
360 def PPCRegGPRCAsmOperand : AsmOperandClass {
361 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
363 def gprc : RegisterOperand<GPRC> {
364 let ParserMatchClass = PPCRegGPRCAsmOperand;
366 def PPCRegG8RCAsmOperand : AsmOperandClass {
367 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
369 def g8rc : RegisterOperand<G8RC> {
370 let ParserMatchClass = PPCRegG8RCAsmOperand;
372 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
373 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
375 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
376 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
378 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
379 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
381 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
382 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
384 def PPCRegF8RCAsmOperand : AsmOperandClass {
385 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
387 def f8rc : RegisterOperand<F8RC> {
388 let ParserMatchClass = PPCRegF8RCAsmOperand;
390 def PPCRegF4RCAsmOperand : AsmOperandClass {
391 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
393 def f4rc : RegisterOperand<F4RC> {
394 let ParserMatchClass = PPCRegF4RCAsmOperand;
396 def PPCRegVRRCAsmOperand : AsmOperandClass {
397 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
399 def vrrc : RegisterOperand<VRRC> {
400 let ParserMatchClass = PPCRegVRRCAsmOperand;
402 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
405 def crbitrc : RegisterOperand<CRBITRC> {
406 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
408 def PPCRegCRRCAsmOperand : AsmOperandClass {
409 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
411 def crrc : RegisterOperand<CRRC> {
412 let ParserMatchClass = PPCRegCRRCAsmOperand;
415 def PPCU2ImmAsmOperand : AsmOperandClass {
416 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
417 let RenderMethod = "addImmOperands";
419 def u2imm : Operand<i32> {
420 let PrintMethod = "printU2ImmOperand";
421 let ParserMatchClass = PPCU2ImmAsmOperand;
424 def PPCU4ImmAsmOperand : AsmOperandClass {
425 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
426 let RenderMethod = "addImmOperands";
428 def u4imm : Operand<i32> {
429 let PrintMethod = "printU4ImmOperand";
430 let ParserMatchClass = PPCU4ImmAsmOperand;
432 def PPCS5ImmAsmOperand : AsmOperandClass {
433 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
434 let RenderMethod = "addImmOperands";
436 def s5imm : Operand<i32> {
437 let PrintMethod = "printS5ImmOperand";
438 let ParserMatchClass = PPCS5ImmAsmOperand;
439 let DecoderMethod = "decodeSImmOperand<5>";
441 def PPCU5ImmAsmOperand : AsmOperandClass {
442 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
443 let RenderMethod = "addImmOperands";
445 def u5imm : Operand<i32> {
446 let PrintMethod = "printU5ImmOperand";
447 let ParserMatchClass = PPCU5ImmAsmOperand;
448 let DecoderMethod = "decodeUImmOperand<5>";
450 def PPCU6ImmAsmOperand : AsmOperandClass {
451 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
452 let RenderMethod = "addImmOperands";
454 def u6imm : Operand<i32> {
455 let PrintMethod = "printU6ImmOperand";
456 let ParserMatchClass = PPCU6ImmAsmOperand;
457 let DecoderMethod = "decodeUImmOperand<6>";
459 def PPCS16ImmAsmOperand : AsmOperandClass {
460 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
461 let RenderMethod = "addS16ImmOperands";
463 def s16imm : Operand<i32> {
464 let PrintMethod = "printS16ImmOperand";
465 let EncoderMethod = "getImm16Encoding";
466 let ParserMatchClass = PPCS16ImmAsmOperand;
467 let DecoderMethod = "decodeSImmOperand<16>";
469 def PPCU16ImmAsmOperand : AsmOperandClass {
470 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
471 let RenderMethod = "addU16ImmOperands";
473 def u16imm : Operand<i32> {
474 let PrintMethod = "printU16ImmOperand";
475 let EncoderMethod = "getImm16Encoding";
476 let ParserMatchClass = PPCU16ImmAsmOperand;
477 let DecoderMethod = "decodeUImmOperand<16>";
479 def PPCS17ImmAsmOperand : AsmOperandClass {
480 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
481 let RenderMethod = "addS16ImmOperands";
483 def s17imm : Operand<i32> {
484 // This operand type is used for addis/lis to allow the assembler parser
485 // to accept immediates in the range -65536..65535 for compatibility with
486 // the GNU assembler. The operand is treated as 16-bit otherwise.
487 let PrintMethod = "printS16ImmOperand";
488 let EncoderMethod = "getImm16Encoding";
489 let ParserMatchClass = PPCS17ImmAsmOperand;
490 let DecoderMethod = "decodeSImmOperand<16>";
492 def PPCDirectBrAsmOperand : AsmOperandClass {
493 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
494 let RenderMethod = "addBranchTargetOperands";
496 def directbrtarget : Operand<OtherVT> {
497 let PrintMethod = "printBranchOperand";
498 let EncoderMethod = "getDirectBrEncoding";
499 let ParserMatchClass = PPCDirectBrAsmOperand;
501 def absdirectbrtarget : Operand<OtherVT> {
502 let PrintMethod = "printAbsBranchOperand";
503 let EncoderMethod = "getAbsDirectBrEncoding";
504 let ParserMatchClass = PPCDirectBrAsmOperand;
506 def PPCCondBrAsmOperand : AsmOperandClass {
507 let Name = "CondBr"; let PredicateMethod = "isCondBr";
508 let RenderMethod = "addBranchTargetOperands";
510 def condbrtarget : Operand<OtherVT> {
511 let PrintMethod = "printBranchOperand";
512 let EncoderMethod = "getCondBrEncoding";
513 let ParserMatchClass = PPCCondBrAsmOperand;
515 def abscondbrtarget : Operand<OtherVT> {
516 let PrintMethod = "printAbsBranchOperand";
517 let EncoderMethod = "getAbsCondBrEncoding";
518 let ParserMatchClass = PPCCondBrAsmOperand;
520 def calltarget : Operand<iPTR> {
521 let PrintMethod = "printBranchOperand";
522 let EncoderMethod = "getDirectBrEncoding";
523 let ParserMatchClass = PPCDirectBrAsmOperand;
525 def abscalltarget : Operand<iPTR> {
526 let PrintMethod = "printAbsBranchOperand";
527 let EncoderMethod = "getAbsDirectBrEncoding";
528 let ParserMatchClass = PPCDirectBrAsmOperand;
530 def PPCCRBitMaskOperand : AsmOperandClass {
531 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
533 def crbitm: Operand<i8> {
534 let PrintMethod = "printcrbitm";
535 let EncoderMethod = "get_crbitm_encoding";
536 let DecoderMethod = "decodeCRBitMOperand";
537 let ParserMatchClass = PPCCRBitMaskOperand;
540 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
541 def PPCRegGxRCNoR0Operand : AsmOperandClass {
542 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
544 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
545 let ParserMatchClass = PPCRegGxRCNoR0Operand;
547 // A version of ptr_rc usable with the asm parser.
548 def PPCRegGxRCOperand : AsmOperandClass {
549 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
551 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
552 let ParserMatchClass = PPCRegGxRCOperand;
555 def PPCDispRIOperand : AsmOperandClass {
556 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
557 let RenderMethod = "addS16ImmOperands";
559 def dispRI : Operand<iPTR> {
560 let ParserMatchClass = PPCDispRIOperand;
562 def PPCDispRIXOperand : AsmOperandClass {
563 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
564 let RenderMethod = "addImmOperands";
566 def dispRIX : Operand<iPTR> {
567 let ParserMatchClass = PPCDispRIXOperand;
569 def PPCDispSPE8Operand : AsmOperandClass {
570 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
571 let RenderMethod = "addImmOperands";
573 def dispSPE8 : Operand<iPTR> {
574 let ParserMatchClass = PPCDispSPE8Operand;
576 def PPCDispSPE4Operand : AsmOperandClass {
577 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
578 let RenderMethod = "addImmOperands";
580 def dispSPE4 : Operand<iPTR> {
581 let ParserMatchClass = PPCDispSPE4Operand;
583 def PPCDispSPE2Operand : AsmOperandClass {
584 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
585 let RenderMethod = "addImmOperands";
587 def dispSPE2 : Operand<iPTR> {
588 let ParserMatchClass = PPCDispSPE2Operand;
591 def memri : Operand<iPTR> {
592 let PrintMethod = "printMemRegImm";
593 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
594 let EncoderMethod = "getMemRIEncoding";
595 let DecoderMethod = "decodeMemRIOperands";
597 def memrr : Operand<iPTR> {
598 let PrintMethod = "printMemRegReg";
599 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
601 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
602 let PrintMethod = "printMemRegImm";
603 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
604 let EncoderMethod = "getMemRIXEncoding";
605 let DecoderMethod = "decodeMemRIXOperands";
607 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
608 let PrintMethod = "printMemRegImm";
609 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
610 let EncoderMethod = "getSPE8DisEncoding";
612 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
613 let PrintMethod = "printMemRegImm";
614 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
615 let EncoderMethod = "getSPE4DisEncoding";
617 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
618 let PrintMethod = "printMemRegImm";
619 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
620 let EncoderMethod = "getSPE2DisEncoding";
623 // A single-register address. This is used with the SjLj
624 // pseudo-instructions.
625 def memr : Operand<iPTR> {
626 let MIOperandInfo = (ops ptr_rc:$ptrreg);
628 def PPCTLSRegOperand : AsmOperandClass {
629 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
630 let RenderMethod = "addTLSRegOperands";
632 def tlsreg32 : Operand<i32> {
633 let EncoderMethod = "getTLSRegEncoding";
634 let ParserMatchClass = PPCTLSRegOperand;
636 def tlsgd32 : Operand<i32> {}
637 def tlscall32 : Operand<i32> {
638 let PrintMethod = "printTLSCall";
639 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
640 let EncoderMethod = "getTLSCallEncoding";
643 // PowerPC Predicate operand.
644 def pred : Operand<OtherVT> {
645 let PrintMethod = "printPredicateOperand";
646 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
649 // Define PowerPC specific addressing mode.
650 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
651 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
652 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
653 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
655 // The address in a single register. This is used with the SjLj
656 // pseudo-instructions.
657 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
659 /// This is just the offset part of iaddr, used for preinc.
660 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
662 //===----------------------------------------------------------------------===//
663 // PowerPC Instruction Predicate Definitions.
664 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
665 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
666 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
667 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
668 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
669 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
670 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
671 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
672 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
673 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
675 //===----------------------------------------------------------------------===//
676 // PowerPC Multiclass Definitions.
678 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
679 string asmbase, string asmstr, InstrItinClass itin,
681 let BaseName = asmbase in {
682 def NAME : XForm_6<opcode, xo, OOL, IOL,
683 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
684 pattern>, RecFormRel;
686 def o : XForm_6<opcode, xo, OOL, IOL,
687 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
688 []>, isDOT, RecFormRel;
692 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
693 string asmbase, string asmstr, InstrItinClass itin,
695 let BaseName = asmbase in {
696 let Defs = [CARRY] in
697 def NAME : XForm_6<opcode, xo, OOL, IOL,
698 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
699 pattern>, RecFormRel;
700 let Defs = [CARRY, CR0] in
701 def o : XForm_6<opcode, xo, OOL, IOL,
702 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
703 []>, isDOT, RecFormRel;
707 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
708 string asmbase, string asmstr, InstrItinClass itin,
710 let BaseName = asmbase in {
711 let Defs = [CARRY] in
712 def NAME : XForm_10<opcode, xo, OOL, IOL,
713 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
714 pattern>, RecFormRel;
715 let Defs = [CARRY, CR0] in
716 def o : XForm_10<opcode, xo, OOL, IOL,
717 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
718 []>, isDOT, RecFormRel;
722 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
723 string asmbase, string asmstr, InstrItinClass itin,
725 let BaseName = asmbase in {
726 def NAME : XForm_11<opcode, xo, OOL, IOL,
727 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
728 pattern>, RecFormRel;
730 def o : XForm_11<opcode, xo, OOL, IOL,
731 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
732 []>, isDOT, RecFormRel;
736 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
737 string asmbase, string asmstr, InstrItinClass itin,
739 let BaseName = asmbase in {
740 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
741 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
742 pattern>, RecFormRel;
744 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
745 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
746 []>, isDOT, RecFormRel;
750 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
751 string asmbase, string asmstr, InstrItinClass itin,
753 let BaseName = asmbase in {
754 let Defs = [CARRY] in
755 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
756 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
757 pattern>, RecFormRel;
758 let Defs = [CARRY, CR0] in
759 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
760 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
761 []>, isDOT, RecFormRel;
765 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
766 string asmbase, string asmstr, InstrItinClass itin,
768 let BaseName = asmbase in {
769 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
770 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
771 pattern>, RecFormRel;
773 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
774 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
775 []>, isDOT, RecFormRel;
779 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
780 string asmbase, string asmstr, InstrItinClass itin,
782 let BaseName = asmbase in {
783 let Defs = [CARRY] in
784 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
785 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
786 pattern>, RecFormRel;
787 let Defs = [CARRY, CR0] in
788 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
789 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
790 []>, isDOT, RecFormRel;
794 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
795 string asmbase, string asmstr, InstrItinClass itin,
797 let BaseName = asmbase in {
798 def NAME : MForm_2<opcode, OOL, IOL,
799 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
800 pattern>, RecFormRel;
802 def o : MForm_2<opcode, OOL, IOL,
803 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
804 []>, isDOT, RecFormRel;
808 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
809 string asmbase, string asmstr, InstrItinClass itin,
811 let BaseName = asmbase in {
812 def NAME : MDForm_1<opcode, xo, OOL, IOL,
813 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
814 pattern>, RecFormRel;
816 def o : MDForm_1<opcode, xo, OOL, IOL,
817 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
818 []>, isDOT, RecFormRel;
822 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
823 string asmbase, string asmstr, InstrItinClass itin,
825 let BaseName = asmbase in {
826 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
827 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
828 pattern>, RecFormRel;
830 def o : MDSForm_1<opcode, xo, OOL, IOL,
831 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
832 []>, isDOT, RecFormRel;
836 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
837 string asmbase, string asmstr, InstrItinClass itin,
839 let BaseName = asmbase in {
840 let Defs = [CARRY] in
841 def NAME : XSForm_1<opcode, xo, OOL, IOL,
842 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
843 pattern>, RecFormRel;
844 let Defs = [CARRY, CR0] in
845 def o : XSForm_1<opcode, xo, OOL, IOL,
846 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
847 []>, isDOT, RecFormRel;
851 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
852 string asmbase, string asmstr, InstrItinClass itin,
854 let BaseName = asmbase in {
855 def NAME : XForm_26<opcode, xo, OOL, IOL,
856 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
857 pattern>, RecFormRel;
859 def o : XForm_26<opcode, xo, OOL, IOL,
860 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
861 []>, isDOT, RecFormRel;
865 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
866 string asmbase, string asmstr, InstrItinClass itin,
868 let BaseName = asmbase in {
869 def NAME : XForm_28<opcode, xo, OOL, IOL,
870 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
871 pattern>, RecFormRel;
873 def o : XForm_28<opcode, xo, OOL, IOL,
874 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
875 []>, isDOT, RecFormRel;
879 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
880 string asmbase, string asmstr, InstrItinClass itin,
882 let BaseName = asmbase in {
883 def NAME : AForm_1<opcode, xo, OOL, IOL,
884 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
885 pattern>, RecFormRel;
887 def o : AForm_1<opcode, xo, OOL, IOL,
888 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
889 []>, isDOT, RecFormRel;
893 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
894 string asmbase, string asmstr, InstrItinClass itin,
896 let BaseName = asmbase in {
897 def NAME : AForm_2<opcode, xo, OOL, IOL,
898 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
899 pattern>, RecFormRel;
901 def o : AForm_2<opcode, xo, OOL, IOL,
902 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
903 []>, isDOT, RecFormRel;
907 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
908 string asmbase, string asmstr, InstrItinClass itin,
910 let BaseName = asmbase in {
911 def NAME : AForm_3<opcode, xo, OOL, IOL,
912 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
913 pattern>, RecFormRel;
915 def o : AForm_3<opcode, xo, OOL, IOL,
916 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
917 []>, isDOT, RecFormRel;
921 //===----------------------------------------------------------------------===//
922 // PowerPC Instruction Definitions.
924 // Pseudo-instructions:
926 let hasCtrlDep = 1 in {
927 let Defs = [R1], Uses = [R1] in {
928 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
929 [(callseq_start timm:$amt)]>;
930 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
931 [(callseq_end timm:$amt1, timm:$amt2)]>;
934 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
935 "UPDATE_VRSAVE $rD, $rS", []>;
938 let Defs = [R1], Uses = [R1] in
939 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
941 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
943 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
944 // instruction selection into a branch sequence.
945 let usesCustomInserter = 1, // Expanded after instruction selection.
946 PPC970_Single = 1 in {
947 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
948 // because either operand might become the first operand in an isel, and
949 // that operand cannot be r0.
950 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
951 gprc_nor0:$T, gprc_nor0:$F,
952 i32imm:$BROPC), "#SELECT_CC_I4",
954 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
955 g8rc_nox0:$T, g8rc_nox0:$F,
956 i32imm:$BROPC), "#SELECT_CC_I8",
958 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
959 i32imm:$BROPC), "#SELECT_CC_F4",
961 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
962 i32imm:$BROPC), "#SELECT_CC_F8",
964 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
965 i32imm:$BROPC), "#SELECT_CC_VRRC",
968 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
969 // register bit directly.
970 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
971 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
972 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
973 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
974 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
975 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
976 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
977 f4rc:$T, f4rc:$F), "#SELECT_F4",
978 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
979 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
980 f8rc:$T, f8rc:$F), "#SELECT_F8",
981 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
982 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
983 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
985 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
988 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
989 // scavenge a register for it.
990 let mayStore = 1 in {
991 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
993 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
997 // RESTORE_CR - Indicate that we're restoring the CR register (previously
998 // spilled), so we'll need to scavenge a register for it.
1000 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1002 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1003 "#RESTORE_CRBIT", []>;
1006 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1007 let isReturn = 1, Uses = [LR, RM] in
1008 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1010 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1011 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1014 let isCodeGenOnly = 1 in {
1015 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1016 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1019 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1020 "bcctr 12, $bi, 0", IIC_BrB, []>;
1021 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1022 "bcctr 4, $bi, 0", IIC_BrB, []>;
1028 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1031 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1032 let isBarrier = 1 in {
1033 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1036 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1037 "ba $dst", IIC_BrB, []>;
1040 // BCC represents an arbitrary conditional branch on a predicate.
1041 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1042 // a two-value operand where a dag node expects two operands. :(
1043 let isCodeGenOnly = 1 in {
1044 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1045 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1046 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1047 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1048 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1050 let isReturn = 1, Uses = [LR, RM] in
1051 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1052 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1055 let isCodeGenOnly = 1 in {
1056 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1057 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1058 "bc 12, $bi, $dst">;
1060 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1061 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1064 let isReturn = 1, Uses = [LR, RM] in
1065 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1066 "bclr 12, $bi, 0", IIC_BrB, []>;
1067 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1068 "bclr 4, $bi, 0", IIC_BrB, []>;
1071 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1072 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1073 "bdzlr", IIC_BrB, []>;
1074 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1075 "bdnzlr", IIC_BrB, []>;
1076 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1077 "bdzlr+", IIC_BrB, []>;
1078 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1079 "bdnzlr+", IIC_BrB, []>;
1080 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1081 "bdzlr-", IIC_BrB, []>;
1082 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1083 "bdnzlr-", IIC_BrB, []>;
1086 let Defs = [CTR], Uses = [CTR] in {
1087 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1089 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1091 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1093 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1095 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1097 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1099 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1101 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1103 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1105 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1107 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1109 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1114 // The unconditional BCL used by the SjLj setjmp code.
1115 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1116 let Defs = [LR], Uses = [RM] in {
1117 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1118 "bcl 20, 31, $dst">;
1122 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1123 // Convenient aliases for call instructions
1124 let Uses = [RM] in {
1125 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1126 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1127 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1128 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1130 let isCodeGenOnly = 1 in {
1131 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1132 "bl $func", IIC_BrB, []>;
1133 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1134 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1135 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1136 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1138 def BCL : BForm_4<16, 12, 0, 1, (outs),
1139 (ins crbitrc:$bi, condbrtarget:$dst),
1140 "bcl 12, $bi, $dst">;
1141 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1142 (ins crbitrc:$bi, condbrtarget:$dst),
1143 "bcl 4, $bi, $dst">;
1146 let Uses = [CTR, RM] in {
1147 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1148 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1149 Requires<[In32BitMode]>;
1151 let isCodeGenOnly = 1 in {
1152 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1153 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1156 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1157 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1158 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1159 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1162 let Uses = [LR, RM] in {
1163 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1164 "blrl", IIC_BrB, []>;
1166 let isCodeGenOnly = 1 in {
1167 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1168 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1171 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1172 "bclrl 12, $bi, 0", IIC_BrB, []>;
1173 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1174 "bclrl 4, $bi, 0", IIC_BrB, []>;
1177 let Defs = [CTR], Uses = [CTR, RM] in {
1178 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1180 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1182 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1184 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1186 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1188 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1190 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1192 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1194 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1196 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1198 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1200 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1203 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1204 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1205 "bdzlrl", IIC_BrB, []>;
1206 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1207 "bdnzlrl", IIC_BrB, []>;
1208 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1209 "bdzlrl+", IIC_BrB, []>;
1210 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1211 "bdnzlrl+", IIC_BrB, []>;
1212 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1213 "bdzlrl-", IIC_BrB, []>;
1214 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1215 "bdnzlrl-", IIC_BrB, []>;
1219 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1220 def TCRETURNdi :Pseudo< (outs),
1221 (ins calltarget:$dst, i32imm:$offset),
1222 "#TC_RETURNd $dst $offset",
1226 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1227 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1228 "#TC_RETURNa $func $offset",
1229 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1231 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1232 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1233 "#TC_RETURNr $dst $offset",
1237 let isCodeGenOnly = 1 in {
1239 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1240 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1241 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1242 []>, Requires<[In32BitMode]>;
1244 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1245 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1246 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1250 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1251 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1252 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1258 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1260 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1261 "#EH_SJLJ_SETJMP32",
1262 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1263 Requires<[In32BitMode]>;
1264 let isTerminator = 1 in
1265 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1266 "#EH_SJLJ_LONGJMP32",
1267 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1268 Requires<[In32BitMode]>;
1271 let isBranch = 1, isTerminator = 1 in {
1272 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1273 "#EH_SjLj_Setup\t$dst", []>;
1277 let PPC970_Unit = 7 in {
1278 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1279 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1282 // DCB* instructions.
1283 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1284 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1285 PPC970_DGroup_Single;
1286 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1287 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1288 PPC970_DGroup_Single;
1289 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1290 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1291 PPC970_DGroup_Single;
1292 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1293 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1294 PPC970_DGroup_Single;
1295 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1296 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1297 PPC970_DGroup_Single;
1298 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1299 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1300 PPC970_DGroup_Single;
1301 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1302 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1303 PPC970_DGroup_Single;
1304 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1305 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1306 PPC970_DGroup_Single;
1308 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1309 "icbt $CT, $src", IIC_LdStLoad>, Requires<[IsBookE]>;
1311 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1312 (DCBT xoaddr:$dst)>; // data prefetch for loads
1313 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1314 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1315 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1316 (ICBT 0, xoaddr:$dst)>; // inst prefetch (for read)
1318 // Atomic operations
1319 let usesCustomInserter = 1 in {
1320 let Defs = [CR0] in {
1321 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1322 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1323 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1324 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1325 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1326 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1327 def ATOMIC_LOAD_AND_I8 : Pseudo<
1328 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1329 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1330 def ATOMIC_LOAD_OR_I8 : Pseudo<
1331 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1332 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1333 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1334 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1335 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1336 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1337 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1338 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1339 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1340 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1341 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1342 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1343 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1344 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1345 def ATOMIC_LOAD_AND_I16 : Pseudo<
1346 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1347 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1348 def ATOMIC_LOAD_OR_I16 : Pseudo<
1349 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1350 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1351 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1352 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1353 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1354 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1355 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1356 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1357 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1358 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1359 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1360 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1361 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1362 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1363 def ATOMIC_LOAD_AND_I32 : Pseudo<
1364 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1365 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1366 def ATOMIC_LOAD_OR_I32 : Pseudo<
1367 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1368 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1369 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1370 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1371 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1372 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1373 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1374 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1376 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1377 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1378 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1379 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1380 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1381 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1382 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1383 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1384 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1386 def ATOMIC_SWAP_I8 : Pseudo<
1387 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1388 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1389 def ATOMIC_SWAP_I16 : Pseudo<
1390 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1391 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1392 def ATOMIC_SWAP_I32 : Pseudo<
1393 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1394 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1398 // Instructions to support atomic operations
1399 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1400 "lwarx $rD, $src", IIC_LdStLWARX,
1401 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1404 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1405 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1406 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1409 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1410 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1412 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1413 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1414 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1415 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1416 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1417 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1418 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1419 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1421 //===----------------------------------------------------------------------===//
1422 // PPC32 Load Instructions.
1425 // Unindexed (r+i) Loads.
1426 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1427 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1428 "lbz $rD, $src", IIC_LdStLoad,
1429 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1430 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1431 "lha $rD, $src", IIC_LdStLHA,
1432 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1433 PPC970_DGroup_Cracked;
1434 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1435 "lhz $rD, $src", IIC_LdStLoad,
1436 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1437 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1438 "lwz $rD, $src", IIC_LdStLoad,
1439 [(set i32:$rD, (load iaddr:$src))]>;
1441 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1442 "lfs $rD, $src", IIC_LdStLFD,
1443 [(set f32:$rD, (load iaddr:$src))]>;
1444 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1445 "lfd $rD, $src", IIC_LdStLFD,
1446 [(set f64:$rD, (load iaddr:$src))]>;
1449 // Unindexed (r+i) Loads with Update (preinc).
1450 let mayLoad = 1, neverHasSideEffects = 1 in {
1451 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1452 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1453 []>, RegConstraint<"$addr.reg = $ea_result">,
1454 NoEncode<"$ea_result">;
1456 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1457 "lhau $rD, $addr", IIC_LdStLHAU,
1458 []>, RegConstraint<"$addr.reg = $ea_result">,
1459 NoEncode<"$ea_result">;
1461 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1462 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1463 []>, RegConstraint<"$addr.reg = $ea_result">,
1464 NoEncode<"$ea_result">;
1466 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1467 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1468 []>, RegConstraint<"$addr.reg = $ea_result">,
1469 NoEncode<"$ea_result">;
1471 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1472 "lfsu $rD, $addr", IIC_LdStLFDU,
1473 []>, RegConstraint<"$addr.reg = $ea_result">,
1474 NoEncode<"$ea_result">;
1476 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1477 "lfdu $rD, $addr", IIC_LdStLFDU,
1478 []>, RegConstraint<"$addr.reg = $ea_result">,
1479 NoEncode<"$ea_result">;
1482 // Indexed (r+r) Loads with Update (preinc).
1483 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1485 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1486 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1487 NoEncode<"$ea_result">;
1489 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1491 "lhaux $rD, $addr", IIC_LdStLHAUX,
1492 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1493 NoEncode<"$ea_result">;
1495 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1497 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1498 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1499 NoEncode<"$ea_result">;
1501 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1503 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1504 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1505 NoEncode<"$ea_result">;
1507 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1509 "lfsux $rD, $addr", IIC_LdStLFDUX,
1510 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1511 NoEncode<"$ea_result">;
1513 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1515 "lfdux $rD, $addr", IIC_LdStLFDUX,
1516 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1517 NoEncode<"$ea_result">;
1521 // Indexed (r+r) Loads.
1523 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1524 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1525 "lbzx $rD, $src", IIC_LdStLoad,
1526 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1527 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1528 "lhax $rD, $src", IIC_LdStLHA,
1529 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1530 PPC970_DGroup_Cracked;
1531 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1532 "lhzx $rD, $src", IIC_LdStLoad,
1533 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1534 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1535 "lwzx $rD, $src", IIC_LdStLoad,
1536 [(set i32:$rD, (load xaddr:$src))]>;
1539 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1540 "lhbrx $rD, $src", IIC_LdStLoad,
1541 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1542 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1543 "lwbrx $rD, $src", IIC_LdStLoad,
1544 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1546 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1547 "lfsx $frD, $src", IIC_LdStLFD,
1548 [(set f32:$frD, (load xaddr:$src))]>;
1549 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1550 "lfdx $frD, $src", IIC_LdStLFD,
1551 [(set f64:$frD, (load xaddr:$src))]>;
1553 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1554 "lfiwax $frD, $src", IIC_LdStLFD,
1555 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1556 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1557 "lfiwzx $frD, $src", IIC_LdStLFD,
1558 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1562 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1563 "lmw $rD, $src", IIC_LdStLMW, []>;
1565 //===----------------------------------------------------------------------===//
1566 // PPC32 Store Instructions.
1569 // Unindexed (r+i) Stores.
1570 let PPC970_Unit = 2 in {
1571 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1572 "stb $rS, $src", IIC_LdStStore,
1573 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1574 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1575 "sth $rS, $src", IIC_LdStStore,
1576 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1577 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1578 "stw $rS, $src", IIC_LdStStore,
1579 [(store i32:$rS, iaddr:$src)]>;
1580 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1581 "stfs $rS, $dst", IIC_LdStSTFD,
1582 [(store f32:$rS, iaddr:$dst)]>;
1583 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1584 "stfd $rS, $dst", IIC_LdStSTFD,
1585 [(store f64:$rS, iaddr:$dst)]>;
1588 // Unindexed (r+i) Stores with Update (preinc).
1589 let PPC970_Unit = 2, mayStore = 1 in {
1590 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1591 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1592 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1593 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1594 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1595 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1596 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1597 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1598 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1599 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1600 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1601 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1602 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1603 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1604 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1607 // Patterns to match the pre-inc stores. We can't put the patterns on
1608 // the instruction definitions directly as ISel wants the address base
1609 // and offset to be separate operands, not a single complex operand.
1610 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1611 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1612 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1613 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1614 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1615 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1616 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1617 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1618 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1619 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1621 // Indexed (r+r) Stores.
1622 let PPC970_Unit = 2 in {
1623 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1624 "stbx $rS, $dst", IIC_LdStStore,
1625 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1626 PPC970_DGroup_Cracked;
1627 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1628 "sthx $rS, $dst", IIC_LdStStore,
1629 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1630 PPC970_DGroup_Cracked;
1631 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1632 "stwx $rS, $dst", IIC_LdStStore,
1633 [(store i32:$rS, xaddr:$dst)]>,
1634 PPC970_DGroup_Cracked;
1636 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1637 "sthbrx $rS, $dst", IIC_LdStStore,
1638 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1639 PPC970_DGroup_Cracked;
1640 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1641 "stwbrx $rS, $dst", IIC_LdStStore,
1642 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1643 PPC970_DGroup_Cracked;
1645 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1646 "stfiwx $frS, $dst", IIC_LdStSTFD,
1647 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1649 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1650 "stfsx $frS, $dst", IIC_LdStSTFD,
1651 [(store f32:$frS, xaddr:$dst)]>;
1652 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1653 "stfdx $frS, $dst", IIC_LdStSTFD,
1654 [(store f64:$frS, xaddr:$dst)]>;
1657 // Indexed (r+r) Stores with Update (preinc).
1658 let PPC970_Unit = 2, mayStore = 1 in {
1659 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1660 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1661 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1662 PPC970_DGroup_Cracked;
1663 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1664 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1665 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1666 PPC970_DGroup_Cracked;
1667 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1668 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1669 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1670 PPC970_DGroup_Cracked;
1671 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1672 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1673 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1674 PPC970_DGroup_Cracked;
1675 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1676 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1677 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1678 PPC970_DGroup_Cracked;
1681 // Patterns to match the pre-inc stores. We can't put the patterns on
1682 // the instruction definitions directly as ISel wants the address base
1683 // and offset to be separate operands, not a single complex operand.
1684 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1685 (STBUX $rS, $ptrreg, $ptroff)>;
1686 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1687 (STHUX $rS, $ptrreg, $ptroff)>;
1688 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1689 (STWUX $rS, $ptrreg, $ptroff)>;
1690 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1691 (STFSUX $rS, $ptrreg, $ptroff)>;
1692 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1693 (STFDUX $rS, $ptrreg, $ptroff)>;
1696 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1697 "stmw $rS, $dst", IIC_LdStLMW, []>;
1699 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1700 "sync $L", IIC_LdStSync, []>;
1702 let isCodeGenOnly = 1 in {
1703 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1704 "msync", IIC_LdStSync, []> {
1709 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1710 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1711 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1712 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1714 //===----------------------------------------------------------------------===//
1715 // PPC32 Arithmetic Instructions.
1718 let PPC970_Unit = 1 in { // FXU Operations.
1719 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1720 "addi $rD, $rA, $imm", IIC_IntSimple,
1721 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1722 let BaseName = "addic" in {
1723 let Defs = [CARRY] in
1724 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1725 "addic $rD, $rA, $imm", IIC_IntGeneral,
1726 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1727 RecFormRel, PPC970_DGroup_Cracked;
1728 let Defs = [CARRY, CR0] in
1729 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1730 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1731 []>, isDOT, RecFormRel;
1733 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1734 "addis $rD, $rA, $imm", IIC_IntSimple,
1735 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1736 let isCodeGenOnly = 1 in
1737 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1738 "la $rD, $sym($rA)", IIC_IntGeneral,
1739 [(set i32:$rD, (add i32:$rA,
1740 (PPClo tglobaladdr:$sym, 0)))]>;
1741 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1742 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1743 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1744 let Defs = [CARRY] in
1745 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1746 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1747 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1749 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1750 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1751 "li $rD, $imm", IIC_IntSimple,
1752 [(set i32:$rD, imm32SExt16:$imm)]>;
1753 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1754 "lis $rD, $imm", IIC_IntSimple,
1755 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1759 let PPC970_Unit = 1 in { // FXU Operations.
1760 let Defs = [CR0] in {
1761 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1762 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1763 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1765 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1766 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1767 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1770 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1771 "ori $dst, $src1, $src2", IIC_IntSimple,
1772 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1773 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1774 "oris $dst, $src1, $src2", IIC_IntSimple,
1775 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1776 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1777 "xori $dst, $src1, $src2", IIC_IntSimple,
1778 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1779 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1780 "xoris $dst, $src1, $src2", IIC_IntSimple,
1781 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1783 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1785 let isCodeGenOnly = 1 in {
1786 // The POWER6 and POWER7 have special group-terminating nops.
1787 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1788 "ori 1, 1, 0", IIC_IntSimple, []>;
1789 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1790 "ori 2, 2, 0", IIC_IntSimple, []>;
1793 let isCompare = 1, neverHasSideEffects = 1 in {
1794 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1795 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1796 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1797 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1801 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1802 let isCommutable = 1 in {
1803 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1804 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1805 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1806 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1807 "and", "$rA, $rS, $rB", IIC_IntSimple,
1808 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1810 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1811 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1812 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1813 let isCommutable = 1 in {
1814 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1815 "or", "$rA, $rS, $rB", IIC_IntSimple,
1816 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1817 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1818 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1819 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1821 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1822 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1823 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1824 let isCommutable = 1 in {
1825 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1826 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1827 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1828 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1829 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1830 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1832 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1833 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1834 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1835 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1836 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1837 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1838 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1839 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1840 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1843 let PPC970_Unit = 1 in { // FXU Operations.
1844 let neverHasSideEffects = 1 in {
1845 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1846 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1847 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1848 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1849 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1850 [(set i32:$rA, (ctlz i32:$rS))]>;
1851 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1852 "extsb", "$rA, $rS", IIC_IntSimple,
1853 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1854 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1855 "extsh", "$rA, $rS", IIC_IntSimple,
1856 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1858 let isCompare = 1, neverHasSideEffects = 1 in {
1859 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1860 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1861 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1862 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1865 let PPC970_Unit = 3 in { // FPU Operations.
1866 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1867 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1868 let isCompare = 1, neverHasSideEffects = 1 in {
1869 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1870 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1871 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1872 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1873 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1876 let Uses = [RM] in {
1877 let neverHasSideEffects = 1 in {
1878 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1879 "fctiw", "$frD, $frB", IIC_FPGeneral,
1881 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1882 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1883 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1885 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1886 "frsp", "$frD, $frB", IIC_FPGeneral,
1887 [(set f32:$frD, (fround f64:$frB))]>;
1889 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1890 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1891 "frin", "$frD, $frB", IIC_FPGeneral,
1892 [(set f64:$frD, (frnd f64:$frB))]>;
1893 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1894 "frin", "$frD, $frB", IIC_FPGeneral,
1895 [(set f32:$frD, (frnd f32:$frB))]>;
1898 let neverHasSideEffects = 1 in {
1899 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1900 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1901 "frip", "$frD, $frB", IIC_FPGeneral,
1902 [(set f64:$frD, (fceil f64:$frB))]>;
1903 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1904 "frip", "$frD, $frB", IIC_FPGeneral,
1905 [(set f32:$frD, (fceil f32:$frB))]>;
1906 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1907 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1908 "friz", "$frD, $frB", IIC_FPGeneral,
1909 [(set f64:$frD, (ftrunc f64:$frB))]>;
1910 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1911 "friz", "$frD, $frB", IIC_FPGeneral,
1912 [(set f32:$frD, (ftrunc f32:$frB))]>;
1913 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1914 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1915 "frim", "$frD, $frB", IIC_FPGeneral,
1916 [(set f64:$frD, (ffloor f64:$frB))]>;
1917 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1918 "frim", "$frD, $frB", IIC_FPGeneral,
1919 [(set f32:$frD, (ffloor f32:$frB))]>;
1921 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1922 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1923 [(set f64:$frD, (fsqrt f64:$frB))]>;
1924 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1925 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1926 [(set f32:$frD, (fsqrt f32:$frB))]>;
1931 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1932 /// often coalesced away and we don't want the dispatch group builder to think
1933 /// that they will fill slots (which could cause the load of a LSU reject to
1934 /// sneak into a d-group with a store).
1935 let neverHasSideEffects = 1 in
1936 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1937 "fmr", "$frD, $frB", IIC_FPGeneral,
1938 []>, // (set f32:$frD, f32:$frB)
1941 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1942 // These are artificially split into two different forms, for 4/8 byte FP.
1943 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1944 "fabs", "$frD, $frB", IIC_FPGeneral,
1945 [(set f32:$frD, (fabs f32:$frB))]>;
1946 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1947 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1948 "fabs", "$frD, $frB", IIC_FPGeneral,
1949 [(set f64:$frD, (fabs f64:$frB))]>;
1950 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1951 "fnabs", "$frD, $frB", IIC_FPGeneral,
1952 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1953 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1954 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1955 "fnabs", "$frD, $frB", IIC_FPGeneral,
1956 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1957 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1958 "fneg", "$frD, $frB", IIC_FPGeneral,
1959 [(set f32:$frD, (fneg f32:$frB))]>;
1960 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1961 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1962 "fneg", "$frD, $frB", IIC_FPGeneral,
1963 [(set f64:$frD, (fneg f64:$frB))]>;
1965 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1966 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1967 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1968 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1969 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1970 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1971 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1973 // Reciprocal estimates.
1974 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1975 "fre", "$frD, $frB", IIC_FPGeneral,
1976 [(set f64:$frD, (PPCfre f64:$frB))]>;
1977 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1978 "fres", "$frD, $frB", IIC_FPGeneral,
1979 [(set f32:$frD, (PPCfre f32:$frB))]>;
1980 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1981 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1982 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1983 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1984 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1985 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1988 // XL-Form instructions. condition register logical ops.
1990 let neverHasSideEffects = 1 in
1991 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1992 "mcrf $BF, $BFA", IIC_BrMCR>,
1993 PPC970_DGroup_First, PPC970_Unit_CRU;
1995 let isCommutable = 1 in {
1996 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1997 (ins crbitrc:$CRA, crbitrc:$CRB),
1998 "crand $CRD, $CRA, $CRB", IIC_BrCR,
1999 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2001 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2002 (ins crbitrc:$CRA, crbitrc:$CRB),
2003 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2004 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2006 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2007 (ins crbitrc:$CRA, crbitrc:$CRB),
2008 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2009 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2011 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2012 (ins crbitrc:$CRA, crbitrc:$CRB),
2013 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2014 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2016 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2017 (ins crbitrc:$CRA, crbitrc:$CRB),
2018 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2019 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2021 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2022 (ins crbitrc:$CRA, crbitrc:$CRB),
2023 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2024 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2027 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2028 (ins crbitrc:$CRA, crbitrc:$CRB),
2029 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2030 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2032 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2033 (ins crbitrc:$CRA, crbitrc:$CRB),
2034 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2035 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2037 let isCodeGenOnly = 1 in {
2038 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2039 "creqv $dst, $dst, $dst", IIC_BrCR,
2040 [(set i1:$dst, 1)]>;
2042 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2043 "crxor $dst, $dst, $dst", IIC_BrCR,
2044 [(set i1:$dst, 0)]>;
2046 let Defs = [CR1EQ], CRD = 6 in {
2047 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2048 "creqv 6, 6, 6", IIC_BrCR,
2051 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2052 "crxor 6, 6, 6", IIC_BrCR,
2057 // XFX-Form instructions. Instructions that deal with SPRs.
2060 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2061 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2062 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2063 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2065 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2066 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2068 let Uses = [CTR] in {
2069 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2070 "mfctr $rT", IIC_SprMFSPR>,
2071 PPC970_DGroup_First, PPC970_Unit_FXU;
2073 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2074 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2075 "mtctr $rS", IIC_SprMTSPR>,
2076 PPC970_DGroup_First, PPC970_Unit_FXU;
2078 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2079 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2080 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2081 "mtctr $rS", IIC_SprMTSPR>,
2082 PPC970_DGroup_First, PPC970_Unit_FXU;
2085 let Defs = [LR] in {
2086 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2087 "mtlr $rS", IIC_SprMTSPR>,
2088 PPC970_DGroup_First, PPC970_Unit_FXU;
2090 let Uses = [LR] in {
2091 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2092 "mflr $rT", IIC_SprMFSPR>,
2093 PPC970_DGroup_First, PPC970_Unit_FXU;
2096 let isCodeGenOnly = 1 in {
2097 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2098 // like a GPR on the PPC970. As such, copies in and out have the same
2099 // performance characteristics as an OR instruction.
2100 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2101 "mtspr 256, $rS", IIC_IntGeneral>,
2102 PPC970_DGroup_Single, PPC970_Unit_FXU;
2103 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2104 "mfspr $rT, 256", IIC_IntGeneral>,
2105 PPC970_DGroup_First, PPC970_Unit_FXU;
2107 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2108 (outs VRSAVERC:$reg), (ins gprc:$rS),
2109 "mtspr 256, $rS", IIC_IntGeneral>,
2110 PPC970_DGroup_Single, PPC970_Unit_FXU;
2111 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2112 (ins VRSAVERC:$reg),
2113 "mfspr $rT, 256", IIC_IntGeneral>,
2114 PPC970_DGroup_First, PPC970_Unit_FXU;
2117 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2118 // so we'll need to scavenge a register for it.
2120 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2121 "#SPILL_VRSAVE", []>;
2123 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2124 // spilled), so we'll need to scavenge a register for it.
2126 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2127 "#RESTORE_VRSAVE", []>;
2129 let neverHasSideEffects = 1 in {
2130 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2131 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2132 PPC970_DGroup_First, PPC970_Unit_CRU;
2134 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2135 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2136 PPC970_MicroCode, PPC970_Unit_CRU;
2138 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2139 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2140 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2141 PPC970_DGroup_First, PPC970_Unit_CRU;
2143 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2144 "mfcr $rT", IIC_SprMFCR>,
2145 PPC970_MicroCode, PPC970_Unit_CRU;
2146 } // neverHasSideEffects = 1
2148 // Pseudo instruction to perform FADD in round-to-zero mode.
2149 let usesCustomInserter = 1, Uses = [RM] in {
2150 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2151 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2154 // The above pseudo gets expanded to make use of the following instructions
2155 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2156 let Uses = [RM], Defs = [RM] in {
2157 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2158 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2159 PPC970_DGroup_Single, PPC970_Unit_FPU;
2160 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2161 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2162 PPC970_DGroup_Single, PPC970_Unit_FPU;
2163 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2164 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2165 PPC970_DGroup_Single, PPC970_Unit_FPU;
2167 let Uses = [RM] in {
2168 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2169 "mffs $rT", IIC_IntMFFS,
2170 [(set f64:$rT, (PPCmffs))]>,
2171 PPC970_DGroup_Single, PPC970_Unit_FPU;
2175 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2176 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2177 let isCommutable = 1 in
2178 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2179 "add", "$rT, $rA, $rB", IIC_IntSimple,
2180 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2181 let isCodeGenOnly = 1 in
2182 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2183 "add $rT, $rA, $rB", IIC_IntSimple,
2184 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2185 let isCommutable = 1 in
2186 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2187 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2188 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2189 PPC970_DGroup_Cracked;
2191 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2192 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2193 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2194 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2195 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2196 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2197 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2198 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2199 let isCommutable = 1 in {
2200 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2201 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2202 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2203 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2204 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2205 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2206 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2207 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2208 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2210 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2211 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2212 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2213 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2214 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2215 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2216 PPC970_DGroup_Cracked;
2217 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2218 "neg", "$rT, $rA", IIC_IntSimple,
2219 [(set i32:$rT, (ineg i32:$rA))]>;
2220 let Uses = [CARRY] in {
2221 let isCommutable = 1 in
2222 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2223 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2224 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2225 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2226 "addme", "$rT, $rA", IIC_IntGeneral,
2227 [(set i32:$rT, (adde i32:$rA, -1))]>;
2228 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2229 "addze", "$rT, $rA", IIC_IntGeneral,
2230 [(set i32:$rT, (adde i32:$rA, 0))]>;
2231 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2232 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2233 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2234 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2235 "subfme", "$rT, $rA", IIC_IntGeneral,
2236 [(set i32:$rT, (sube -1, i32:$rA))]>;
2237 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2238 "subfze", "$rT, $rA", IIC_IntGeneral,
2239 [(set i32:$rT, (sube 0, i32:$rA))]>;
2243 // A-Form instructions. Most of the instructions executed in the FPU are of
2246 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2247 let Uses = [RM] in {
2248 let isCommutable = 1 in {
2249 defm FMADD : AForm_1r<63, 29,
2250 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2251 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2252 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2253 defm FMADDS : AForm_1r<59, 29,
2254 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2255 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2256 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2257 defm FMSUB : AForm_1r<63, 28,
2258 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2259 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2261 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2262 defm FMSUBS : AForm_1r<59, 28,
2263 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2264 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2266 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2267 defm FNMADD : AForm_1r<63, 31,
2268 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2269 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2271 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2272 defm FNMADDS : AForm_1r<59, 31,
2273 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2274 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2276 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2277 defm FNMSUB : AForm_1r<63, 30,
2278 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2279 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2280 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2281 (fneg f64:$FRB))))]>;
2282 defm FNMSUBS : AForm_1r<59, 30,
2283 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2284 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2285 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2286 (fneg f32:$FRB))))]>;
2289 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2290 // having 4 of these, force the comparison to always be an 8-byte double (code
2291 // should use an FMRSD if the input comparison value really wants to be a float)
2292 // and 4/8 byte forms for the result and operand type..
2293 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2294 defm FSELD : AForm_1r<63, 23,
2295 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2296 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2297 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2298 defm FSELS : AForm_1r<63, 23,
2299 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2300 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2301 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2302 let Uses = [RM] in {
2303 let isCommutable = 1 in {
2304 defm FADD : AForm_2r<63, 21,
2305 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2306 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2307 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2308 defm FADDS : AForm_2r<59, 21,
2309 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2310 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2311 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2313 defm FDIV : AForm_2r<63, 18,
2314 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2315 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2316 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2317 defm FDIVS : AForm_2r<59, 18,
2318 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2319 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2320 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2321 let isCommutable = 1 in {
2322 defm FMUL : AForm_3r<63, 25,
2323 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2324 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2325 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2326 defm FMULS : AForm_3r<59, 25,
2327 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2328 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2329 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2331 defm FSUB : AForm_2r<63, 20,
2332 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2333 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2334 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2335 defm FSUBS : AForm_2r<59, 20,
2336 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2337 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2338 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2342 let neverHasSideEffects = 1 in {
2343 let PPC970_Unit = 1 in { // FXU Operations.
2345 def ISEL : AForm_4<31, 15,
2346 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2347 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2351 let PPC970_Unit = 1 in { // FXU Operations.
2352 // M-Form instructions. rotate and mask instructions.
2354 let isCommutable = 1 in {
2355 // RLWIMI can be commuted if the rotate amount is zero.
2356 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2357 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2358 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2359 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2360 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2362 let BaseName = "rlwinm" in {
2363 def RLWINM : MForm_2<21,
2364 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2365 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2368 def RLWINMo : MForm_2<21,
2369 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2370 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2371 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2373 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2374 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2375 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2378 } // neverHasSideEffects = 1
2380 //===----------------------------------------------------------------------===//
2381 // PowerPC Instruction Patterns
2384 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2385 def : Pat<(i32 imm:$imm),
2386 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2388 // Implement the 'not' operation with the NOR instruction.
2389 def i32not : OutPatFrag<(ops node:$in),
2391 def : Pat<(not i32:$in),
2394 // ADD an arbitrary immediate.
2395 def : Pat<(add i32:$in, imm:$imm),
2396 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2397 // OR an arbitrary immediate.
2398 def : Pat<(or i32:$in, imm:$imm),
2399 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2400 // XOR an arbitrary immediate.
2401 def : Pat<(xor i32:$in, imm:$imm),
2402 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2404 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2405 (SUBFIC $in, imm:$imm)>;
2408 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2409 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2410 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2411 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2414 def : Pat<(rotl i32:$in, i32:$sh),
2415 (RLWNM $in, $sh, 0, 31)>;
2416 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2417 (RLWINM $in, imm:$imm, 0, 31)>;
2420 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2421 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2424 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2425 (BL tglobaladdr:$dst)>;
2426 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2427 (BL texternalsym:$dst)>;
2430 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2431 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2433 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2434 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2436 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2437 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2441 // Hi and Lo for Darwin Global Addresses.
2442 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2443 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2444 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2445 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2446 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2447 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2448 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2449 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2450 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2451 (ADDIS $in, tglobaltlsaddr:$g)>;
2452 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2453 (ADDI $in, tglobaltlsaddr:$g)>;
2454 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2455 (ADDIS $in, tglobaladdr:$g)>;
2456 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2457 (ADDIS $in, tconstpool:$g)>;
2458 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2459 (ADDIS $in, tjumptable:$g)>;
2460 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2461 (ADDIS $in, tblockaddress:$g)>;
2463 // Support for thread-local storage.
2464 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2465 [(set i32:$rD, (PPCppc32GOT))]>;
2467 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2468 // This uses two output registers, the first as the real output, the second as a
2469 // temporary register, used internally in code generation.
2470 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2471 []>, NoEncode<"$rT">;
2473 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2476 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2477 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2478 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2480 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2483 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2484 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2487 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2488 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2491 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2492 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2495 (PPCgetTlsldAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2496 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2499 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2500 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2503 (PPCaddisDtprelHA i32:$reg,
2504 tglobaltlsaddr:$disp))]>;
2506 // Support for Position-independent code
2507 def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2510 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2511 // Get Global (GOT) Base Register offset, from the word immediately preceding
2512 // the function label.
2513 def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
2514 // Update the Global(GOT) Base Register with the above offset.
2515 def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2518 // Standard shifts. These are represented separately from the real shifts above
2519 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2521 def : Pat<(sra i32:$rS, i32:$rB),
2523 def : Pat<(srl i32:$rS, i32:$rB),
2525 def : Pat<(shl i32:$rS, i32:$rB),
2528 def : Pat<(zextloadi1 iaddr:$src),
2530 def : Pat<(zextloadi1 xaddr:$src),
2532 def : Pat<(extloadi1 iaddr:$src),
2534 def : Pat<(extloadi1 xaddr:$src),
2536 def : Pat<(extloadi8 iaddr:$src),
2538 def : Pat<(extloadi8 xaddr:$src),
2540 def : Pat<(extloadi16 iaddr:$src),
2542 def : Pat<(extloadi16 xaddr:$src),
2544 def : Pat<(f64 (extloadf32 iaddr:$src)),
2545 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2546 def : Pat<(f64 (extloadf32 xaddr:$src)),
2547 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2549 def : Pat<(f64 (fextend f32:$src)),
2550 (COPY_TO_REGCLASS $src, F8RC)>;
2552 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2553 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2555 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2556 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2557 (FNMSUB $A, $C, $B)>;
2558 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2559 (FNMSUB $A, $C, $B)>;
2560 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2561 (FNMSUBS $A, $C, $B)>;
2562 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2563 (FNMSUBS $A, $C, $B)>;
2565 // FCOPYSIGN's operand types need not agree.
2566 def : Pat<(fcopysign f64:$frB, f32:$frA),
2567 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2568 def : Pat<(fcopysign f32:$frB, f64:$frA),
2569 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2571 include "PPCInstrAltivec.td"
2572 include "PPCInstrSPE.td"
2573 include "PPCInstr64Bit.td"
2574 include "PPCInstrVSX.td"
2576 def crnot : OutPatFrag<(ops node:$in),
2578 def : Pat<(not i1:$in),
2581 // Patterns for arithmetic i1 operations.
2582 def : Pat<(add i1:$a, i1:$b),
2584 def : Pat<(sub i1:$a, i1:$b),
2586 def : Pat<(mul i1:$a, i1:$b),
2589 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2590 // (-1 is used to mean all bits set).
2591 def : Pat<(i1 -1), (CRSET)>;
2593 // i1 extensions, implemented in terms of isel.
2594 def : Pat<(i32 (zext i1:$in)),
2595 (SELECT_I4 $in, (LI 1), (LI 0))>;
2596 def : Pat<(i32 (sext i1:$in)),
2597 (SELECT_I4 $in, (LI -1), (LI 0))>;
2599 def : Pat<(i64 (zext i1:$in)),
2600 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2601 def : Pat<(i64 (sext i1:$in)),
2602 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2604 // FIXME: We should choose either a zext or a sext based on other constants
2606 def : Pat<(i32 (anyext i1:$in)),
2607 (SELECT_I4 $in, (LI 1), (LI 0))>;
2608 def : Pat<(i64 (anyext i1:$in)),
2609 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2611 // match setcc on i1 variables.
2612 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2614 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2616 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2618 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2620 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2622 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2624 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2626 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2628 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2630 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2633 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2634 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2635 // floating-point types.
2637 multiclass CRNotPat<dag pattern, dag result> {
2638 def : Pat<pattern, (crnot result)>;
2639 def : Pat<(not pattern), result>;
2641 // We can also fold the crnot into an extension:
2642 def : Pat<(i32 (zext pattern)),
2643 (SELECT_I4 result, (LI 0), (LI 1))>;
2644 def : Pat<(i32 (sext pattern)),
2645 (SELECT_I4 result, (LI 0), (LI -1))>;
2647 // We can also fold the crnot into an extension:
2648 def : Pat<(i64 (zext pattern)),
2649 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2650 def : Pat<(i64 (sext pattern)),
2651 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2653 // FIXME: We should choose either a zext or a sext based on other constants
2655 def : Pat<(i32 (anyext pattern)),
2656 (SELECT_I4 result, (LI 0), (LI 1))>;
2658 def : Pat<(i64 (anyext pattern)),
2659 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2662 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2663 // we need to write imm:$imm in the output patterns below, not just $imm, or
2664 // else the resulting matcher will not correctly add the immediate operand
2665 // (making it a register operand instead).
2668 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2669 OutPatFrag rfrag, OutPatFrag rfrag8> {
2670 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2672 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2674 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2675 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2676 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2677 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2679 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2681 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2683 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2684 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2685 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2686 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2689 // Note that we do all inversions below with i(32|64)not, instead of using
2690 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2691 // has 2-cycle latency.
2693 defm : ExtSetCCPat<SETEQ,
2694 PatFrag<(ops node:$in, node:$cc),
2695 (setcc $in, 0, $cc)>,
2696 OutPatFrag<(ops node:$in),
2697 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2698 OutPatFrag<(ops node:$in),
2699 (RLDICL (CNTLZD $in), 58, 63)> >;
2701 defm : ExtSetCCPat<SETNE,
2702 PatFrag<(ops node:$in, node:$cc),
2703 (setcc $in, 0, $cc)>,
2704 OutPatFrag<(ops node:$in),
2705 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2706 OutPatFrag<(ops node:$in),
2707 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2709 defm : ExtSetCCPat<SETLT,
2710 PatFrag<(ops node:$in, node:$cc),
2711 (setcc $in, 0, $cc)>,
2712 OutPatFrag<(ops node:$in),
2713 (RLWINM $in, 1, 31, 31)>,
2714 OutPatFrag<(ops node:$in),
2715 (RLDICL $in, 1, 63)> >;
2717 defm : ExtSetCCPat<SETGE,
2718 PatFrag<(ops node:$in, node:$cc),
2719 (setcc $in, 0, $cc)>,
2720 OutPatFrag<(ops node:$in),
2721 (RLWINM (i32not $in), 1, 31, 31)>,
2722 OutPatFrag<(ops node:$in),
2723 (RLDICL (i64not $in), 1, 63)> >;
2725 defm : ExtSetCCPat<SETGT,
2726 PatFrag<(ops node:$in, node:$cc),
2727 (setcc $in, 0, $cc)>,
2728 OutPatFrag<(ops node:$in),
2729 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2730 OutPatFrag<(ops node:$in),
2731 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2733 defm : ExtSetCCPat<SETLE,
2734 PatFrag<(ops node:$in, node:$cc),
2735 (setcc $in, 0, $cc)>,
2736 OutPatFrag<(ops node:$in),
2737 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2738 OutPatFrag<(ops node:$in),
2739 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2741 defm : ExtSetCCPat<SETLT,
2742 PatFrag<(ops node:$in, node:$cc),
2743 (setcc $in, -1, $cc)>,
2744 OutPatFrag<(ops node:$in),
2745 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2746 OutPatFrag<(ops node:$in),
2747 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2749 defm : ExtSetCCPat<SETGE,
2750 PatFrag<(ops node:$in, node:$cc),
2751 (setcc $in, -1, $cc)>,
2752 OutPatFrag<(ops node:$in),
2753 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2754 OutPatFrag<(ops node:$in),
2755 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2757 defm : ExtSetCCPat<SETGT,
2758 PatFrag<(ops node:$in, node:$cc),
2759 (setcc $in, -1, $cc)>,
2760 OutPatFrag<(ops node:$in),
2761 (RLWINM (i32not $in), 1, 31, 31)>,
2762 OutPatFrag<(ops node:$in),
2763 (RLDICL (i64not $in), 1, 63)> >;
2765 defm : ExtSetCCPat<SETLE,
2766 PatFrag<(ops node:$in, node:$cc),
2767 (setcc $in, -1, $cc)>,
2768 OutPatFrag<(ops node:$in),
2769 (RLWINM $in, 1, 31, 31)>,
2770 OutPatFrag<(ops node:$in),
2771 (RLDICL $in, 1, 63)> >;
2774 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2775 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2776 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2777 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2778 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2779 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2780 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2781 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2782 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2783 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2784 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2785 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2787 // For non-equality comparisons, the default code would materialize the
2788 // constant, then compare against it, like this:
2790 // ori r2, r2, 22136
2793 // Since we are just comparing for equality, we can emit this instead:
2794 // xoris r0,r3,0x1234
2795 // cmplwi cr0,r0,0x5678
2798 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2799 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2800 (LO16 imm:$imm)), sub_eq)>;
2802 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2803 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2804 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2805 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2806 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2807 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2808 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2809 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2810 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2811 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2812 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2813 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2815 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2816 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2817 (LO16 imm:$imm)), sub_eq)>;
2819 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2820 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2821 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2822 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2823 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2824 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2825 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2826 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2827 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2828 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2830 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2831 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2832 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2833 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2834 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2835 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2836 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2837 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2838 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2839 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2842 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2843 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2844 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2845 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2846 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2847 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2848 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2849 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2850 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2851 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2852 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2853 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2855 // For non-equality comparisons, the default code would materialize the
2856 // constant, then compare against it, like this:
2858 // ori r2, r2, 22136
2861 // Since we are just comparing for equality, we can emit this instead:
2862 // xoris r0,r3,0x1234
2863 // cmpldi cr0,r0,0x5678
2866 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2867 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2868 (LO16 imm:$imm)), sub_eq)>;
2870 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2871 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2872 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2873 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2874 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2875 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2876 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2877 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2878 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2879 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2880 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2881 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2883 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2884 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2885 (LO16 imm:$imm)), sub_eq)>;
2887 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2888 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2889 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2890 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2891 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2892 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2893 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2894 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2895 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2896 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2898 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2899 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2900 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2901 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2902 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2903 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2904 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2905 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2906 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2907 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2910 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2911 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2912 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2913 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2914 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2915 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2916 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2917 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2918 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2919 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2920 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2921 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2922 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2923 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2925 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2926 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2927 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2928 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2929 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2930 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2931 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2932 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2933 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2934 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2935 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2936 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2937 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2938 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2941 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2942 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2943 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2944 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2945 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2946 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2947 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2948 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2949 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2950 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2951 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2952 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2953 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2954 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2956 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2957 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2958 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2959 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2960 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2961 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2962 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2963 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2964 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2965 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2966 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2967 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2968 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2969 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2971 // match select on i1 variables:
2972 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2973 (CROR (CRAND $cond , $tval),
2974 (CRAND (crnot $cond), $fval))>;
2976 // match selectcc on i1 variables:
2977 // select (lhs == rhs), tval, fval is:
2978 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2979 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2980 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2981 (CRAND (CRORC $lhs, $rhs), $fval))>;
2982 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2983 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2984 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2985 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2986 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2987 (CRAND (CRXOR $lhs, $rhs), $fval))>;
2988 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
2989 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
2990 (CRAND (CRANDC $rhs, $lhs), $fval))>;
2991 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
2992 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
2993 (CRAND (CRORC $rhs, $lhs), $fval))>;
2994 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
2995 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
2996 (CRAND (CRXOR $lhs, $rhs), $tval))>;
2998 // match selectcc on i1 variables with non-i1 output.
2999 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3000 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3001 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3002 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3003 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3004 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3005 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3006 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3007 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3008 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3009 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3010 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3012 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3013 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3014 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3015 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3016 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3017 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3018 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3019 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3020 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3021 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3022 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3023 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3025 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3026 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3027 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3028 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3029 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3030 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3031 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3032 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3033 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3034 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3035 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3036 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3038 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3039 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3040 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3041 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3042 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3043 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3044 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3045 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3046 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3047 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3048 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3049 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3051 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3052 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3053 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3054 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3055 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3056 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3057 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3058 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3059 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3060 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3061 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3062 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3064 let usesCustomInserter = 1 in {
3065 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3067 [(set i1:$dst, (trunc (not i32:$in)))]>;
3068 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3070 [(set i1:$dst, (trunc i32:$in))]>;
3072 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3074 [(set i1:$dst, (trunc (not i64:$in)))]>;
3075 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3077 [(set i1:$dst, (trunc i64:$in))]>;
3080 def : Pat<(i1 (not (trunc i32:$in))),
3081 (ANDIo_1_EQ_BIT $in)>;
3082 def : Pat<(i1 (not (trunc i64:$in))),
3083 (ANDIo_1_EQ_BIT8 $in)>;
3085 //===----------------------------------------------------------------------===//
3086 // PowerPC Instructions used for assembler/disassembler only
3089 // FIXME: For B=0 or B > 8, the registers following RT are used.
3090 // WARNING: Do not add patterns for this instruction without fixing this.
3091 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3092 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3094 // FIXME: For B=0 or B > 8, the registers following RT are used.
3095 // WARNING: Do not add patterns for this instruction without fixing this.
3096 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3097 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3099 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3100 "isync", IIC_SprISYNC, []>;
3102 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3103 "icbi $src", IIC_LdStICBI, []>;
3105 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3106 "eieio", IIC_LdStLoad, []>;
3108 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3109 "wait $L", IIC_LdStLoad, []>;
3111 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3112 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3114 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3115 "mtsr $SR, $RS", IIC_SprMTSR>;
3117 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3118 "mfsr $RS, $SR", IIC_SprMFSR>;
3120 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3121 "mtsrin $RS, $RB", IIC_SprMTSR>;
3123 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3124 "mfsrin $RS, $RB", IIC_SprMFSR>;
3126 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3127 "mtmsr $RS, $L", IIC_SprMTMSR>;
3129 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3130 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3134 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3135 Requires<[IsBookE]> {
3139 let Inst{21-30} = 163;
3142 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3143 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3144 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3145 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3147 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3148 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3149 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3150 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3152 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3153 "mfmsr $RT", IIC_SprMFMSR, []>;
3155 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3156 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3158 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3159 "slbie $RB", IIC_SprSLBIE, []>;
3161 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3162 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3164 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3165 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3167 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3169 def TLBIA : XForm_0<31, 370, (outs), (ins),
3170 "tlbia", IIC_SprTLBIA, []>;
3172 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3173 "tlbsync", IIC_SprTLBSYNC, []>;
3175 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3176 "tlbiel $RB", IIC_SprTLBIEL, []>;
3178 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3179 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3180 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3181 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3183 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3184 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3186 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3187 IIC_LdStLoad>, Requires<[IsBookE]>;
3189 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3190 IIC_LdStLoad>, Requires<[IsBookE]>;
3192 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3193 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3195 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3196 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3198 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3199 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3201 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3202 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3204 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3205 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3206 Requires<[IsPPC4xx]>;
3207 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3208 (ins gprc:$RST, gprc:$A, gprc:$B),
3209 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3210 Requires<[IsPPC4xx]>, isDOT;
3212 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3214 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3215 Requires<[IsBookE]>;
3216 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3217 Requires<[IsBookE]>;
3219 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3221 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3224 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3225 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3226 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3227 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3229 //===----------------------------------------------------------------------===//
3230 // PowerPC Assembler Instruction Aliases
3233 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3234 // These are aliases that require C++ handling to convert to the target
3235 // instruction, while InstAliases can be handled directly by tblgen.
3236 class PPCAsmPseudo<string asm, dag iops>
3238 let Namespace = "PPC";
3239 bit PPC64 = 0; // Default value, override with isPPC64
3241 let OutOperandList = (outs);
3242 let InOperandList = iops;
3244 let AsmString = asm;
3245 let isAsmParserOnly = 1;
3249 def : InstAlias<"sc", (SC 0)>;
3251 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3252 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3253 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3254 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3256 def : InstAlias<"wait", (WAIT 0)>;
3257 def : InstAlias<"waitrsv", (WAIT 1)>;
3258 def : InstAlias<"waitimpl", (WAIT 2)>;
3260 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3262 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3263 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3264 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3265 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3267 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3268 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3270 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3271 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3273 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3274 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3276 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3277 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3279 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3280 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3282 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3283 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3285 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3286 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3288 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3289 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3291 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3292 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3294 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3295 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3297 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3298 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3300 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3301 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3303 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3304 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3306 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3307 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3309 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3310 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3311 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3313 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3314 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3316 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3317 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3318 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3319 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3321 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3323 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3324 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3326 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3327 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3329 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3331 foreach BATR = 0-3 in {
3332 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3333 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3334 Requires<[IsPPC6xx]>;
3335 def : InstAlias<"mfdbatu $Rx, "#BATR,
3336 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3337 Requires<[IsPPC6xx]>;
3338 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3339 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3340 Requires<[IsPPC6xx]>;
3341 def : InstAlias<"mfdbatl $Rx, "#BATR,
3342 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3343 Requires<[IsPPC6xx]>;
3344 def : InstAlias<"mtibatu "#BATR#", $Rx",
3345 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3346 Requires<[IsPPC6xx]>;
3347 def : InstAlias<"mfibatu $Rx, "#BATR,
3348 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3349 Requires<[IsPPC6xx]>;
3350 def : InstAlias<"mtibatl "#BATR#", $Rx",
3351 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3352 Requires<[IsPPC6xx]>;
3353 def : InstAlias<"mfibatl $Rx, "#BATR,
3354 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3355 Requires<[IsPPC6xx]>;
3358 foreach BR = 0-7 in {
3359 def : InstAlias<"mfbr"#BR#" $Rx",
3360 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3361 Requires<[IsPPC4xx]>;
3362 def : InstAlias<"mtbr"#BR#" $Rx",
3363 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3364 Requires<[IsPPC4xx]>;
3367 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3368 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3370 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3371 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3373 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3374 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3376 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3377 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3379 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3380 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3382 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3383 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3385 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3387 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3388 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3389 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3390 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3391 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3392 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3393 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3394 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3396 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3397 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3398 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3399 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3401 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3402 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3404 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3405 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3407 foreach SPRG = 0-3 in {
3408 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3409 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3410 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3411 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3413 foreach SPRG = 4-7 in {
3414 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3415 Requires<[IsBookE]>;
3416 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3417 Requires<[IsBookE]>;
3418 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3419 Requires<[IsBookE]>;
3420 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3421 Requires<[IsBookE]>;
3424 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3426 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3427 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3429 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3431 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3432 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3434 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3435 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3436 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3437 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3439 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3441 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3442 Requires<[IsPPC4xx]>;
3443 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3444 Requires<[IsPPC4xx]>;
3445 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3446 Requires<[IsPPC4xx]>;
3447 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3448 Requires<[IsPPC4xx]>;
3450 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3451 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3452 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3453 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3454 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3455 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3456 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3457 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3458 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3459 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3460 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3461 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3462 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3463 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3464 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3465 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3466 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3467 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3468 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3469 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3470 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3471 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3472 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3473 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3474 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3475 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3476 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3477 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3478 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3479 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3480 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3481 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3482 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3483 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3484 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3485 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3487 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3488 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3489 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3490 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3491 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3492 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3494 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3495 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3496 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3497 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3498 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3499 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3500 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3501 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3502 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3503 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3504 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3505 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3506 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3507 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3508 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3509 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3510 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3511 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3512 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3513 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3514 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3515 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3516 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3517 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3518 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3519 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3520 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3521 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3522 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3523 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3524 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3525 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3527 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3528 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3529 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3530 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3531 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3532 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3534 // These generic branch instruction forms are used for the assembler parser only.
3535 // Defs and Uses are conservative, since we don't know the BO value.
3536 let PPC970_Unit = 7 in {
3537 let Defs = [CTR], Uses = [CTR, RM] in {
3538 def gBC : BForm_3<16, 0, 0, (outs),
3539 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3540 "bc $bo, $bi, $dst">;
3541 def gBCA : BForm_3<16, 1, 0, (outs),
3542 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3543 "bca $bo, $bi, $dst">;
3545 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3546 def gBCL : BForm_3<16, 0, 1, (outs),
3547 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3548 "bcl $bo, $bi, $dst">;
3549 def gBCLA : BForm_3<16, 1, 1, (outs),
3550 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3551 "bcla $bo, $bi, $dst">;
3553 let Defs = [CTR], Uses = [CTR, LR, RM] in
3554 def gBCLR : XLForm_2<19, 16, 0, (outs),
3555 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3556 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3557 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3558 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3559 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3560 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3561 let Defs = [CTR], Uses = [CTR, LR, RM] in
3562 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3563 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3564 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3565 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3566 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3567 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3568 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3570 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3571 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3572 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3573 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3575 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3576 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3577 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3578 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3579 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3580 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3581 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3583 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3584 : BranchSimpleMnemonic1<name, pm, bo> {
3585 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3586 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3588 defm : BranchSimpleMnemonic2<"t", "", 12>;
3589 defm : BranchSimpleMnemonic2<"f", "", 4>;
3590 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3591 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3592 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3593 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3594 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3595 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3596 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3597 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3599 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3600 def : InstAlias<"b"#name#pm#" $cc, $dst",
3601 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3602 def : InstAlias<"b"#name#pm#" $dst",
3603 (BCC bibo, CR0, condbrtarget:$dst)>;
3605 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3606 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3607 def : InstAlias<"b"#name#"a"#pm#" $dst",
3608 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3610 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3611 (BCCLR bibo, crrc:$cc)>;
3612 def : InstAlias<"b"#name#"lr"#pm,
3615 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3616 (BCCCTR bibo, crrc:$cc)>;
3617 def : InstAlias<"b"#name#"ctr"#pm,
3618 (BCCCTR bibo, CR0)>;
3620 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3621 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3622 def : InstAlias<"b"#name#"l"#pm#" $dst",
3623 (BCCL bibo, CR0, condbrtarget:$dst)>;
3625 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3626 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3627 def : InstAlias<"b"#name#"la"#pm#" $dst",
3628 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3630 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3631 (BCCLRL bibo, crrc:$cc)>;
3632 def : InstAlias<"b"#name#"lrl"#pm,
3633 (BCCLRL bibo, CR0)>;
3635 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3636 (BCCCTRL bibo, crrc:$cc)>;
3637 def : InstAlias<"b"#name#"ctrl"#pm,
3638 (BCCCTRL bibo, CR0)>;
3640 multiclass BranchExtendedMnemonic<string name, int bibo> {
3641 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3642 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3643 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3645 defm : BranchExtendedMnemonic<"lt", 12>;
3646 defm : BranchExtendedMnemonic<"gt", 44>;
3647 defm : BranchExtendedMnemonic<"eq", 76>;
3648 defm : BranchExtendedMnemonic<"un", 108>;
3649 defm : BranchExtendedMnemonic<"so", 108>;
3650 defm : BranchExtendedMnemonic<"ge", 4>;
3651 defm : BranchExtendedMnemonic<"nl", 4>;
3652 defm : BranchExtendedMnemonic<"le", 36>;
3653 defm : BranchExtendedMnemonic<"ng", 36>;
3654 defm : BranchExtendedMnemonic<"ne", 68>;
3655 defm : BranchExtendedMnemonic<"nu", 100>;
3656 defm : BranchExtendedMnemonic<"ns", 100>;
3658 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3659 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3660 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3661 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3662 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3663 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3664 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3665 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3667 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3668 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3669 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3670 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3671 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3672 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3673 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3674 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3676 multiclass TrapExtendedMnemonic<string name, int to> {
3677 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3678 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3679 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3680 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3682 defm : TrapExtendedMnemonic<"lt", 16>;
3683 defm : TrapExtendedMnemonic<"le", 20>;
3684 defm : TrapExtendedMnemonic<"eq", 4>;
3685 defm : TrapExtendedMnemonic<"ge", 12>;
3686 defm : TrapExtendedMnemonic<"gt", 8>;
3687 defm : TrapExtendedMnemonic<"nl", 12>;
3688 defm : TrapExtendedMnemonic<"ne", 24>;
3689 defm : TrapExtendedMnemonic<"ng", 20>;
3690 defm : TrapExtendedMnemonic<"llt", 2>;
3691 defm : TrapExtendedMnemonic<"lle", 6>;
3692 defm : TrapExtendedMnemonic<"lge", 5>;
3693 defm : TrapExtendedMnemonic<"lgt", 1>;
3694 defm : TrapExtendedMnemonic<"lnl", 5>;
3695 defm : TrapExtendedMnemonic<"lng", 6>;
3696 defm : TrapExtendedMnemonic<"u", 31>;
3699 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3700 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3701 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3702 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3703 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3704 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3707 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3708 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3709 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3710 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3711 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3712 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;