1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
50 SDTCisPtrTy<0>, SDTCisVT<1, i32>
53 def tocentry32 : Operand<iPTR> {
54 let MIOperandInfo = (ops i32imm:$imm);
57 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [
58 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
60 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [
61 SDTCisVec<0>, SDTCisInt<1>
63 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [
64 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
66 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [
67 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
70 def SDT_PPCqbflt : SDTypeProfile<1, 1, [
71 SDTCisVec<0>, SDTCisVec<1>
74 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
75 SDTCisVec<0>, SDTCisPtrTy<1>
78 //===----------------------------------------------------------------------===//
79 // PowerPC specific DAG Nodes.
82 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
83 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
85 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
86 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
87 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
88 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
89 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
90 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
91 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
92 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
93 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
94 [SDNPHasChain, SDNPMayStore]>;
95 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
96 [SDNPHasChain, SDNPMayLoad]>;
97 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
98 [SDNPHasChain, SDNPMayLoad]>;
100 // Extract FPSCR (not modeled at the DAG level).
101 def PPCmffs : SDNode<"PPCISD::MFFS",
102 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
104 // Perform FADD in round-to-zero mode.
105 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
108 def PPCfsel : SDNode<"PPCISD::FSEL",
109 // Type constraint for fsel.
110 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
111 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
113 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
114 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
115 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
116 [SDNPMayLoad, SDNPMemOperand]>;
117 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
118 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
120 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
122 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
123 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
125 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
126 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
127 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
128 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
129 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
130 SDTypeProfile<1, 3, [
131 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
132 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
133 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
134 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
135 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
136 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
137 SDTypeProfile<1, 3, [
138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
139 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
140 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
141 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
143 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
145 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
146 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
147 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
148 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
150 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
152 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
153 [SDNPHasChain, SDNPMayLoad]>;
155 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
157 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
158 // amounts. These nodes are generated by the multi-precision shift code.
159 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
160 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
161 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
163 // These are target-independent nodes, but have target-specific formats.
164 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
165 [SDNPHasChain, SDNPOutGlue]>;
166 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
169 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
170 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
171 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
173 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
176 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
177 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
178 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
179 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
181 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
182 SDTypeProfile<0, 1, []>,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
186 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
187 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
189 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
190 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
192 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
193 SDTypeProfile<1, 1, [SDTCisInt<0>,
195 [SDNPHasChain, SDNPSideEffect]>;
196 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
197 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
198 [SDNPHasChain, SDNPSideEffect]>;
200 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
201 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
202 [SDNPHasChain, SDNPSideEffect]>;
204 def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone,
205 [SDNPHasChain, SDNPSideEffect]>;
206 def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
207 def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
208 [SDNPHasChain, SDNPSideEffect]>;
210 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
211 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
213 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
214 [SDNPHasChain, SDNPOptInGlue]>;
216 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
217 [SDNPHasChain, SDNPMayLoad]>;
218 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
219 [SDNPHasChain, SDNPMayStore]>;
221 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
222 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
223 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
224 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
225 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
227 // Instructions to support dynamic alloca.
228 def SDTDynOp : SDTypeProfile<1, 2, []>;
229 def SDTDynAreaOp : SDTypeProfile<1, 1, []>;
230 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
231 def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
233 //===----------------------------------------------------------------------===//
234 // PowerPC specific transformation functions and pattern fragments.
237 def SHL32 : SDNodeXForm<imm, [{
238 // Transformation function: 31 - imm
239 return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
242 def SRL32 : SDNodeXForm<imm, [{
243 // Transformation function: 32 - imm
244 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
245 : getI32Imm(0, SDLoc(N));
248 def LO16 : SDNodeXForm<imm, [{
249 // Transformation function: get the low 16 bits.
250 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
253 def HI16 : SDNodeXForm<imm, [{
254 // Transformation function: shift the immediate value down into the low bits.
255 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
258 def HA16 : SDNodeXForm<imm, [{
259 // Transformation function: shift the immediate value down into the low bits.
260 signed int Val = N->getZExtValue();
261 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
263 def MB : SDNodeXForm<imm, [{
264 // Transformation function: get the start bit of a mask
266 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
267 return getI32Imm(mb, SDLoc(N));
270 def ME : SDNodeXForm<imm, [{
271 // Transformation function: get the end bit of a mask
273 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
274 return getI32Imm(me, SDLoc(N));
276 def maskimm32 : PatLeaf<(imm), [{
277 // maskImm predicate - True if immediate is a run of ones.
279 if (N->getValueType(0) == MVT::i32)
280 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
285 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
286 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
287 // sign extended field. Used by instructions like 'addi'.
288 return (int32_t)Imm == (short)Imm;
290 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
291 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
292 // sign extended field. Used by instructions like 'addi'.
293 return (int64_t)Imm == (short)Imm;
295 def immZExt16 : PatLeaf<(imm), [{
296 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
297 // field. Used by instructions like 'ori'.
298 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
301 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
302 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
303 // identical in 32-bit mode, but in 64-bit mode, they return true if the
304 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
306 def imm16ShiftedZExt : PatLeaf<(imm), [{
307 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
308 // immediate are set. Used by instructions like 'xoris'.
309 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
312 def imm16ShiftedSExt : PatLeaf<(imm), [{
313 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
314 // immediate are set. Used by instructions like 'addis'. Identical to
315 // imm16ShiftedZExt in 32-bit mode.
316 if (N->getZExtValue() & 0xFFFF) return false;
317 if (N->getValueType(0) == MVT::i32)
319 // For 64-bit, make sure it is sext right.
320 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
323 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
324 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
325 // zero extended field.
326 return isUInt<32>(Imm);
329 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
330 // restricted memrix (4-aligned) constants are alignment sensitive. If these
331 // offsets are hidden behind TOC entries than the values of the lower-order
332 // bits cannot be checked directly. As a result, we need to also incorporate
333 // an alignment check into the relevant patterns.
335 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
336 return cast<LoadSDNode>(N)->getAlignment() >= 4;
338 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
339 (store node:$val, node:$ptr), [{
340 return cast<StoreSDNode>(N)->getAlignment() >= 4;
342 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
343 return cast<LoadSDNode>(N)->getAlignment() >= 4;
345 def aligned4pre_store : PatFrag<
346 (ops node:$val, node:$base, node:$offset),
347 (pre_store node:$val, node:$base, node:$offset), [{
348 return cast<StoreSDNode>(N)->getAlignment() >= 4;
351 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
352 return cast<LoadSDNode>(N)->getAlignment() < 4;
354 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
355 (store node:$val, node:$ptr), [{
356 return cast<StoreSDNode>(N)->getAlignment() < 4;
358 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
359 return cast<LoadSDNode>(N)->getAlignment() < 4;
362 //===----------------------------------------------------------------------===//
363 // PowerPC Flag Definitions.
365 class isPPC64 { bit PPC64 = 1; }
366 class isDOT { bit RC = 1; }
368 class RegConstraint<string C> {
369 string Constraints = C;
371 class NoEncode<string E> {
372 string DisableEncoding = E;
376 //===----------------------------------------------------------------------===//
377 // PowerPC Operand Definitions.
379 // In the default PowerPC assembler syntax, registers are specified simply
380 // by number, so they cannot be distinguished from immediate values (without
381 // looking at the opcode). This means that the default operand matching logic
382 // for the asm parser does not work, and we need to specify custom matchers.
383 // Since those can only be specified with RegisterOperand classes and not
384 // directly on the RegisterClass, all instructions patterns used by the asm
385 // parser need to use a RegisterOperand (instead of a RegisterClass) for
386 // all their register operands.
387 // For this purpose, we define one RegisterOperand for each RegisterClass,
388 // using the same name as the class, just in lower case.
390 def PPCRegGPRCAsmOperand : AsmOperandClass {
391 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
393 def gprc : RegisterOperand<GPRC> {
394 let ParserMatchClass = PPCRegGPRCAsmOperand;
396 def PPCRegG8RCAsmOperand : AsmOperandClass {
397 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
399 def g8rc : RegisterOperand<G8RC> {
400 let ParserMatchClass = PPCRegG8RCAsmOperand;
402 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
403 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
405 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
406 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
408 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
409 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
411 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
412 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
414 def PPCRegF8RCAsmOperand : AsmOperandClass {
415 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
417 def f8rc : RegisterOperand<F8RC> {
418 let ParserMatchClass = PPCRegF8RCAsmOperand;
420 def PPCRegF4RCAsmOperand : AsmOperandClass {
421 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
423 def f4rc : RegisterOperand<F4RC> {
424 let ParserMatchClass = PPCRegF4RCAsmOperand;
426 def PPCRegVRRCAsmOperand : AsmOperandClass {
427 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
429 def vrrc : RegisterOperand<VRRC> {
430 let ParserMatchClass = PPCRegVRRCAsmOperand;
432 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
433 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
435 def crbitrc : RegisterOperand<CRBITRC> {
436 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
438 def PPCRegCRRCAsmOperand : AsmOperandClass {
439 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
441 def crrc : RegisterOperand<CRRC> {
442 let ParserMatchClass = PPCRegCRRCAsmOperand;
444 def crrc0 : RegisterOperand<CRRC0> {
445 let ParserMatchClass = PPCRegCRRCAsmOperand;
448 def PPCU1ImmAsmOperand : AsmOperandClass {
449 let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
450 let RenderMethod = "addImmOperands";
452 def u1imm : Operand<i32> {
453 let PrintMethod = "printU1ImmOperand";
454 let ParserMatchClass = PPCU1ImmAsmOperand;
457 def PPCU2ImmAsmOperand : AsmOperandClass {
458 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
459 let RenderMethod = "addImmOperands";
461 def u2imm : Operand<i32> {
462 let PrintMethod = "printU2ImmOperand";
463 let ParserMatchClass = PPCU2ImmAsmOperand;
466 def PPCU3ImmAsmOperand : AsmOperandClass {
467 let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
468 let RenderMethod = "addImmOperands";
470 def u3imm : Operand<i32> {
471 let PrintMethod = "printU3ImmOperand";
472 let ParserMatchClass = PPCU3ImmAsmOperand;
475 def PPCU4ImmAsmOperand : AsmOperandClass {
476 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
477 let RenderMethod = "addImmOperands";
479 def u4imm : Operand<i32> {
480 let PrintMethod = "printU4ImmOperand";
481 let ParserMatchClass = PPCU4ImmAsmOperand;
483 def PPCS5ImmAsmOperand : AsmOperandClass {
484 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
485 let RenderMethod = "addImmOperands";
487 def s5imm : Operand<i32> {
488 let PrintMethod = "printS5ImmOperand";
489 let ParserMatchClass = PPCS5ImmAsmOperand;
490 let DecoderMethod = "decodeSImmOperand<5>";
492 def PPCU5ImmAsmOperand : AsmOperandClass {
493 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
494 let RenderMethod = "addImmOperands";
496 def u5imm : Operand<i32> {
497 let PrintMethod = "printU5ImmOperand";
498 let ParserMatchClass = PPCU5ImmAsmOperand;
499 let DecoderMethod = "decodeUImmOperand<5>";
501 def PPCU6ImmAsmOperand : AsmOperandClass {
502 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
503 let RenderMethod = "addImmOperands";
505 def u6imm : Operand<i32> {
506 let PrintMethod = "printU6ImmOperand";
507 let ParserMatchClass = PPCU6ImmAsmOperand;
508 let DecoderMethod = "decodeUImmOperand<6>";
510 def PPCU10ImmAsmOperand : AsmOperandClass {
511 let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
512 let RenderMethod = "addImmOperands";
514 def u10imm : Operand<i32> {
515 let PrintMethod = "printU10ImmOperand";
516 let ParserMatchClass = PPCU10ImmAsmOperand;
517 let DecoderMethod = "decodeUImmOperand<10>";
519 def PPCU12ImmAsmOperand : AsmOperandClass {
520 let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
521 let RenderMethod = "addImmOperands";
523 def u12imm : Operand<i32> {
524 let PrintMethod = "printU12ImmOperand";
525 let ParserMatchClass = PPCU12ImmAsmOperand;
526 let DecoderMethod = "decodeUImmOperand<12>";
528 def PPCS16ImmAsmOperand : AsmOperandClass {
529 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
530 let RenderMethod = "addS16ImmOperands";
532 def s16imm : Operand<i32> {
533 let PrintMethod = "printS16ImmOperand";
534 let EncoderMethod = "getImm16Encoding";
535 let ParserMatchClass = PPCS16ImmAsmOperand;
536 let DecoderMethod = "decodeSImmOperand<16>";
538 def PPCU16ImmAsmOperand : AsmOperandClass {
539 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
540 let RenderMethod = "addU16ImmOperands";
542 def u16imm : Operand<i32> {
543 let PrintMethod = "printU16ImmOperand";
544 let EncoderMethod = "getImm16Encoding";
545 let ParserMatchClass = PPCU16ImmAsmOperand;
546 let DecoderMethod = "decodeUImmOperand<16>";
548 def PPCS17ImmAsmOperand : AsmOperandClass {
549 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
550 let RenderMethod = "addS16ImmOperands";
552 def s17imm : Operand<i32> {
553 // This operand type is used for addis/lis to allow the assembler parser
554 // to accept immediates in the range -65536..65535 for compatibility with
555 // the GNU assembler. The operand is treated as 16-bit otherwise.
556 let PrintMethod = "printS16ImmOperand";
557 let EncoderMethod = "getImm16Encoding";
558 let ParserMatchClass = PPCS17ImmAsmOperand;
559 let DecoderMethod = "decodeSImmOperand<16>";
561 def PPCDirectBrAsmOperand : AsmOperandClass {
562 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
563 let RenderMethod = "addBranchTargetOperands";
565 def directbrtarget : Operand<OtherVT> {
566 let PrintMethod = "printBranchOperand";
567 let EncoderMethod = "getDirectBrEncoding";
568 let ParserMatchClass = PPCDirectBrAsmOperand;
570 def absdirectbrtarget : Operand<OtherVT> {
571 let PrintMethod = "printAbsBranchOperand";
572 let EncoderMethod = "getAbsDirectBrEncoding";
573 let ParserMatchClass = PPCDirectBrAsmOperand;
575 def PPCCondBrAsmOperand : AsmOperandClass {
576 let Name = "CondBr"; let PredicateMethod = "isCondBr";
577 let RenderMethod = "addBranchTargetOperands";
579 def condbrtarget : Operand<OtherVT> {
580 let PrintMethod = "printBranchOperand";
581 let EncoderMethod = "getCondBrEncoding";
582 let ParserMatchClass = PPCCondBrAsmOperand;
584 def abscondbrtarget : Operand<OtherVT> {
585 let PrintMethod = "printAbsBranchOperand";
586 let EncoderMethod = "getAbsCondBrEncoding";
587 let ParserMatchClass = PPCCondBrAsmOperand;
589 def calltarget : Operand<iPTR> {
590 let PrintMethod = "printBranchOperand";
591 let EncoderMethod = "getDirectBrEncoding";
592 let ParserMatchClass = PPCDirectBrAsmOperand;
594 def abscalltarget : Operand<iPTR> {
595 let PrintMethod = "printAbsBranchOperand";
596 let EncoderMethod = "getAbsDirectBrEncoding";
597 let ParserMatchClass = PPCDirectBrAsmOperand;
599 def PPCCRBitMaskOperand : AsmOperandClass {
600 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
602 def crbitm: Operand<i8> {
603 let PrintMethod = "printcrbitm";
604 let EncoderMethod = "get_crbitm_encoding";
605 let DecoderMethod = "decodeCRBitMOperand";
606 let ParserMatchClass = PPCCRBitMaskOperand;
609 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
610 def PPCRegGxRCNoR0Operand : AsmOperandClass {
611 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
613 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
614 let ParserMatchClass = PPCRegGxRCNoR0Operand;
616 // A version of ptr_rc usable with the asm parser.
617 def PPCRegGxRCOperand : AsmOperandClass {
618 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
620 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
621 let ParserMatchClass = PPCRegGxRCOperand;
624 def PPCDispRIOperand : AsmOperandClass {
625 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
626 let RenderMethod = "addS16ImmOperands";
628 def dispRI : Operand<iPTR> {
629 let ParserMatchClass = PPCDispRIOperand;
631 def PPCDispRIXOperand : AsmOperandClass {
632 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
633 let RenderMethod = "addImmOperands";
635 def dispRIX : Operand<iPTR> {
636 let ParserMatchClass = PPCDispRIXOperand;
638 def PPCDispSPE8Operand : AsmOperandClass {
639 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
640 let RenderMethod = "addImmOperands";
642 def dispSPE8 : Operand<iPTR> {
643 let ParserMatchClass = PPCDispSPE8Operand;
645 def PPCDispSPE4Operand : AsmOperandClass {
646 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
647 let RenderMethod = "addImmOperands";
649 def dispSPE4 : Operand<iPTR> {
650 let ParserMatchClass = PPCDispSPE4Operand;
652 def PPCDispSPE2Operand : AsmOperandClass {
653 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
654 let RenderMethod = "addImmOperands";
656 def dispSPE2 : Operand<iPTR> {
657 let ParserMatchClass = PPCDispSPE2Operand;
660 def memri : Operand<iPTR> {
661 let PrintMethod = "printMemRegImm";
662 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
663 let EncoderMethod = "getMemRIEncoding";
664 let DecoderMethod = "decodeMemRIOperands";
666 def memrr : Operand<iPTR> {
667 let PrintMethod = "printMemRegReg";
668 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
670 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
671 let PrintMethod = "printMemRegImm";
672 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
673 let EncoderMethod = "getMemRIXEncoding";
674 let DecoderMethod = "decodeMemRIXOperands";
676 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
677 let PrintMethod = "printMemRegImm";
678 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
679 let EncoderMethod = "getSPE8DisEncoding";
681 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
682 let PrintMethod = "printMemRegImm";
683 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
684 let EncoderMethod = "getSPE4DisEncoding";
686 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
687 let PrintMethod = "printMemRegImm";
688 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
689 let EncoderMethod = "getSPE2DisEncoding";
692 // A single-register address. This is used with the SjLj
693 // pseudo-instructions.
694 def memr : Operand<iPTR> {
695 let MIOperandInfo = (ops ptr_rc:$ptrreg);
697 def PPCTLSRegOperand : AsmOperandClass {
698 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
699 let RenderMethod = "addTLSRegOperands";
701 def tlsreg32 : Operand<i32> {
702 let EncoderMethod = "getTLSRegEncoding";
703 let ParserMatchClass = PPCTLSRegOperand;
705 def tlsgd32 : Operand<i32> {}
706 def tlscall32 : Operand<i32> {
707 let PrintMethod = "printTLSCall";
708 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
709 let EncoderMethod = "getTLSCallEncoding";
712 // PowerPC Predicate operand.
713 def pred : Operand<OtherVT> {
714 let PrintMethod = "printPredicateOperand";
715 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
718 // Define PowerPC specific addressing mode.
719 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
720 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
721 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
722 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
724 // The address in a single register. This is used with the SjLj
725 // pseudo-instructions.
726 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
728 /// This is just the offset part of iaddr, used for preinc.
729 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
731 //===----------------------------------------------------------------------===//
732 // PowerPC Instruction Predicate Definitions.
733 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
734 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
735 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
736 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
737 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
738 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
739 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
740 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
741 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
742 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
743 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
744 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
745 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
746 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
747 def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
748 def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
750 //===----------------------------------------------------------------------===//
751 // PowerPC Multiclass Definitions.
753 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
754 string asmbase, string asmstr, InstrItinClass itin,
756 let BaseName = asmbase in {
757 def NAME : XForm_6<opcode, xo, OOL, IOL,
758 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
759 pattern>, RecFormRel;
761 def o : XForm_6<opcode, xo, OOL, IOL,
762 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
763 []>, isDOT, RecFormRel;
767 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
768 string asmbase, string asmstr, InstrItinClass itin,
770 let BaseName = asmbase in {
771 let Defs = [CARRY] in
772 def NAME : XForm_6<opcode, xo, OOL, IOL,
773 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
774 pattern>, RecFormRel;
775 let Defs = [CARRY, CR0] in
776 def o : XForm_6<opcode, xo, OOL, IOL,
777 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
778 []>, isDOT, RecFormRel;
782 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
783 string asmbase, string asmstr, InstrItinClass itin,
785 let BaseName = asmbase in {
786 let Defs = [CARRY] in
787 def NAME : XForm_10<opcode, xo, OOL, IOL,
788 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
789 pattern>, RecFormRel;
790 let Defs = [CARRY, CR0] in
791 def o : XForm_10<opcode, xo, OOL, IOL,
792 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
793 []>, isDOT, RecFormRel;
797 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
798 string asmbase, string asmstr, InstrItinClass itin,
800 let BaseName = asmbase in {
801 def NAME : XForm_11<opcode, xo, OOL, IOL,
802 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
803 pattern>, RecFormRel;
805 def o : XForm_11<opcode, xo, OOL, IOL,
806 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
807 []>, isDOT, RecFormRel;
811 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
812 string asmbase, string asmstr, InstrItinClass itin,
814 let BaseName = asmbase in {
815 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
816 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
817 pattern>, RecFormRel;
819 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
820 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
821 []>, isDOT, RecFormRel;
825 // Multiclass for instructions for which the non record form is not cracked
826 // and the record form is cracked (i.e. divw, mullw, etc.)
827 multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
828 string asmbase, string asmstr, InstrItinClass itin,
830 let BaseName = asmbase in {
831 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
832 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
833 pattern>, RecFormRel;
835 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
836 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
837 []>, isDOT, RecFormRel, PPC970_DGroup_First,
838 PPC970_DGroup_Cracked;
842 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
843 string asmbase, string asmstr, InstrItinClass itin,
845 let BaseName = asmbase in {
846 let Defs = [CARRY] in
847 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
848 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
849 pattern>, RecFormRel;
850 let Defs = [CARRY, CR0] in
851 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
852 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
853 []>, isDOT, RecFormRel;
857 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
858 string asmbase, string asmstr, InstrItinClass itin,
860 let BaseName = asmbase in {
861 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
862 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
863 pattern>, RecFormRel;
865 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
866 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
867 []>, isDOT, RecFormRel;
871 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
872 string asmbase, string asmstr, InstrItinClass itin,
874 let BaseName = asmbase in {
875 let Defs = [CARRY] in
876 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
877 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
878 pattern>, RecFormRel;
879 let Defs = [CARRY, CR0] in
880 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
881 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
882 []>, isDOT, RecFormRel;
886 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
887 string asmbase, string asmstr, InstrItinClass itin,
889 let BaseName = asmbase in {
890 def NAME : MForm_2<opcode, OOL, IOL,
891 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
892 pattern>, RecFormRel;
894 def o : MForm_2<opcode, OOL, IOL,
895 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
896 []>, isDOT, RecFormRel;
900 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
901 string asmbase, string asmstr, InstrItinClass itin,
903 let BaseName = asmbase in {
904 def NAME : MDForm_1<opcode, xo, OOL, IOL,
905 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
906 pattern>, RecFormRel;
908 def o : MDForm_1<opcode, xo, OOL, IOL,
909 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
910 []>, isDOT, RecFormRel;
914 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
915 string asmbase, string asmstr, InstrItinClass itin,
917 let BaseName = asmbase in {
918 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
919 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
920 pattern>, RecFormRel;
922 def o : MDSForm_1<opcode, xo, OOL, IOL,
923 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
924 []>, isDOT, RecFormRel;
928 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
929 string asmbase, string asmstr, InstrItinClass itin,
931 let BaseName = asmbase in {
932 let Defs = [CARRY] in
933 def NAME : XSForm_1<opcode, xo, OOL, IOL,
934 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
935 pattern>, RecFormRel;
936 let Defs = [CARRY, CR0] in
937 def o : XSForm_1<opcode, xo, OOL, IOL,
938 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
939 []>, isDOT, RecFormRel;
943 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
944 string asmbase, string asmstr, InstrItinClass itin,
946 let BaseName = asmbase in {
947 def NAME : XForm_26<opcode, xo, OOL, IOL,
948 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
949 pattern>, RecFormRel;
951 def o : XForm_26<opcode, xo, OOL, IOL,
952 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
953 []>, isDOT, RecFormRel;
957 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
958 string asmbase, string asmstr, InstrItinClass itin,
960 let BaseName = asmbase in {
961 def NAME : XForm_28<opcode, xo, OOL, IOL,
962 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
963 pattern>, RecFormRel;
965 def o : XForm_28<opcode, xo, OOL, IOL,
966 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
967 []>, isDOT, RecFormRel;
971 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
972 string asmbase, string asmstr, InstrItinClass itin,
974 let BaseName = asmbase in {
975 def NAME : AForm_1<opcode, xo, OOL, IOL,
976 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
977 pattern>, RecFormRel;
979 def o : AForm_1<opcode, xo, OOL, IOL,
980 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
981 []>, isDOT, RecFormRel;
985 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
986 string asmbase, string asmstr, InstrItinClass itin,
988 let BaseName = asmbase in {
989 def NAME : AForm_2<opcode, xo, OOL, IOL,
990 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
991 pattern>, RecFormRel;
993 def o : AForm_2<opcode, xo, OOL, IOL,
994 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
995 []>, isDOT, RecFormRel;
999 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1000 string asmbase, string asmstr, InstrItinClass itin,
1001 list<dag> pattern> {
1002 let BaseName = asmbase in {
1003 def NAME : AForm_3<opcode, xo, OOL, IOL,
1004 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1005 pattern>, RecFormRel;
1007 def o : AForm_3<opcode, xo, OOL, IOL,
1008 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1009 []>, isDOT, RecFormRel;
1013 //===----------------------------------------------------------------------===//
1014 // PowerPC Instruction Definitions.
1016 // Pseudo-instructions:
1018 let hasCtrlDep = 1 in {
1019 let Defs = [R1], Uses = [R1] in {
1020 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1021 [(callseq_start timm:$amt)]>;
1022 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1023 [(callseq_end timm:$amt1, timm:$amt2)]>;
1026 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1027 "UPDATE_VRSAVE $rD, $rS", []>;
1030 let Defs = [R1], Uses = [R1] in
1031 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1033 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1034 def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1035 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
1037 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
1038 // instruction selection into a branch sequence.
1039 let usesCustomInserter = 1, // Expanded after instruction selection.
1040 PPC970_Single = 1 in {
1041 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1042 // because either operand might become the first operand in an isel, and
1043 // that operand cannot be r0.
1044 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1045 gprc_nor0:$T, gprc_nor0:$F,
1046 i32imm:$BROPC), "#SELECT_CC_I4",
1048 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1049 g8rc_nox0:$T, g8rc_nox0:$F,
1050 i32imm:$BROPC), "#SELECT_CC_I8",
1052 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1053 i32imm:$BROPC), "#SELECT_CC_F4",
1055 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1056 i32imm:$BROPC), "#SELECT_CC_F8",
1058 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1059 i32imm:$BROPC), "#SELECT_CC_VRRC",
1062 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1063 // register bit directly.
1064 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1065 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1066 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1067 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1068 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1069 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1070 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1071 f4rc:$T, f4rc:$F), "#SELECT_F4",
1072 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1073 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1074 f8rc:$T, f8rc:$F), "#SELECT_F8",
1075 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1076 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1077 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1079 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1082 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1083 // scavenge a register for it.
1084 let mayStore = 1 in {
1085 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1087 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1088 "#SPILL_CRBIT", []>;
1091 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1092 // spilled), so we'll need to scavenge a register for it.
1093 let mayLoad = 1 in {
1094 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1096 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1097 "#RESTORE_CRBIT", []>;
1100 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1101 let isReturn = 1, Uses = [LR, RM] in
1102 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1103 [(retflag)]>, Requires<[In32BitMode]>;
1104 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1105 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1108 let isCodeGenOnly = 1 in {
1109 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1110 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1113 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1114 "bcctr 12, $bi, 0", IIC_BrB, []>;
1115 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1116 "bcctr 4, $bi, 0", IIC_BrB, []>;
1122 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1125 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1128 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1129 let isBarrier = 1 in {
1130 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1133 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1134 "ba $dst", IIC_BrB, []>;
1137 // BCC represents an arbitrary conditional branch on a predicate.
1138 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1139 // a two-value operand where a dag node expects two operands. :(
1140 let isCodeGenOnly = 1 in {
1141 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1142 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1143 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1144 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1145 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1147 let isReturn = 1, Uses = [LR, RM] in
1148 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1149 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1152 let isCodeGenOnly = 1 in {
1153 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1154 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1155 "bc 12, $bi, $dst">;
1157 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1158 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1161 let isReturn = 1, Uses = [LR, RM] in
1162 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1163 "bclr 12, $bi, 0", IIC_BrB, []>;
1164 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1165 "bclr 4, $bi, 0", IIC_BrB, []>;
1168 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1169 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1170 "bdzlr", IIC_BrB, []>;
1171 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1172 "bdnzlr", IIC_BrB, []>;
1173 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1174 "bdzlr+", IIC_BrB, []>;
1175 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1176 "bdnzlr+", IIC_BrB, []>;
1177 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1178 "bdzlr-", IIC_BrB, []>;
1179 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1180 "bdnzlr-", IIC_BrB, []>;
1183 let Defs = [CTR], Uses = [CTR] in {
1184 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1186 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1188 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1190 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1192 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1194 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1196 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1198 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1200 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1202 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1204 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1206 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1211 // The unconditional BCL used by the SjLj setjmp code.
1212 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1213 let Defs = [LR], Uses = [RM] in {
1214 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1215 "bcl 20, 31, $dst">;
1219 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1220 // Convenient aliases for call instructions
1221 let Uses = [RM] in {
1222 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1223 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1224 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1225 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1227 let isCodeGenOnly = 1 in {
1228 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1229 "bl $func", IIC_BrB, []>;
1230 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1231 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1232 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1233 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1235 def BCL : BForm_4<16, 12, 0, 1, (outs),
1236 (ins crbitrc:$bi, condbrtarget:$dst),
1237 "bcl 12, $bi, $dst">;
1238 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1239 (ins crbitrc:$bi, condbrtarget:$dst),
1240 "bcl 4, $bi, $dst">;
1243 let Uses = [CTR, RM] in {
1244 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1245 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1246 Requires<[In32BitMode]>;
1248 let isCodeGenOnly = 1 in {
1249 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1250 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1253 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1254 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1255 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1256 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1259 let Uses = [LR, RM] in {
1260 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1261 "blrl", IIC_BrB, []>;
1263 let isCodeGenOnly = 1 in {
1264 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1265 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1268 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1269 "bclrl 12, $bi, 0", IIC_BrB, []>;
1270 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1271 "bclrl 4, $bi, 0", IIC_BrB, []>;
1274 let Defs = [CTR], Uses = [CTR, RM] in {
1275 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1277 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1279 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1281 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1283 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1285 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1287 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1289 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1291 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1293 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1295 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1297 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1300 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1301 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1302 "bdzlrl", IIC_BrB, []>;
1303 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1304 "bdnzlrl", IIC_BrB, []>;
1305 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1306 "bdzlrl+", IIC_BrB, []>;
1307 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1308 "bdnzlrl+", IIC_BrB, []>;
1309 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1310 "bdzlrl-", IIC_BrB, []>;
1311 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1312 "bdnzlrl-", IIC_BrB, []>;
1316 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1317 def TCRETURNdi :Pseudo< (outs),
1318 (ins calltarget:$dst, i32imm:$offset),
1319 "#TC_RETURNd $dst $offset",
1323 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1324 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1325 "#TC_RETURNa $func $offset",
1326 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1328 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1329 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1330 "#TC_RETURNr $dst $offset",
1334 let isCodeGenOnly = 1 in {
1336 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1337 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1338 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1339 []>, Requires<[In32BitMode]>;
1341 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1342 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1343 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1347 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1348 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1349 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1355 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1357 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1358 "#EH_SJLJ_SETJMP32",
1359 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1360 Requires<[In32BitMode]>;
1361 let isTerminator = 1 in
1362 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1363 "#EH_SJLJ_LONGJMP32",
1364 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1365 Requires<[In32BitMode]>;
1368 let isBranch = 1, isTerminator = 1 in {
1369 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1370 "#EH_SjLj_Setup\t$dst", []>;
1374 let PPC970_Unit = 7 in {
1375 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1376 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1379 // Branch history rolling buffer.
1380 def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1382 PPC970_DGroup_Single;
1383 // The $dmy argument used for MFBHRBE is not needed; however, including
1384 // it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1385 // interferes with necessary special handling (see PPCFastISel.cpp).
1386 def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1387 (ins u10imm:$imm, u10imm:$dmy),
1388 "mfbhrbe $rD, $imm", IIC_BrB,
1390 (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1391 PPC970_DGroup_First;
1393 def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1394 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1395 PPC970_DGroup_Single;
1397 // DCB* instructions.
1398 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1399 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1400 PPC970_DGroup_Single;
1401 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1402 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1403 PPC970_DGroup_Single;
1404 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1405 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1406 PPC970_DGroup_Single;
1407 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1408 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1409 PPC970_DGroup_Single;
1410 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1411 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1412 PPC970_DGroup_Single;
1413 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1414 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1415 PPC970_DGroup_Single;
1417 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1418 def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1419 "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1420 PPC970_DGroup_Single;
1421 def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1422 "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1423 PPC970_DGroup_Single;
1424 } // hasSideEffects = 0
1426 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1427 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1429 def : Pat<(int_ppc_dcbt xoaddr:$dst),
1430 (DCBT 0, xoaddr:$dst)>;
1431 def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1432 (DCBTST 0, xoaddr:$dst)>;
1434 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1435 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads
1436 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1437 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1438 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1439 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1441 // Atomic operations
1442 let usesCustomInserter = 1 in {
1443 let Defs = [CR0] in {
1444 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1445 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1446 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1447 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1448 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1449 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1450 def ATOMIC_LOAD_AND_I8 : Pseudo<
1451 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1452 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1453 def ATOMIC_LOAD_OR_I8 : Pseudo<
1454 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1455 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1456 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1457 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1458 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1459 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1460 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1461 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1462 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1463 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1464 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1465 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1466 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1467 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1468 def ATOMIC_LOAD_AND_I16 : Pseudo<
1469 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1470 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1471 def ATOMIC_LOAD_OR_I16 : Pseudo<
1472 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1473 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1474 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1475 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1476 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1477 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1478 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1479 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1480 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1481 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1482 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1483 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1484 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1485 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1486 def ATOMIC_LOAD_AND_I32 : Pseudo<
1487 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1488 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1489 def ATOMIC_LOAD_OR_I32 : Pseudo<
1490 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1491 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1492 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1493 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1494 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1495 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1496 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1497 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1499 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1500 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1501 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1502 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1503 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1504 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1505 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1506 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1507 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1509 def ATOMIC_SWAP_I8 : Pseudo<
1510 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1511 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1512 def ATOMIC_SWAP_I16 : Pseudo<
1513 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1514 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1515 def ATOMIC_SWAP_I32 : Pseudo<
1516 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1517 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1521 // Instructions to support atomic operations
1522 let mayLoad = 1, hasSideEffects = 0 in {
1523 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1524 "lbarx $rD, $src", IIC_LdStLWARX, []>,
1525 Requires<[HasPartwordAtomics]>;
1527 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1528 "lharx $rD, $src", IIC_LdStLWARX, []>,
1529 Requires<[HasPartwordAtomics]>;
1531 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1532 "lwarx $rD, $src", IIC_LdStLWARX, []>;
1534 // Instructions to support lock versions of atomics
1535 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1536 def LBARXL : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1537 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1538 Requires<[HasPartwordAtomics]>;
1540 def LHARXL : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1541 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1542 Requires<[HasPartwordAtomics]>;
1544 def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1545 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1548 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1549 def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1550 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1551 isDOT, Requires<[HasPartwordAtomics]>;
1553 def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1554 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1555 isDOT, Requires<[HasPartwordAtomics]>;
1557 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1558 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1561 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1562 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1564 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1565 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1566 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1567 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1568 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1569 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1570 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1571 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1573 //===----------------------------------------------------------------------===//
1574 // PPC32 Load Instructions.
1577 // Unindexed (r+i) Loads.
1578 let PPC970_Unit = 2 in {
1579 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1580 "lbz $rD, $src", IIC_LdStLoad,
1581 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1582 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1583 "lha $rD, $src", IIC_LdStLHA,
1584 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1585 PPC970_DGroup_Cracked;
1586 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1587 "lhz $rD, $src", IIC_LdStLoad,
1588 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1589 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1590 "lwz $rD, $src", IIC_LdStLoad,
1591 [(set i32:$rD, (load iaddr:$src))]>;
1593 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1594 "lfs $rD, $src", IIC_LdStLFD,
1595 [(set f32:$rD, (load iaddr:$src))]>;
1596 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1597 "lfd $rD, $src", IIC_LdStLFD,
1598 [(set f64:$rD, (load iaddr:$src))]>;
1601 // Unindexed (r+i) Loads with Update (preinc).
1602 let mayLoad = 1, hasSideEffects = 0 in {
1603 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1604 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1605 []>, RegConstraint<"$addr.reg = $ea_result">,
1606 NoEncode<"$ea_result">;
1608 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1609 "lhau $rD, $addr", IIC_LdStLHAU,
1610 []>, RegConstraint<"$addr.reg = $ea_result">,
1611 NoEncode<"$ea_result">;
1613 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1614 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1615 []>, RegConstraint<"$addr.reg = $ea_result">,
1616 NoEncode<"$ea_result">;
1618 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1619 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1620 []>, RegConstraint<"$addr.reg = $ea_result">,
1621 NoEncode<"$ea_result">;
1623 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1624 "lfsu $rD, $addr", IIC_LdStLFDU,
1625 []>, RegConstraint<"$addr.reg = $ea_result">,
1626 NoEncode<"$ea_result">;
1628 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1629 "lfdu $rD, $addr", IIC_LdStLFDU,
1630 []>, RegConstraint<"$addr.reg = $ea_result">,
1631 NoEncode<"$ea_result">;
1634 // Indexed (r+r) Loads with Update (preinc).
1635 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1637 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1638 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1639 NoEncode<"$ea_result">;
1641 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1643 "lhaux $rD, $addr", IIC_LdStLHAUX,
1644 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1645 NoEncode<"$ea_result">;
1647 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1649 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1650 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1651 NoEncode<"$ea_result">;
1653 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1655 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1656 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1657 NoEncode<"$ea_result">;
1659 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1661 "lfsux $rD, $addr", IIC_LdStLFDUX,
1662 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1663 NoEncode<"$ea_result">;
1665 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1667 "lfdux $rD, $addr", IIC_LdStLFDUX,
1668 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1669 NoEncode<"$ea_result">;
1673 // Indexed (r+r) Loads.
1675 let PPC970_Unit = 2 in {
1676 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1677 "lbzx $rD, $src", IIC_LdStLoad,
1678 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1679 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1680 "lhax $rD, $src", IIC_LdStLHA,
1681 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1682 PPC970_DGroup_Cracked;
1683 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1684 "lhzx $rD, $src", IIC_LdStLoad,
1685 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1686 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1687 "lwzx $rD, $src", IIC_LdStLoad,
1688 [(set i32:$rD, (load xaddr:$src))]>;
1691 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1692 "lhbrx $rD, $src", IIC_LdStLoad,
1693 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1694 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1695 "lwbrx $rD, $src", IIC_LdStLoad,
1696 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1698 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1699 "lfsx $frD, $src", IIC_LdStLFD,
1700 [(set f32:$frD, (load xaddr:$src))]>;
1701 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1702 "lfdx $frD, $src", IIC_LdStLFD,
1703 [(set f64:$frD, (load xaddr:$src))]>;
1705 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1706 "lfiwax $frD, $src", IIC_LdStLFD,
1707 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1708 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1709 "lfiwzx $frD, $src", IIC_LdStLFD,
1710 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1714 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1715 "lmw $rD, $src", IIC_LdStLMW, []>;
1717 //===----------------------------------------------------------------------===//
1718 // PPC32 Store Instructions.
1721 // Unindexed (r+i) Stores.
1722 let PPC970_Unit = 2 in {
1723 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1724 "stb $rS, $src", IIC_LdStStore,
1725 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1726 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1727 "sth $rS, $src", IIC_LdStStore,
1728 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1729 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1730 "stw $rS, $src", IIC_LdStStore,
1731 [(store i32:$rS, iaddr:$src)]>;
1732 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1733 "stfs $rS, $dst", IIC_LdStSTFD,
1734 [(store f32:$rS, iaddr:$dst)]>;
1735 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1736 "stfd $rS, $dst", IIC_LdStSTFD,
1737 [(store f64:$rS, iaddr:$dst)]>;
1740 // Unindexed (r+i) Stores with Update (preinc).
1741 let PPC970_Unit = 2, mayStore = 1 in {
1742 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1743 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1744 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1745 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1746 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1747 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1748 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1749 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1750 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1751 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1752 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1753 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1754 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1755 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1756 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1759 // Patterns to match the pre-inc stores. We can't put the patterns on
1760 // the instruction definitions directly as ISel wants the address base
1761 // and offset to be separate operands, not a single complex operand.
1762 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1763 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1764 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1765 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1766 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1767 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1768 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1769 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1770 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1771 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1773 // Indexed (r+r) Stores.
1774 let PPC970_Unit = 2 in {
1775 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1776 "stbx $rS, $dst", IIC_LdStStore,
1777 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1778 PPC970_DGroup_Cracked;
1779 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1780 "sthx $rS, $dst", IIC_LdStStore,
1781 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1782 PPC970_DGroup_Cracked;
1783 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1784 "stwx $rS, $dst", IIC_LdStStore,
1785 [(store i32:$rS, xaddr:$dst)]>,
1786 PPC970_DGroup_Cracked;
1788 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1789 "sthbrx $rS, $dst", IIC_LdStStore,
1790 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1791 PPC970_DGroup_Cracked;
1792 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1793 "stwbrx $rS, $dst", IIC_LdStStore,
1794 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1795 PPC970_DGroup_Cracked;
1797 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1798 "stfiwx $frS, $dst", IIC_LdStSTFD,
1799 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1801 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1802 "stfsx $frS, $dst", IIC_LdStSTFD,
1803 [(store f32:$frS, xaddr:$dst)]>;
1804 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1805 "stfdx $frS, $dst", IIC_LdStSTFD,
1806 [(store f64:$frS, xaddr:$dst)]>;
1809 // Indexed (r+r) Stores with Update (preinc).
1810 let PPC970_Unit = 2, mayStore = 1 in {
1811 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1812 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1813 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1814 PPC970_DGroup_Cracked;
1815 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1816 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1817 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1818 PPC970_DGroup_Cracked;
1819 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1820 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1821 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1822 PPC970_DGroup_Cracked;
1823 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1824 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1825 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1826 PPC970_DGroup_Cracked;
1827 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1828 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1829 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1830 PPC970_DGroup_Cracked;
1833 // Patterns to match the pre-inc stores. We can't put the patterns on
1834 // the instruction definitions directly as ISel wants the address base
1835 // and offset to be separate operands, not a single complex operand.
1836 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1837 (STBUX $rS, $ptrreg, $ptroff)>;
1838 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1839 (STHUX $rS, $ptrreg, $ptroff)>;
1840 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1841 (STWUX $rS, $ptrreg, $ptroff)>;
1842 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1843 (STFSUX $rS, $ptrreg, $ptroff)>;
1844 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1845 (STFDUX $rS, $ptrreg, $ptroff)>;
1848 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1849 "stmw $rS, $dst", IIC_LdStLMW, []>;
1851 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1852 "sync $L", IIC_LdStSync, []>;
1854 let isCodeGenOnly = 1 in {
1855 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1856 "msync", IIC_LdStSync, []> {
1861 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1862 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1863 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1864 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1866 //===----------------------------------------------------------------------===//
1867 // PPC32 Arithmetic Instructions.
1870 let PPC970_Unit = 1 in { // FXU Operations.
1871 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1872 "addi $rD, $rA, $imm", IIC_IntSimple,
1873 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1874 let BaseName = "addic" in {
1875 let Defs = [CARRY] in
1876 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1877 "addic $rD, $rA, $imm", IIC_IntGeneral,
1878 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1879 RecFormRel, PPC970_DGroup_Cracked;
1880 let Defs = [CARRY, CR0] in
1881 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1882 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1883 []>, isDOT, RecFormRel;
1885 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1886 "addis $rD, $rA, $imm", IIC_IntSimple,
1887 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1888 let isCodeGenOnly = 1 in
1889 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1890 "la $rD, $sym($rA)", IIC_IntGeneral,
1891 [(set i32:$rD, (add i32:$rA,
1892 (PPClo tglobaladdr:$sym, 0)))]>;
1893 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1894 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1895 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1896 let Defs = [CARRY] in
1897 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1898 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1899 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1901 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1902 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1903 "li $rD, $imm", IIC_IntSimple,
1904 [(set i32:$rD, imm32SExt16:$imm)]>;
1905 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1906 "lis $rD, $imm", IIC_IntSimple,
1907 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1911 let PPC970_Unit = 1 in { // FXU Operations.
1912 let Defs = [CR0] in {
1913 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1914 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1915 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1917 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1918 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1919 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1922 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1923 "ori $dst, $src1, $src2", IIC_IntSimple,
1924 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1925 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1926 "oris $dst, $src1, $src2", IIC_IntSimple,
1927 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1928 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1929 "xori $dst, $src1, $src2", IIC_IntSimple,
1930 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1931 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1932 "xoris $dst, $src1, $src2", IIC_IntSimple,
1933 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1935 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1937 let isCodeGenOnly = 1 in {
1938 // The POWER6 and POWER7 have special group-terminating nops.
1939 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1940 "ori 1, 1, 0", IIC_IntSimple, []>;
1941 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1942 "ori 2, 2, 0", IIC_IntSimple, []>;
1945 let isCompare = 1, hasSideEffects = 0 in {
1946 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1947 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1948 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1949 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1953 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1954 let isCommutable = 1 in {
1955 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1956 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1957 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1958 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1959 "and", "$rA, $rS, $rB", IIC_IntSimple,
1960 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1962 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1963 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1964 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1965 let isCommutable = 1 in {
1966 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1967 "or", "$rA, $rS, $rB", IIC_IntSimple,
1968 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1969 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1970 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1971 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1973 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1974 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1975 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1976 let isCommutable = 1 in {
1977 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1978 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1979 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1980 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1981 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1982 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1984 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1985 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1986 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1987 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1988 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1989 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1990 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1991 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1992 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1995 let PPC970_Unit = 1 in { // FXU Operations.
1996 let hasSideEffects = 0 in {
1997 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1998 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1999 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
2000 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
2001 "cntlzw", "$rA, $rS", IIC_IntGeneral,
2002 [(set i32:$rA, (ctlz i32:$rS))]>;
2003 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2004 "extsb", "$rA, $rS", IIC_IntSimple,
2005 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2006 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2007 "extsh", "$rA, $rS", IIC_IntSimple,
2008 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2010 let isCommutable = 1 in
2011 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2012 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2013 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2015 let isCompare = 1, hasSideEffects = 0 in {
2016 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2017 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2018 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2019 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2022 let PPC970_Unit = 3 in { // FPU Operations.
2023 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2024 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2025 let isCompare = 1, hasSideEffects = 0 in {
2026 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2027 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2028 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2029 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2030 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2033 let Uses = [RM] in {
2034 let hasSideEffects = 0 in {
2035 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2036 "fctiw", "$frD, $frB", IIC_FPGeneral,
2038 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2039 "fctiwz", "$frD, $frB", IIC_FPGeneral,
2040 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2042 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2043 "frsp", "$frD, $frB", IIC_FPGeneral,
2044 [(set f32:$frD, (fround f64:$frB))]>;
2046 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2047 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2048 "frin", "$frD, $frB", IIC_FPGeneral,
2049 [(set f64:$frD, (frnd f64:$frB))]>;
2050 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2051 "frin", "$frD, $frB", IIC_FPGeneral,
2052 [(set f32:$frD, (frnd f32:$frB))]>;
2055 let hasSideEffects = 0 in {
2056 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2057 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2058 "frip", "$frD, $frB", IIC_FPGeneral,
2059 [(set f64:$frD, (fceil f64:$frB))]>;
2060 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2061 "frip", "$frD, $frB", IIC_FPGeneral,
2062 [(set f32:$frD, (fceil f32:$frB))]>;
2063 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2064 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2065 "friz", "$frD, $frB", IIC_FPGeneral,
2066 [(set f64:$frD, (ftrunc f64:$frB))]>;
2067 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2068 "friz", "$frD, $frB", IIC_FPGeneral,
2069 [(set f32:$frD, (ftrunc f32:$frB))]>;
2070 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2071 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2072 "frim", "$frD, $frB", IIC_FPGeneral,
2073 [(set f64:$frD, (ffloor f64:$frB))]>;
2074 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2075 "frim", "$frD, $frB", IIC_FPGeneral,
2076 [(set f32:$frD, (ffloor f32:$frB))]>;
2078 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2079 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2080 [(set f64:$frD, (fsqrt f64:$frB))]>;
2081 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2082 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2083 [(set f32:$frD, (fsqrt f32:$frB))]>;
2088 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2089 /// often coalesced away and we don't want the dispatch group builder to think
2090 /// that they will fill slots (which could cause the load of a LSU reject to
2091 /// sneak into a d-group with a store).
2092 let hasSideEffects = 0 in
2093 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2094 "fmr", "$frD, $frB", IIC_FPGeneral,
2095 []>, // (set f32:$frD, f32:$frB)
2098 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2099 // These are artificially split into two different forms, for 4/8 byte FP.
2100 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2101 "fabs", "$frD, $frB", IIC_FPGeneral,
2102 [(set f32:$frD, (fabs f32:$frB))]>;
2103 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2104 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2105 "fabs", "$frD, $frB", IIC_FPGeneral,
2106 [(set f64:$frD, (fabs f64:$frB))]>;
2107 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2108 "fnabs", "$frD, $frB", IIC_FPGeneral,
2109 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2110 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2111 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2112 "fnabs", "$frD, $frB", IIC_FPGeneral,
2113 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2114 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2115 "fneg", "$frD, $frB", IIC_FPGeneral,
2116 [(set f32:$frD, (fneg f32:$frB))]>;
2117 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2118 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2119 "fneg", "$frD, $frB", IIC_FPGeneral,
2120 [(set f64:$frD, (fneg f64:$frB))]>;
2122 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2123 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2124 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2125 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2126 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2127 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2128 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2130 // Reciprocal estimates.
2131 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2132 "fre", "$frD, $frB", IIC_FPGeneral,
2133 [(set f64:$frD, (PPCfre f64:$frB))]>;
2134 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2135 "fres", "$frD, $frB", IIC_FPGeneral,
2136 [(set f32:$frD, (PPCfre f32:$frB))]>;
2137 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2138 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2139 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2140 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2141 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2142 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2145 // XL-Form instructions. condition register logical ops.
2147 let hasSideEffects = 0 in
2148 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2149 "mcrf $BF, $BFA", IIC_BrMCR>,
2150 PPC970_DGroup_First, PPC970_Unit_CRU;
2152 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2153 // condition-register logical instructions have preferred forms. Specifically,
2154 // it is preferred that the bit specified by the BT field be in the same
2155 // condition register as that specified by the bit BB. We might want to account
2156 // for this via hinting the register allocator and anti-dep breakers, or we
2157 // could constrain the register class to force this constraint and then loosen
2158 // it during register allocation via convertToThreeAddress or some similar
2161 let isCommutable = 1 in {
2162 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2163 (ins crbitrc:$CRA, crbitrc:$CRB),
2164 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2165 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2167 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2168 (ins crbitrc:$CRA, crbitrc:$CRB),
2169 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2170 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2172 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2173 (ins crbitrc:$CRA, crbitrc:$CRB),
2174 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2175 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2177 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2178 (ins crbitrc:$CRA, crbitrc:$CRB),
2179 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2180 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2182 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2183 (ins crbitrc:$CRA, crbitrc:$CRB),
2184 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2185 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2187 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2188 (ins crbitrc:$CRA, crbitrc:$CRB),
2189 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2190 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2193 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2194 (ins crbitrc:$CRA, crbitrc:$CRB),
2195 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2196 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2198 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2199 (ins crbitrc:$CRA, crbitrc:$CRB),
2200 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2201 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2203 let isCodeGenOnly = 1 in {
2204 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2205 "creqv $dst, $dst, $dst", IIC_BrCR,
2206 [(set i1:$dst, 1)]>;
2208 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2209 "crxor $dst, $dst, $dst", IIC_BrCR,
2210 [(set i1:$dst, 0)]>;
2212 let Defs = [CR1EQ], CRD = 6 in {
2213 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2214 "creqv 6, 6, 6", IIC_BrCR,
2217 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2218 "crxor 6, 6, 6", IIC_BrCR,
2223 // XFX-Form instructions. Instructions that deal with SPRs.
2226 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2227 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2228 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2229 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2231 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2232 "mftb $RT, $SPR", IIC_SprMFTB>;
2234 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2235 // on a 32-bit target.
2236 let hasSideEffects = 1, usesCustomInserter = 1 in
2237 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2240 let Uses = [CTR] in {
2241 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2242 "mfctr $rT", IIC_SprMFSPR>,
2243 PPC970_DGroup_First, PPC970_Unit_FXU;
2245 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2246 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2247 "mtctr $rS", IIC_SprMTSPR>,
2248 PPC970_DGroup_First, PPC970_Unit_FXU;
2250 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2251 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2252 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2253 "mtctr $rS", IIC_SprMTSPR>,
2254 PPC970_DGroup_First, PPC970_Unit_FXU;
2257 let Defs = [LR] in {
2258 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2259 "mtlr $rS", IIC_SprMTSPR>,
2260 PPC970_DGroup_First, PPC970_Unit_FXU;
2262 let Uses = [LR] in {
2263 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2264 "mflr $rT", IIC_SprMFSPR>,
2265 PPC970_DGroup_First, PPC970_Unit_FXU;
2268 let isCodeGenOnly = 1 in {
2269 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2270 // like a GPR on the PPC970. As such, copies in and out have the same
2271 // performance characteristics as an OR instruction.
2272 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2273 "mtspr 256, $rS", IIC_IntGeneral>,
2274 PPC970_DGroup_Single, PPC970_Unit_FXU;
2275 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2276 "mfspr $rT, 256", IIC_IntGeneral>,
2277 PPC970_DGroup_First, PPC970_Unit_FXU;
2279 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2280 (outs VRSAVERC:$reg), (ins gprc:$rS),
2281 "mtspr 256, $rS", IIC_IntGeneral>,
2282 PPC970_DGroup_Single, PPC970_Unit_FXU;
2283 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2284 (ins VRSAVERC:$reg),
2285 "mfspr $rT, 256", IIC_IntGeneral>,
2286 PPC970_DGroup_First, PPC970_Unit_FXU;
2289 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2290 // so we'll need to scavenge a register for it.
2292 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2293 "#SPILL_VRSAVE", []>;
2295 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2296 // spilled), so we'll need to scavenge a register for it.
2298 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2299 "#RESTORE_VRSAVE", []>;
2301 let hasSideEffects = 0 in {
2302 // mtocrf's input needs to be prepared by shifting by an amount dependent
2303 // on the cr register selected. Thus, post-ra anti-dep breaking must not
2304 // later change that register assignment.
2305 let hasExtraDefRegAllocReq = 1 in {
2306 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2307 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2308 PPC970_DGroup_First, PPC970_Unit_CRU;
2310 // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
2311 // is dependent on the cr fields being set.
2312 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2313 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2314 PPC970_MicroCode, PPC970_Unit_CRU;
2315 } // hasExtraDefRegAllocReq = 1
2317 // mfocrf's input needs to be prepared by shifting by an amount dependent
2318 // on the cr register selected. Thus, post-ra anti-dep breaking must not
2319 // later change that register assignment.
2320 let hasExtraSrcRegAllocReq = 1 in {
2321 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2322 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2323 PPC970_DGroup_First, PPC970_Unit_CRU;
2325 // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
2326 // is dependent on the cr fields being copied.
2327 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2328 "mfcr $rT", IIC_SprMFCR>,
2329 PPC970_MicroCode, PPC970_Unit_CRU;
2330 } // hasExtraSrcRegAllocReq = 1
2331 } // hasSideEffects = 0
2333 // Pseudo instruction to perform FADD in round-to-zero mode.
2334 let usesCustomInserter = 1, Uses = [RM] in {
2335 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2336 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2339 // The above pseudo gets expanded to make use of the following instructions
2340 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2341 let Uses = [RM], Defs = [RM] in {
2342 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2343 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2344 PPC970_DGroup_Single, PPC970_Unit_FPU;
2345 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2346 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2347 PPC970_DGroup_Single, PPC970_Unit_FPU;
2348 let isCodeGenOnly = 1 in
2349 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2350 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2351 PPC970_DGroup_Single, PPC970_Unit_FPU;
2353 let Uses = [RM] in {
2354 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2355 "mffs $rT", IIC_IntMFFS,
2356 [(set f64:$rT, (PPCmffs))]>,
2357 PPC970_DGroup_Single, PPC970_Unit_FPU;
2360 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2361 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2365 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2366 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2367 let isCommutable = 1 in
2368 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2369 "add", "$rT, $rA, $rB", IIC_IntSimple,
2370 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2371 let isCodeGenOnly = 1 in
2372 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2373 "add $rT, $rA, $rB", IIC_IntSimple,
2374 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2375 let isCommutable = 1 in
2376 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2377 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2378 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2379 PPC970_DGroup_Cracked;
2381 defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2382 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2383 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2384 defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2385 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2386 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2387 def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2388 "divwe $rT, $rA, $rB", IIC_IntDivW,
2389 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2390 Requires<[HasExtDiv]>;
2392 def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2393 "divwe. $rT, $rA, $rB", IIC_IntDivW,
2394 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2395 Requires<[HasExtDiv]>;
2396 def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2397 "divweu $rT, $rA, $rB", IIC_IntDivW,
2398 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2399 Requires<[HasExtDiv]>;
2401 def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2402 "divweu. $rT, $rA, $rB", IIC_IntDivW,
2403 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2404 Requires<[HasExtDiv]>;
2405 let isCommutable = 1 in {
2406 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2407 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2408 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2409 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2410 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2411 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2412 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2413 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2414 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2416 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2417 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2418 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2419 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2420 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2421 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2422 PPC970_DGroup_Cracked;
2423 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2424 "neg", "$rT, $rA", IIC_IntSimple,
2425 [(set i32:$rT, (ineg i32:$rA))]>;
2426 let Uses = [CARRY] in {
2427 let isCommutable = 1 in
2428 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2429 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2430 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2431 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2432 "addme", "$rT, $rA", IIC_IntGeneral,
2433 [(set i32:$rT, (adde i32:$rA, -1))]>;
2434 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2435 "addze", "$rT, $rA", IIC_IntGeneral,
2436 [(set i32:$rT, (adde i32:$rA, 0))]>;
2437 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2438 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2439 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2440 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2441 "subfme", "$rT, $rA", IIC_IntGeneral,
2442 [(set i32:$rT, (sube -1, i32:$rA))]>;
2443 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2444 "subfze", "$rT, $rA", IIC_IntGeneral,
2445 [(set i32:$rT, (sube 0, i32:$rA))]>;
2449 // A-Form instructions. Most of the instructions executed in the FPU are of
2452 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2453 let Uses = [RM] in {
2454 let isCommutable = 1 in {
2455 defm FMADD : AForm_1r<63, 29,
2456 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2457 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2458 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2459 defm FMADDS : AForm_1r<59, 29,
2460 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2461 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2462 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2463 defm FMSUB : AForm_1r<63, 28,
2464 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2465 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2467 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2468 defm FMSUBS : AForm_1r<59, 28,
2469 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2470 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2472 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2473 defm FNMADD : AForm_1r<63, 31,
2474 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2475 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2477 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2478 defm FNMADDS : AForm_1r<59, 31,
2479 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2480 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2482 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2483 defm FNMSUB : AForm_1r<63, 30,
2484 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2485 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2486 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2487 (fneg f64:$FRB))))]>;
2488 defm FNMSUBS : AForm_1r<59, 30,
2489 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2490 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2491 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2492 (fneg f32:$FRB))))]>;
2495 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2496 // having 4 of these, force the comparison to always be an 8-byte double (code
2497 // should use an FMRSD if the input comparison value really wants to be a float)
2498 // and 4/8 byte forms for the result and operand type..
2499 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2500 defm FSELD : AForm_1r<63, 23,
2501 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2502 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2503 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2504 defm FSELS : AForm_1r<63, 23,
2505 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2506 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2507 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2508 let Uses = [RM] in {
2509 let isCommutable = 1 in {
2510 defm FADD : AForm_2r<63, 21,
2511 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2512 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2513 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2514 defm FADDS : AForm_2r<59, 21,
2515 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2516 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2517 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2519 defm FDIV : AForm_2r<63, 18,
2520 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2521 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2522 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2523 defm FDIVS : AForm_2r<59, 18,
2524 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2525 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2526 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2527 let isCommutable = 1 in {
2528 defm FMUL : AForm_3r<63, 25,
2529 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2530 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2531 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2532 defm FMULS : AForm_3r<59, 25,
2533 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2534 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2535 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2537 defm FSUB : AForm_2r<63, 20,
2538 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2539 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2540 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2541 defm FSUBS : AForm_2r<59, 20,
2542 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2543 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2544 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2548 let hasSideEffects = 0 in {
2549 let PPC970_Unit = 1 in { // FXU Operations.
2551 def ISEL : AForm_4<31, 15,
2552 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2553 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2557 let PPC970_Unit = 1 in { // FXU Operations.
2558 // M-Form instructions. rotate and mask instructions.
2560 let isCommutable = 1 in {
2561 // RLWIMI can be commuted if the rotate amount is zero.
2562 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2563 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2564 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2565 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2566 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2568 let BaseName = "rlwinm" in {
2569 def RLWINM : MForm_2<21,
2570 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2571 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2574 def RLWINMo : MForm_2<21,
2575 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2576 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2577 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2579 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2580 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2581 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2584 } // hasSideEffects = 0
2586 //===----------------------------------------------------------------------===//
2587 // PowerPC Instruction Patterns
2590 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2591 def : Pat<(i32 imm:$imm),
2592 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2594 // Implement the 'not' operation with the NOR instruction.
2595 def i32not : OutPatFrag<(ops node:$in),
2597 def : Pat<(not i32:$in),
2600 // ADD an arbitrary immediate.
2601 def : Pat<(add i32:$in, imm:$imm),
2602 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2603 // OR an arbitrary immediate.
2604 def : Pat<(or i32:$in, imm:$imm),
2605 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2606 // XOR an arbitrary immediate.
2607 def : Pat<(xor i32:$in, imm:$imm),
2608 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2610 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2611 (SUBFIC $in, imm:$imm)>;
2614 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2615 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2616 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2617 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2620 def : Pat<(rotl i32:$in, i32:$sh),
2621 (RLWNM $in, $sh, 0, 31)>;
2622 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2623 (RLWINM $in, imm:$imm, 0, 31)>;
2626 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2627 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2630 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2631 (BL tglobaladdr:$dst)>;
2632 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2633 (BL texternalsym:$dst)>;
2635 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2636 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2638 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2639 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2641 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2642 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2646 // Hi and Lo for Darwin Global Addresses.
2647 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2648 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2649 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2650 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2651 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2652 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2653 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2654 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2655 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2656 (ADDIS $in, tglobaltlsaddr:$g)>;
2657 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2658 (ADDI $in, tglobaltlsaddr:$g)>;
2659 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2660 (ADDIS $in, tglobaladdr:$g)>;
2661 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2662 (ADDIS $in, tconstpool:$g)>;
2663 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2664 (ADDIS $in, tjumptable:$g)>;
2665 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2666 (ADDIS $in, tblockaddress:$g)>;
2668 // Support for thread-local storage.
2669 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2670 [(set i32:$rD, (PPCppc32GOT))]>;
2672 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2673 // This uses two output registers, the first as the real output, the second as a
2674 // temporary register, used internally in code generation.
2675 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2676 []>, NoEncode<"$rT">;
2678 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2681 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2682 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2683 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2685 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2688 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2689 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2690 // explicitly defined when this op is created, so not mentioned here.
2691 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2692 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2693 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2696 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2697 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2698 // are true defines while the rest of the Defs are clobbers.
2699 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2700 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2701 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2702 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2703 "#ADDItlsgdLADDR32",
2705 (PPCaddiTlsgdLAddr i32:$reg,
2706 tglobaltlsaddr:$disp,
2707 tglobaltlsaddr:$sym))]>;
2708 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2711 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2712 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2713 // explicitly defined when this op is created, so not mentioned here.
2714 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2715 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2716 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2719 (PPCgetTlsldAddr i32:$reg,
2720 tglobaltlsaddr:$sym))]>;
2721 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2722 // are true defines while the rest of the Defs are clobbers.
2723 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2724 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2725 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2726 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2727 "#ADDItlsldLADDR32",
2729 (PPCaddiTlsldLAddr i32:$reg,
2730 tglobaltlsaddr:$disp,
2731 tglobaltlsaddr:$sym))]>;
2732 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2735 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2736 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2739 (PPCaddisDtprelHA i32:$reg,
2740 tglobaltlsaddr:$disp))]>;
2742 // Support for Position-independent code
2743 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2746 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2747 // Get Global (GOT) Base Register offset, from the word immediately preceding
2748 // the function label.
2749 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2752 // Standard shifts. These are represented separately from the real shifts above
2753 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2755 def : Pat<(sra i32:$rS, i32:$rB),
2757 def : Pat<(srl i32:$rS, i32:$rB),
2759 def : Pat<(shl i32:$rS, i32:$rB),
2762 def : Pat<(zextloadi1 iaddr:$src),
2764 def : Pat<(zextloadi1 xaddr:$src),
2766 def : Pat<(extloadi1 iaddr:$src),
2768 def : Pat<(extloadi1 xaddr:$src),
2770 def : Pat<(extloadi8 iaddr:$src),
2772 def : Pat<(extloadi8 xaddr:$src),
2774 def : Pat<(extloadi16 iaddr:$src),
2776 def : Pat<(extloadi16 xaddr:$src),
2778 def : Pat<(f64 (extloadf32 iaddr:$src)),
2779 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2780 def : Pat<(f64 (extloadf32 xaddr:$src)),
2781 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2783 def : Pat<(f64 (fextend f32:$src)),
2784 (COPY_TO_REGCLASS $src, F8RC)>;
2786 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2787 // All others can use the lightweight sync (SYNC 1).
2788 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2789 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2790 // versions of Power.
2791 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2792 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2793 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2794 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2796 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2797 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2798 (FNMSUB $A, $C, $B)>;
2799 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2800 (FNMSUB $A, $C, $B)>;
2801 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2802 (FNMSUBS $A, $C, $B)>;
2803 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2804 (FNMSUBS $A, $C, $B)>;
2806 // FCOPYSIGN's operand types need not agree.
2807 def : Pat<(fcopysign f64:$frB, f32:$frA),
2808 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2809 def : Pat<(fcopysign f32:$frB, f64:$frA),
2810 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2812 include "PPCInstrAltivec.td"
2813 include "PPCInstrSPE.td"
2814 include "PPCInstr64Bit.td"
2815 include "PPCInstrVSX.td"
2816 include "PPCInstrQPX.td"
2817 include "PPCInstrHTM.td"
2819 def crnot : OutPatFrag<(ops node:$in),
2821 def : Pat<(not i1:$in),
2824 // Patterns for arithmetic i1 operations.
2825 def : Pat<(add i1:$a, i1:$b),
2827 def : Pat<(sub i1:$a, i1:$b),
2829 def : Pat<(mul i1:$a, i1:$b),
2832 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2833 // (-1 is used to mean all bits set).
2834 def : Pat<(i1 -1), (CRSET)>;
2836 // i1 extensions, implemented in terms of isel.
2837 def : Pat<(i32 (zext i1:$in)),
2838 (SELECT_I4 $in, (LI 1), (LI 0))>;
2839 def : Pat<(i32 (sext i1:$in)),
2840 (SELECT_I4 $in, (LI -1), (LI 0))>;
2842 def : Pat<(i64 (zext i1:$in)),
2843 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2844 def : Pat<(i64 (sext i1:$in)),
2845 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2847 // FIXME: We should choose either a zext or a sext based on other constants
2849 def : Pat<(i32 (anyext i1:$in)),
2850 (SELECT_I4 $in, (LI 1), (LI 0))>;
2851 def : Pat<(i64 (anyext i1:$in)),
2852 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2854 // match setcc on i1 variables.
2872 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2874 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2893 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2895 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2898 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2912 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2914 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2928 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2930 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2933 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2936 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2937 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2938 // floating-point types.
2940 multiclass CRNotPat<dag pattern, dag result> {
2941 def : Pat<pattern, (crnot result)>;
2942 def : Pat<(not pattern), result>;
2944 // We can also fold the crnot into an extension:
2945 def : Pat<(i32 (zext pattern)),
2946 (SELECT_I4 result, (LI 0), (LI 1))>;
2947 def : Pat<(i32 (sext pattern)),
2948 (SELECT_I4 result, (LI 0), (LI -1))>;
2950 // We can also fold the crnot into an extension:
2951 def : Pat<(i64 (zext pattern)),
2952 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2953 def : Pat<(i64 (sext pattern)),
2954 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2956 // FIXME: We should choose either a zext or a sext based on other constants
2958 def : Pat<(i32 (anyext pattern)),
2959 (SELECT_I4 result, (LI 0), (LI 1))>;
2961 def : Pat<(i64 (anyext pattern)),
2962 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2965 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2966 // we need to write imm:$imm in the output patterns below, not just $imm, or
2967 // else the resulting matcher will not correctly add the immediate operand
2968 // (making it a register operand instead).
2971 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2972 OutPatFrag rfrag, OutPatFrag rfrag8> {
2973 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2975 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2977 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2978 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2979 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2980 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2982 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2984 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2986 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2987 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2988 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2989 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2992 // Note that we do all inversions below with i(32|64)not, instead of using
2993 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2994 // has 2-cycle latency.
2996 defm : ExtSetCCPat<SETEQ,
2997 PatFrag<(ops node:$in, node:$cc),
2998 (setcc $in, 0, $cc)>,
2999 OutPatFrag<(ops node:$in),
3000 (RLWINM (CNTLZW $in), 27, 31, 31)>,
3001 OutPatFrag<(ops node:$in),
3002 (RLDICL (CNTLZD $in), 58, 63)> >;
3004 defm : ExtSetCCPat<SETNE,
3005 PatFrag<(ops node:$in, node:$cc),
3006 (setcc $in, 0, $cc)>,
3007 OutPatFrag<(ops node:$in),
3008 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
3009 OutPatFrag<(ops node:$in),
3010 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3012 defm : ExtSetCCPat<SETLT,
3013 PatFrag<(ops node:$in, node:$cc),
3014 (setcc $in, 0, $cc)>,
3015 OutPatFrag<(ops node:$in),
3016 (RLWINM $in, 1, 31, 31)>,
3017 OutPatFrag<(ops node:$in),
3018 (RLDICL $in, 1, 63)> >;
3020 defm : ExtSetCCPat<SETGE,
3021 PatFrag<(ops node:$in, node:$cc),
3022 (setcc $in, 0, $cc)>,
3023 OutPatFrag<(ops node:$in),
3024 (RLWINM (i32not $in), 1, 31, 31)>,
3025 OutPatFrag<(ops node:$in),
3026 (RLDICL (i64not $in), 1, 63)> >;
3028 defm : ExtSetCCPat<SETGT,
3029 PatFrag<(ops node:$in, node:$cc),
3030 (setcc $in, 0, $cc)>,
3031 OutPatFrag<(ops node:$in),
3032 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
3033 OutPatFrag<(ops node:$in),
3034 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3036 defm : ExtSetCCPat<SETLE,
3037 PatFrag<(ops node:$in, node:$cc),
3038 (setcc $in, 0, $cc)>,
3039 OutPatFrag<(ops node:$in),
3040 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
3041 OutPatFrag<(ops node:$in),
3042 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3044 defm : ExtSetCCPat<SETLT,
3045 PatFrag<(ops node:$in, node:$cc),
3046 (setcc $in, -1, $cc)>,
3047 OutPatFrag<(ops node:$in),
3048 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
3049 OutPatFrag<(ops node:$in),
3050 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3052 defm : ExtSetCCPat<SETGE,
3053 PatFrag<(ops node:$in, node:$cc),
3054 (setcc $in, -1, $cc)>,
3055 OutPatFrag<(ops node:$in),
3056 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
3057 OutPatFrag<(ops node:$in),
3058 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3060 defm : ExtSetCCPat<SETGT,
3061 PatFrag<(ops node:$in, node:$cc),
3062 (setcc $in, -1, $cc)>,
3063 OutPatFrag<(ops node:$in),
3064 (RLWINM (i32not $in), 1, 31, 31)>,
3065 OutPatFrag<(ops node:$in),
3066 (RLDICL (i64not $in), 1, 63)> >;
3068 defm : ExtSetCCPat<SETLE,
3069 PatFrag<(ops node:$in, node:$cc),
3070 (setcc $in, -1, $cc)>,
3071 OutPatFrag<(ops node:$in),
3072 (RLWINM $in, 1, 31, 31)>,
3073 OutPatFrag<(ops node:$in),
3074 (RLDICL $in, 1, 63)> >;
3077 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3078 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3079 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3080 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3081 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3082 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3083 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3084 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3085 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3086 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3087 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3088 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3090 // For non-equality comparisons, the default code would materialize the
3091 // constant, then compare against it, like this:
3093 // ori r2, r2, 22136
3096 // Since we are just comparing for equality, we can emit this instead:
3097 // xoris r0,r3,0x1234
3098 // cmplwi cr0,r0,0x5678
3101 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3102 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3103 (LO16 imm:$imm)), sub_eq)>;
3105 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3106 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3107 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3108 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3109 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3110 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3111 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3112 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3113 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3114 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3115 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3116 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3118 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3119 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3120 (LO16 imm:$imm)), sub_eq)>;
3122 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3123 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3124 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3125 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3126 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3127 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3128 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3129 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3130 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3131 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3133 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3134 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3135 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3136 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3137 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3138 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3139 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3140 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3141 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3142 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3145 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3146 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3147 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3148 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3149 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3150 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3151 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3152 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3153 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3154 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3155 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3156 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3158 // For non-equality comparisons, the default code would materialize the
3159 // constant, then compare against it, like this:
3161 // ori r2, r2, 22136
3164 // Since we are just comparing for equality, we can emit this instead:
3165 // xoris r0,r3,0x1234
3166 // cmpldi cr0,r0,0x5678
3169 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3170 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3171 (LO16 imm:$imm)), sub_eq)>;
3173 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3174 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3175 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3176 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3177 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3178 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3179 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3180 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3181 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3182 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3183 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3184 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3186 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3187 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3188 (LO16 imm:$imm)), sub_eq)>;
3190 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3191 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3192 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3193 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3194 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3195 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3196 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3197 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3198 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3199 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3201 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3202 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3203 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3204 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3205 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3206 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3207 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3208 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3209 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3210 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3213 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3214 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3215 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3216 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3217 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3218 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3219 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3220 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3221 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3222 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3223 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3224 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3225 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3226 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3228 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3229 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3230 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3231 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3232 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3233 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3234 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3235 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3236 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3237 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3238 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3239 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3240 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3241 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3244 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3245 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3246 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3247 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3248 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3249 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3250 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3251 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3252 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3253 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3254 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3255 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3256 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3257 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3259 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3260 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3261 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3262 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3263 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3264 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3265 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3266 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3267 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3268 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3269 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3270 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3271 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3272 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3274 // match select on i1 variables:
3275 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3276 (CROR (CRAND $cond , $tval),
3277 (CRAND (crnot $cond), $fval))>;
3279 // match selectcc on i1 variables:
3280 // select (lhs == rhs), tval, fval is:
3281 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3282 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3283 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3284 (CRAND (CRORC $rhs, $lhs), $fval))>;
3285 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3286 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3287 (CRAND (CRORC $lhs, $rhs), $fval))>;
3288 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3289 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3290 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3291 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3292 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3293 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3294 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3295 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3296 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3297 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3298 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3299 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3300 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3301 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3302 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3303 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3304 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3305 (CRAND (CRORC $lhs, $rhs), $fval))>;
3306 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3307 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3308 (CRAND (CRORC $rhs, $lhs), $fval))>;
3309 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3310 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3311 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3313 // match selectcc on i1 variables with non-i1 output.
3314 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3315 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3316 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3317 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3318 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3319 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3320 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3321 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3322 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3323 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3324 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3325 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3326 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3327 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3328 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3329 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3330 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3331 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3332 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3333 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3335 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3336 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3337 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3338 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3339 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3340 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3341 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
3342 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3343 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3344 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3345 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3346 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3347 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
3348 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3349 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3350 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3351 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3352 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3353 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3354 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3356 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3357 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3358 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3359 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3360 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3361 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3362 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3363 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3364 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3365 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3366 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3367 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3368 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3369 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3370 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3371 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3372 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3373 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3374 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3375 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3377 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3378 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3379 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
3380 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3381 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3382 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3383 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
3384 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3385 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3386 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3387 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3388 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3389 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
3390 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3391 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3392 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3393 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
3394 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3395 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3396 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3398 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3399 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3400 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
3401 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3402 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3403 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3404 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
3405 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3406 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3407 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3408 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3409 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3410 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
3411 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3412 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3413 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3414 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
3415 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3416 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3417 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3419 let usesCustomInserter = 1 in {
3420 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3422 [(set i1:$dst, (trunc (not i32:$in)))]>;
3423 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3425 [(set i1:$dst, (trunc i32:$in))]>;
3427 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3429 [(set i1:$dst, (trunc (not i64:$in)))]>;
3430 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3432 [(set i1:$dst, (trunc i64:$in))]>;
3435 def : Pat<(i1 (not (trunc i32:$in))),
3436 (ANDIo_1_EQ_BIT $in)>;
3437 def : Pat<(i1 (not (trunc i64:$in))),
3438 (ANDIo_1_EQ_BIT8 $in)>;
3440 //===----------------------------------------------------------------------===//
3441 // PowerPC Instructions used for assembler/disassembler only
3444 // FIXME: For B=0 or B > 8, the registers following RT are used.
3445 // WARNING: Do not add patterns for this instruction without fixing this.
3446 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3447 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3449 // FIXME: For B=0 or B > 8, the registers following RT are used.
3450 // WARNING: Do not add patterns for this instruction without fixing this.
3451 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3452 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3454 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3455 "isync", IIC_SprISYNC, []>;
3457 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3458 "icbi $src", IIC_LdStICBI, []>;
3460 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3461 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3462 "eieio", IIC_LdStLoad, []>;
3464 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3465 "wait $L", IIC_LdStLoad, []>;
3467 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3468 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3470 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3471 "mtsr $SR, $RS", IIC_SprMTSR>;
3473 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3474 "mfsr $RS, $SR", IIC_SprMFSR>;
3476 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3477 "mtsrin $RS, $RB", IIC_SprMTSR>;
3479 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3480 "mfsrin $RS, $RB", IIC_SprMFSR>;
3482 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3483 "mtmsr $RS, $L", IIC_SprMTMSR>;
3485 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3486 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3490 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3491 Requires<[IsBookE]> {
3495 let Inst{21-30} = 163;
3498 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3499 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3500 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3501 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3503 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3504 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3505 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3506 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3508 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3509 "mfmsr $RT", IIC_SprMFMSR, []>;
3511 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3512 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3514 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3515 "mcrfs $BF, $BFA", IIC_BrMCR>;
3517 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3518 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3520 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3521 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3523 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3524 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3526 def MTFSF : XFLForm_1<63, 711, (outs),
3527 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3528 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3529 def MTFSFo : XFLForm_1<63, 711, (outs),
3530 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3531 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3533 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3534 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3536 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3537 "slbie $RB", IIC_SprSLBIE, []>;
3539 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3540 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3542 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3543 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3545 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3547 def TLBIA : XForm_0<31, 370, (outs), (ins),
3548 "tlbia", IIC_SprTLBIA, []>;
3550 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3551 "tlbsync", IIC_SprTLBSYNC, []>;
3553 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3554 "tlbiel $RB", IIC_SprTLBIEL, []>;
3556 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3557 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3558 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3559 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3561 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3562 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3564 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3565 IIC_LdStLoad>, Requires<[IsBookE]>;
3567 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3568 IIC_LdStLoad>, Requires<[IsBookE]>;
3570 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3571 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3573 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3574 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3576 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3577 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3579 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3580 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3582 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3583 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3584 Requires<[IsPPC4xx]>;
3585 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3586 (ins gprc:$RST, gprc:$A, gprc:$B),
3587 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3588 Requires<[IsPPC4xx]>, isDOT;
3590 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3592 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3593 Requires<[IsBookE]>;
3594 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3595 Requires<[IsBookE]>;
3597 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3599 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3602 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3603 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3604 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3605 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3607 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3609 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3610 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3611 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3612 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3613 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3614 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3615 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3616 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3618 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3619 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3620 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3621 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3622 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3623 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3624 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3625 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3627 //===----------------------------------------------------------------------===//
3628 // PowerPC Assembler Instruction Aliases
3631 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3632 // These are aliases that require C++ handling to convert to the target
3633 // instruction, while InstAliases can be handled directly by tblgen.
3634 class PPCAsmPseudo<string asm, dag iops>
3636 let Namespace = "PPC";
3637 bit PPC64 = 0; // Default value, override with isPPC64
3639 let OutOperandList = (outs);
3640 let InOperandList = iops;
3642 let AsmString = asm;
3643 let isAsmParserOnly = 1;
3647 def : InstAlias<"sc", (SC 0)>;
3649 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3650 def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3651 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3652 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3654 def : InstAlias<"wait", (WAIT 0)>;
3655 def : InstAlias<"waitrsv", (WAIT 1)>;
3656 def : InstAlias<"waitimpl", (WAIT 2)>;
3658 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3660 def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3661 def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3663 def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3664 def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3665 def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3667 def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3668 def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3669 def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3671 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3672 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3673 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3674 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3676 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3677 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3679 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3680 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3682 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3683 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3685 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3686 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3688 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3689 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3691 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3692 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3694 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3695 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3697 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3698 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3700 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3701 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3703 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3704 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3706 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3707 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3709 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3710 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3712 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3713 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3715 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3716 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3718 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3719 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3720 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3722 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3723 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3725 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3726 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3727 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3728 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3730 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3732 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3733 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3735 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3736 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3738 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3740 foreach BATR = 0-3 in {
3741 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3742 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3743 Requires<[IsPPC6xx]>;
3744 def : InstAlias<"mfdbatu $Rx, "#BATR,
3745 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3746 Requires<[IsPPC6xx]>;
3747 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3748 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3749 Requires<[IsPPC6xx]>;
3750 def : InstAlias<"mfdbatl $Rx, "#BATR,
3751 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3752 Requires<[IsPPC6xx]>;
3753 def : InstAlias<"mtibatu "#BATR#", $Rx",
3754 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3755 Requires<[IsPPC6xx]>;
3756 def : InstAlias<"mfibatu $Rx, "#BATR,
3757 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3758 Requires<[IsPPC6xx]>;
3759 def : InstAlias<"mtibatl "#BATR#", $Rx",
3760 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3761 Requires<[IsPPC6xx]>;
3762 def : InstAlias<"mfibatl $Rx, "#BATR,
3763 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3764 Requires<[IsPPC6xx]>;
3767 foreach BR = 0-7 in {
3768 def : InstAlias<"mfbr"#BR#" $Rx",
3769 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3770 Requires<[IsPPC4xx]>;
3771 def : InstAlias<"mtbr"#BR#" $Rx",
3772 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3773 Requires<[IsPPC4xx]>;
3776 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3777 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3779 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3780 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3782 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3783 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3785 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3786 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3788 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3789 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3791 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3792 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3794 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3796 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3797 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3798 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3799 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3800 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3801 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3802 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3803 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3805 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3806 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3807 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3808 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3810 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3811 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3813 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3814 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3816 foreach SPRG = 0-3 in {
3817 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3818 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3819 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3820 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3822 foreach SPRG = 4-7 in {
3823 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3824 Requires<[IsBookE]>;
3825 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3826 Requires<[IsBookE]>;
3827 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3828 Requires<[IsBookE]>;
3829 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3830 Requires<[IsBookE]>;
3833 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3835 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3836 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3838 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3840 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3841 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3843 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3844 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3845 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3846 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3848 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3850 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3851 Requires<[IsPPC4xx]>;
3852 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3853 Requires<[IsPPC4xx]>;
3854 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3855 Requires<[IsPPC4xx]>;
3856 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3857 Requires<[IsPPC4xx]>;
3859 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3860 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3861 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3862 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3863 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3864 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3865 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3866 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3867 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3868 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3869 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3870 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3871 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3872 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3873 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3874 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3875 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3876 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3877 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3878 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3879 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3880 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3881 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3882 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3883 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3884 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3885 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3886 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3887 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3888 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3889 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3890 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3891 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3892 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3893 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3894 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3896 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3897 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3898 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3899 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3900 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3901 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3903 def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3904 def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3905 // The POWER variant
3906 def : MnemonicAlias<"cntlz", "cntlzw">;
3907 def : MnemonicAlias<"cntlz.", "cntlzw.">;
3909 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3910 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3911 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3912 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3913 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3914 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3915 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3916 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3917 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3918 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3919 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3920 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3921 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3922 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3923 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3924 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3925 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3926 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3927 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3928 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3929 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3930 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3931 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3932 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3933 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3934 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3935 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3936 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3937 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3938 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3939 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3940 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3942 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3943 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3944 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3945 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3946 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3947 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3949 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
3950 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3951 def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
3952 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3953 def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
3954 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3955 def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
3956 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3957 def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
3958 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3959 def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
3960 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3962 // These generic branch instruction forms are used for the assembler parser only.
3963 // Defs and Uses are conservative, since we don't know the BO value.
3964 let PPC970_Unit = 7 in {
3965 let Defs = [CTR], Uses = [CTR, RM] in {
3966 def gBC : BForm_3<16, 0, 0, (outs),
3967 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3968 "bc $bo, $bi, $dst">;
3969 def gBCA : BForm_3<16, 1, 0, (outs),
3970 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3971 "bca $bo, $bi, $dst">;
3973 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3974 def gBCL : BForm_3<16, 0, 1, (outs),
3975 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3976 "bcl $bo, $bi, $dst">;
3977 def gBCLA : BForm_3<16, 1, 1, (outs),
3978 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3979 "bcla $bo, $bi, $dst">;
3981 let Defs = [CTR], Uses = [CTR, LR, RM] in
3982 def gBCLR : XLForm_2<19, 16, 0, (outs),
3983 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3984 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3985 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3986 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3987 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3988 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3989 let Defs = [CTR], Uses = [CTR, LR, RM] in
3990 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3991 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3992 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3993 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3994 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3995 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3996 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3998 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3999 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
4000 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
4001 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
4003 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
4004 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
4005 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4006 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
4007 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
4008 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4009 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
4011 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
4012 : BranchSimpleMnemonic1<name, pm, bo> {
4013 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
4014 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
4016 defm : BranchSimpleMnemonic2<"t", "", 12>;
4017 defm : BranchSimpleMnemonic2<"f", "", 4>;
4018 defm : BranchSimpleMnemonic2<"t", "-", 14>;
4019 defm : BranchSimpleMnemonic2<"f", "-", 6>;
4020 defm : BranchSimpleMnemonic2<"t", "+", 15>;
4021 defm : BranchSimpleMnemonic2<"f", "+", 7>;
4022 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
4023 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
4024 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
4025 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
4027 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
4028 def : InstAlias<"b"#name#pm#" $cc, $dst",
4029 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
4030 def : InstAlias<"b"#name#pm#" $dst",
4031 (BCC bibo, CR0, condbrtarget:$dst)>;
4033 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
4034 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4035 def : InstAlias<"b"#name#"a"#pm#" $dst",
4036 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
4038 def : InstAlias<"b"#name#"lr"#pm#" $cc",
4039 (BCCLR bibo, crrc:$cc)>;
4040 def : InstAlias<"b"#name#"lr"#pm,
4043 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
4044 (BCCCTR bibo, crrc:$cc)>;
4045 def : InstAlias<"b"#name#"ctr"#pm,
4046 (BCCCTR bibo, CR0)>;
4048 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
4049 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
4050 def : InstAlias<"b"#name#"l"#pm#" $dst",
4051 (BCCL bibo, CR0, condbrtarget:$dst)>;
4053 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
4054 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4055 def : InstAlias<"b"#name#"la"#pm#" $dst",
4056 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
4058 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
4059 (BCCLRL bibo, crrc:$cc)>;
4060 def : InstAlias<"b"#name#"lrl"#pm,
4061 (BCCLRL bibo, CR0)>;
4063 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
4064 (BCCCTRL bibo, crrc:$cc)>;
4065 def : InstAlias<"b"#name#"ctrl"#pm,
4066 (BCCCTRL bibo, CR0)>;
4068 multiclass BranchExtendedMnemonic<string name, int bibo> {
4069 defm : BranchExtendedMnemonicPM<name, "", bibo>;
4070 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
4071 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
4073 defm : BranchExtendedMnemonic<"lt", 12>;
4074 defm : BranchExtendedMnemonic<"gt", 44>;
4075 defm : BranchExtendedMnemonic<"eq", 76>;
4076 defm : BranchExtendedMnemonic<"un", 108>;
4077 defm : BranchExtendedMnemonic<"so", 108>;
4078 defm : BranchExtendedMnemonic<"ge", 4>;
4079 defm : BranchExtendedMnemonic<"nl", 4>;
4080 defm : BranchExtendedMnemonic<"le", 36>;
4081 defm : BranchExtendedMnemonic<"ng", 36>;
4082 defm : BranchExtendedMnemonic<"ne", 68>;
4083 defm : BranchExtendedMnemonic<"nu", 100>;
4084 defm : BranchExtendedMnemonic<"ns", 100>;
4086 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
4087 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
4088 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
4089 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
4090 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
4091 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
4092 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
4093 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
4095 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
4096 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
4097 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
4098 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
4099 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
4100 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4101 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
4102 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4104 multiclass TrapExtendedMnemonic<string name, int to> {
4105 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
4106 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
4107 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
4108 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
4110 defm : TrapExtendedMnemonic<"lt", 16>;
4111 defm : TrapExtendedMnemonic<"le", 20>;
4112 defm : TrapExtendedMnemonic<"eq", 4>;
4113 defm : TrapExtendedMnemonic<"ge", 12>;
4114 defm : TrapExtendedMnemonic<"gt", 8>;
4115 defm : TrapExtendedMnemonic<"nl", 12>;
4116 defm : TrapExtendedMnemonic<"ne", 24>;
4117 defm : TrapExtendedMnemonic<"ng", 20>;
4118 defm : TrapExtendedMnemonic<"llt", 2>;
4119 defm : TrapExtendedMnemonic<"lle", 6>;
4120 defm : TrapExtendedMnemonic<"lge", 5>;
4121 defm : TrapExtendedMnemonic<"lgt", 1>;
4122 defm : TrapExtendedMnemonic<"lnl", 5>;
4123 defm : TrapExtendedMnemonic<"lng", 6>;
4124 defm : TrapExtendedMnemonic<"u", 31>;
4127 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
4128 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
4129 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
4130 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
4131 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4132 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4135 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
4136 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
4137 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
4138 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4139 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4140 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;