1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
57 //===----------------------------------------------------------------------===//
58 // PowerPC specific DAG Nodes.
61 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
62 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
63 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
64 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
65 [SDNPHasChain, SDNPMayStore]>;
67 // Extract FPSCR (not modeled at the DAG level).
68 def PPCmffs : SDNode<"PPCISD::MFFS",
69 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
71 // Perform FADD in round-to-zero mode.
72 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
75 def PPCfsel : SDNode<"PPCISD::FSEL",
76 // Type constraint for fsel.
77 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
78 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
80 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
81 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
82 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
83 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
84 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
86 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
87 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
89 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
90 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
91 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
92 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
93 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
94 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
95 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
96 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
98 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
100 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
102 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
103 // amounts. These nodes are generated by the multi-precision shift code.
104 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
105 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
106 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
108 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
109 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
110 [SDNPHasChain, SDNPMayStore]>;
112 // These are target-independent nodes, but have target-specific formats.
113 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
114 [SDNPHasChain, SDNPOutGlue]>;
115 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
118 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
119 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
123 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
125 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
126 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
127 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
128 [SDNPHasChain, SDNPSideEffect,
129 SDNPInGlue, SDNPOutGlue]>;
130 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
131 [SDNPHasChain, SDNPSideEffect,
132 SDNPInGlue, SDNPOutGlue]>;
133 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
136 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
140 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
143 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
146 SDTypeProfile<1, 1, [SDTCisInt<0>,
148 [SDNPHasChain, SDNPSideEffect]>;
149 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
150 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
151 [SDNPHasChain, SDNPSideEffect]>;
153 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
154 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
156 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
157 [SDNPHasChain, SDNPOptInGlue]>;
159 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
160 [SDNPHasChain, SDNPMayLoad]>;
161 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
162 [SDNPHasChain, SDNPMayStore]>;
164 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
165 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
166 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
167 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
168 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
170 // Instructions to support atomic operations
171 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
172 [SDNPHasChain, SDNPMayLoad]>;
173 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
174 [SDNPHasChain, SDNPMayStore]>;
176 // Instructions to support medium and large code model
177 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
178 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
179 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
182 // Instructions to support dynamic alloca.
183 def SDTDynOp : SDTypeProfile<1, 2, []>;
184 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
186 //===----------------------------------------------------------------------===//
187 // PowerPC specific transformation functions and pattern fragments.
190 def SHL32 : SDNodeXForm<imm, [{
191 // Transformation function: 31 - imm
192 return getI32Imm(31 - N->getZExtValue());
195 def SRL32 : SDNodeXForm<imm, [{
196 // Transformation function: 32 - imm
197 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
200 def LO16 : SDNodeXForm<imm, [{
201 // Transformation function: get the low 16 bits.
202 return getI32Imm((unsigned short)N->getZExtValue());
205 def HI16 : SDNodeXForm<imm, [{
206 // Transformation function: shift the immediate value down into the low bits.
207 return getI32Imm((unsigned)N->getZExtValue() >> 16);
210 def HA16 : SDNodeXForm<imm, [{
211 // Transformation function: shift the immediate value down into the low bits.
212 signed int Val = N->getZExtValue();
213 return getI32Imm((Val - (signed short)Val) >> 16);
215 def MB : SDNodeXForm<imm, [{
216 // Transformation function: get the start bit of a mask
218 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
219 return getI32Imm(mb);
222 def ME : SDNodeXForm<imm, [{
223 // Transformation function: get the end bit of a mask
225 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
226 return getI32Imm(me);
228 def maskimm32 : PatLeaf<(imm), [{
229 // maskImm predicate - True if immediate is a run of ones.
231 if (N->getValueType(0) == MVT::i32)
232 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 def immSExt16 : PatLeaf<(imm), [{
238 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
239 // field. Used by instructions like 'addi'.
240 if (N->getValueType(0) == MVT::i32)
241 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
243 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
245 def immZExt16 : PatLeaf<(imm), [{
246 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
247 // field. Used by instructions like 'ori'.
248 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
251 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
252 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
253 // identical in 32-bit mode, but in 64-bit mode, they return true if the
254 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
256 def imm16ShiftedZExt : PatLeaf<(imm), [{
257 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
258 // immediate are set. Used by instructions like 'xoris'.
259 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
262 def imm16ShiftedSExt : PatLeaf<(imm), [{
263 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
264 // immediate are set. Used by instructions like 'addis'. Identical to
265 // imm16ShiftedZExt in 32-bit mode.
266 if (N->getZExtValue() & 0xFFFF) return false;
267 if (N->getValueType(0) == MVT::i32)
269 // For 64-bit, make sure it is sext right.
270 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
273 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
274 // restricted memrix (offset/4) constants are alignment sensitive. If these
275 // offsets are hidden behind TOC entries than the values of the lower-order
276 // bits cannot be checked directly. As a result, we need to also incorporate
277 // an alignment check into the relevant patterns.
279 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
280 return cast<LoadSDNode>(N)->getAlignment() >= 4;
282 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
283 (store node:$val, node:$ptr), [{
284 return cast<StoreSDNode>(N)->getAlignment() >= 4;
286 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
287 return cast<LoadSDNode>(N)->getAlignment() >= 4;
289 def aligned4pre_store : PatFrag<
290 (ops node:$val, node:$base, node:$offset),
291 (pre_store node:$val, node:$base, node:$offset), [{
292 return cast<StoreSDNode>(N)->getAlignment() >= 4;
295 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
296 return cast<LoadSDNode>(N)->getAlignment() < 4;
298 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
299 (store node:$val, node:$ptr), [{
300 return cast<StoreSDNode>(N)->getAlignment() < 4;
302 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
303 return cast<LoadSDNode>(N)->getAlignment() < 4;
306 //===----------------------------------------------------------------------===//
307 // PowerPC Flag Definitions.
309 class isPPC64 { bit PPC64 = 1; }
311 list<Register> Defs = [CR0];
315 class RegConstraint<string C> {
316 string Constraints = C;
318 class NoEncode<string E> {
319 string DisableEncoding = E;
323 //===----------------------------------------------------------------------===//
324 // PowerPC Operand Definitions.
326 def s5imm : Operand<i32> {
327 let PrintMethod = "printS5ImmOperand";
329 def u5imm : Operand<i32> {
330 let PrintMethod = "printU5ImmOperand";
332 def u6imm : Operand<i32> {
333 let PrintMethod = "printU6ImmOperand";
335 def s16imm : Operand<i32> {
336 let PrintMethod = "printS16ImmOperand";
338 def u16imm : Operand<i32> {
339 let PrintMethod = "printU16ImmOperand";
341 def directbrtarget : Operand<OtherVT> {
342 let PrintMethod = "printBranchOperand";
343 let EncoderMethod = "getDirectBrEncoding";
345 def condbrtarget : Operand<OtherVT> {
346 let PrintMethod = "printBranchOperand";
347 let EncoderMethod = "getCondBrEncoding";
349 def calltarget : Operand<iPTR> {
350 let EncoderMethod = "getDirectBrEncoding";
352 def aaddr : Operand<iPTR> {
353 let PrintMethod = "printAbsAddrOperand";
355 def symbolHi: Operand<i32> {
356 let PrintMethod = "printSymbolHi";
357 let EncoderMethod = "getHA16Encoding";
359 def symbolLo: Operand<i32> {
360 let PrintMethod = "printSymbolLo";
361 let EncoderMethod = "getLO16Encoding";
363 def crbitm: Operand<i8> {
364 let PrintMethod = "printcrbitm";
365 let EncoderMethod = "get_crbitm_encoding";
368 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
369 def ptr_rc_nor0 : PointerLikeRegClass<1>;
371 def dispRI : Operand<iPTR>;
372 def dispRIX : Operand<iPTR>;
374 def memri : Operand<iPTR> {
375 let PrintMethod = "printMemRegImm";
376 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
377 let EncoderMethod = "getMemRIEncoding";
379 def memrr : Operand<iPTR> {
380 let PrintMethod = "printMemRegReg";
381 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc:$offreg);
383 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
384 let PrintMethod = "printMemRegImmShifted";
385 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
386 let EncoderMethod = "getMemRIXEncoding";
389 // A single-register address. This is used with the SjLj
390 // pseudo-instructions.
391 def memr : Operand<iPTR> {
392 let MIOperandInfo = (ops ptr_rc:$ptrreg);
395 // PowerPC Predicate operand.
396 def pred : Operand<OtherVT> {
397 let PrintMethod = "printPredicateOperand";
398 let MIOperandInfo = (ops i32imm:$bibo, CRRC:$reg);
401 // Define PowerPC specific addressing mode.
402 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
403 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
404 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
405 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
407 // The address in a single register. This is used with the SjLj
408 // pseudo-instructions.
409 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
411 /// This is just the offset part of iaddr, used for preinc.
412 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
414 //===----------------------------------------------------------------------===//
415 // PowerPC Instruction Predicate Definitions.
416 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
417 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
418 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
420 //===----------------------------------------------------------------------===//
421 // PowerPC Instruction Definitions.
423 // Pseudo-instructions:
425 let hasCtrlDep = 1 in {
426 let Defs = [R1], Uses = [R1] in {
427 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
428 [(callseq_start timm:$amt)]>;
429 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
430 [(callseq_end timm:$amt1, timm:$amt2)]>;
433 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
434 "UPDATE_VRSAVE $rD, $rS", []>;
437 let Defs = [R1], Uses = [R1] in
438 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
440 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
442 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
443 // instruction selection into a branch sequence.
444 let usesCustomInserter = 1, // Expanded after instruction selection.
445 PPC970_Single = 1 in {
446 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
447 i32imm:$BROPC), "#SELECT_CC_I4",
449 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
450 i32imm:$BROPC), "#SELECT_CC_I8",
452 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
453 i32imm:$BROPC), "#SELECT_CC_F4",
455 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
456 i32imm:$BROPC), "#SELECT_CC_F8",
458 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
459 i32imm:$BROPC), "#SELECT_CC_VRRC",
463 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
464 // scavenge a register for it.
466 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
469 // RESTORE_CR - Indicate that we're restoring the CR register (previously
470 // spilled), so we'll need to scavenge a register for it.
472 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
475 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
476 let isReturn = 1, Uses = [LR, RM] in
477 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
479 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
480 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
484 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
487 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
488 let isBarrier = 1 in {
489 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
494 // BCC represents an arbitrary conditional branch on a predicate.
495 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
496 // a two-value operand where a dag node expects two operands. :(
497 let isCodeGenOnly = 1 in
498 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
499 "b${cond:cc} ${cond:reg}, $dst"
500 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
502 let Defs = [CTR], Uses = [CTR] in {
503 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
505 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
510 // The direct BCL used by the SjLj setjmp code.
511 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
512 let Defs = [LR], Uses = [RM] in {
513 def BCL : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
518 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
519 // Convenient aliases for call instructions
521 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
522 "bl $func", BrB, []>; // See Pat patterns below.
523 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
524 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
526 let Uses = [CTR, RM] in {
527 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
528 "bctrl", BrB, [(PPCbctrl)]>,
529 Requires<[In32BitMode]>;
533 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
534 def TCRETURNdi :Pseudo< (outs),
535 (ins calltarget:$dst, i32imm:$offset),
536 "#TC_RETURNd $dst $offset",
540 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
541 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
542 "#TC_RETURNa $func $offset",
543 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
545 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
546 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
547 "#TC_RETURNr $dst $offset",
551 let isCodeGenOnly = 1 in {
553 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
554 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
555 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
556 Requires<[In32BitMode]>;
560 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
561 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
562 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
568 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
569 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
570 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
574 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
575 def EH_SjLj_SetJmp32 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
577 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
578 Requires<[In32BitMode]>;
579 let isTerminator = 1 in
580 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
581 "#EH_SJLJ_LONGJMP32",
582 [(PPCeh_sjlj_longjmp addr:$buf)]>,
583 Requires<[In32BitMode]>;
586 let isBranch = 1, isTerminator = 1 in {
587 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
588 "#EH_SjLj_Setup\t$dst", []>;
591 // DCB* instructions.
592 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
593 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
594 PPC970_DGroup_Single;
595 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
596 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
597 PPC970_DGroup_Single;
598 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
599 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
600 PPC970_DGroup_Single;
601 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
602 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
603 PPC970_DGroup_Single;
604 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
605 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
606 PPC970_DGroup_Single;
607 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
608 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
609 PPC970_DGroup_Single;
610 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
611 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
612 PPC970_DGroup_Single;
613 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
614 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
615 PPC970_DGroup_Single;
617 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
621 let usesCustomInserter = 1 in {
622 let Defs = [CR0] in {
623 def ATOMIC_LOAD_ADD_I8 : Pseudo<
624 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
625 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
626 def ATOMIC_LOAD_SUB_I8 : Pseudo<
627 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
628 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
629 def ATOMIC_LOAD_AND_I8 : Pseudo<
630 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
631 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
632 def ATOMIC_LOAD_OR_I8 : Pseudo<
633 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
634 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
635 def ATOMIC_LOAD_XOR_I8 : Pseudo<
636 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
637 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
638 def ATOMIC_LOAD_NAND_I8 : Pseudo<
639 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
640 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
641 def ATOMIC_LOAD_ADD_I16 : Pseudo<
642 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
643 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
644 def ATOMIC_LOAD_SUB_I16 : Pseudo<
645 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
646 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
647 def ATOMIC_LOAD_AND_I16 : Pseudo<
648 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
649 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
650 def ATOMIC_LOAD_OR_I16 : Pseudo<
651 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
652 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
653 def ATOMIC_LOAD_XOR_I16 : Pseudo<
654 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
655 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
656 def ATOMIC_LOAD_NAND_I16 : Pseudo<
657 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
658 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
659 def ATOMIC_LOAD_ADD_I32 : Pseudo<
660 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
661 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
662 def ATOMIC_LOAD_SUB_I32 : Pseudo<
663 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
664 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
665 def ATOMIC_LOAD_AND_I32 : Pseudo<
666 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
667 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
668 def ATOMIC_LOAD_OR_I32 : Pseudo<
669 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
670 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
671 def ATOMIC_LOAD_XOR_I32 : Pseudo<
672 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
673 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
674 def ATOMIC_LOAD_NAND_I32 : Pseudo<
675 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
676 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
678 def ATOMIC_CMP_SWAP_I8 : Pseudo<
679 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
680 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
681 def ATOMIC_CMP_SWAP_I16 : Pseudo<
682 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
683 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
684 def ATOMIC_CMP_SWAP_I32 : Pseudo<
685 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
686 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
688 def ATOMIC_SWAP_I8 : Pseudo<
689 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
690 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
691 def ATOMIC_SWAP_I16 : Pseudo<
692 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
693 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
694 def ATOMIC_SWAP_I32 : Pseudo<
695 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
696 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
700 // Instructions to support atomic operations
701 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
702 "lwarx $rD, $src", LdStLWARX,
703 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
706 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
707 "stwcx. $rS, $dst", LdStSTWCX,
708 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
711 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
712 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
714 //===----------------------------------------------------------------------===//
715 // PPC32 Load Instructions.
718 // Unindexed (r+i) Loads.
719 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
720 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
721 "lbz $rD, $src", LdStLoad,
722 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
723 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
724 "lha $rD, $src", LdStLHA,
725 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
726 PPC970_DGroup_Cracked;
727 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
728 "lhz $rD, $src", LdStLoad,
729 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
730 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
731 "lwz $rD, $src", LdStLoad,
732 [(set i32:$rD, (load iaddr:$src))]>;
734 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
735 "lfs $rD, $src", LdStLFD,
736 [(set f32:$rD, (load iaddr:$src))]>;
737 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
738 "lfd $rD, $src", LdStLFD,
739 [(set f64:$rD, (load iaddr:$src))]>;
742 // Unindexed (r+i) Loads with Update (preinc).
744 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
745 "lbzu $rD, $addr", LdStLoadUpd,
746 []>, RegConstraint<"$addr.reg = $ea_result">,
747 NoEncode<"$ea_result">;
749 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
750 "lhau $rD, $addr", LdStLHAU,
751 []>, RegConstraint<"$addr.reg = $ea_result">,
752 NoEncode<"$ea_result">;
754 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
755 "lhzu $rD, $addr", LdStLoadUpd,
756 []>, RegConstraint<"$addr.reg = $ea_result">,
757 NoEncode<"$ea_result">;
759 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
760 "lwzu $rD, $addr", LdStLoadUpd,
761 []>, RegConstraint<"$addr.reg = $ea_result">,
762 NoEncode<"$ea_result">;
764 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
765 "lfsu $rD, $addr", LdStLFDU,
766 []>, RegConstraint<"$addr.reg = $ea_result">,
767 NoEncode<"$ea_result">;
769 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
770 "lfdu $rD, $addr", LdStLFDU,
771 []>, RegConstraint<"$addr.reg = $ea_result">,
772 NoEncode<"$ea_result">;
775 // Indexed (r+r) Loads with Update (preinc).
776 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
778 "lbzux $rD, $addr", LdStLoadUpd,
779 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
780 NoEncode<"$ea_result">;
782 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
784 "lhaux $rD, $addr", LdStLHAU,
785 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
786 NoEncode<"$ea_result">;
788 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
790 "lhzux $rD, $addr", LdStLoadUpd,
791 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
792 NoEncode<"$ea_result">;
794 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
796 "lwzux $rD, $addr", LdStLoadUpd,
797 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
798 NoEncode<"$ea_result">;
800 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result),
802 "lfsux $rD, $addr", LdStLFDU,
803 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
804 NoEncode<"$ea_result">;
806 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result),
808 "lfdux $rD, $addr", LdStLFDU,
809 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
810 NoEncode<"$ea_result">;
814 // Indexed (r+r) Loads.
816 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
817 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
818 "lbzx $rD, $src", LdStLoad,
819 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
820 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
821 "lhax $rD, $src", LdStLHA,
822 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
823 PPC970_DGroup_Cracked;
824 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
825 "lhzx $rD, $src", LdStLoad,
826 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
827 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
828 "lwzx $rD, $src", LdStLoad,
829 [(set i32:$rD, (load xaddr:$src))]>;
832 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
833 "lhbrx $rD, $src", LdStLoad,
834 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
835 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
836 "lwbrx $rD, $src", LdStLoad,
837 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
839 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
840 "lfsx $frD, $src", LdStLFD,
841 [(set f32:$frD, (load xaddr:$src))]>;
842 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
843 "lfdx $frD, $src", LdStLFD,
844 [(set f64:$frD, (load xaddr:$src))]>;
847 //===----------------------------------------------------------------------===//
848 // PPC32 Store Instructions.
851 // Unindexed (r+i) Stores.
852 let PPC970_Unit = 2 in {
853 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
854 "stb $rS, $src", LdStStore,
855 [(truncstorei8 i32:$rS, iaddr:$src)]>;
856 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
857 "sth $rS, $src", LdStStore,
858 [(truncstorei16 i32:$rS, iaddr:$src)]>;
859 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
860 "stw $rS, $src", LdStStore,
861 [(store i32:$rS, iaddr:$src)]>;
862 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
863 "stfs $rS, $dst", LdStSTFD,
864 [(store f32:$rS, iaddr:$dst)]>;
865 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
866 "stfd $rS, $dst", LdStSTFD,
867 [(store f64:$rS, iaddr:$dst)]>;
870 // Unindexed (r+i) Stores with Update (preinc).
871 let PPC970_Unit = 2, mayStore = 1 in {
872 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
873 "stbu $rS, $dst", LdStStoreUpd, []>,
874 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
875 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
876 "sthu $rS, $dst", LdStStoreUpd, []>,
877 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
878 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
879 "stwu $rS, $dst", LdStStoreUpd, []>,
880 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
881 def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst),
882 "stfsu $rS, $dst", LdStSTFDU, []>,
883 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
884 def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
885 "stfdu $rS, $dst", LdStSTFDU, []>,
886 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
889 // Patterns to match the pre-inc stores. We can't put the patterns on
890 // the instruction definitions directly as ISel wants the address base
891 // and offset to be separate operands, not a single complex operand.
892 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
893 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
894 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
895 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
896 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
897 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
898 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
899 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
900 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
901 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
903 // Indexed (r+r) Stores.
904 let PPC970_Unit = 2 in {
905 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
906 "stbx $rS, $dst", LdStStore,
907 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
908 PPC970_DGroup_Cracked;
909 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
910 "sthx $rS, $dst", LdStStore,
911 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
912 PPC970_DGroup_Cracked;
913 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
914 "stwx $rS, $dst", LdStStore,
915 [(store i32:$rS, xaddr:$dst)]>,
916 PPC970_DGroup_Cracked;
918 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
919 "sthbrx $rS, $dst", LdStStore,
920 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
921 PPC970_DGroup_Cracked;
922 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
923 "stwbrx $rS, $dst", LdStStore,
924 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
925 PPC970_DGroup_Cracked;
927 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
928 "stfiwx $frS, $dst", LdStSTFD,
929 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
931 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
932 "stfsx $frS, $dst", LdStSTFD,
933 [(store f32:$frS, xaddr:$dst)]>;
934 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
935 "stfdx $frS, $dst", LdStSTFD,
936 [(store f64:$frS, xaddr:$dst)]>;
939 // Indexed (r+r) Stores with Update (preinc).
940 let PPC970_Unit = 2, mayStore = 1 in {
941 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
942 "stbux $rS, $dst", LdStStoreUpd, []>,
943 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
944 PPC970_DGroup_Cracked;
945 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
946 "sthux $rS, $dst", LdStStoreUpd, []>,
947 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
948 PPC970_DGroup_Cracked;
949 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
950 "stwux $rS, $dst", LdStStoreUpd, []>,
951 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
952 PPC970_DGroup_Cracked;
953 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst),
954 "stfsux $rS, $dst", LdStSTFDU, []>,
955 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
956 PPC970_DGroup_Cracked;
957 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst),
958 "stfdux $rS, $dst", LdStSTFDU, []>,
959 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
960 PPC970_DGroup_Cracked;
963 // Patterns to match the pre-inc stores. We can't put the patterns on
964 // the instruction definitions directly as ISel wants the address base
965 // and offset to be separate operands, not a single complex operand.
966 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
967 (STBUX $rS, $ptrreg, $ptroff)>;
968 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
969 (STHUX $rS, $ptrreg, $ptroff)>;
970 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
971 (STWUX $rS, $ptrreg, $ptroff)>;
972 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
973 (STFSUX $rS, $ptrreg, $ptroff)>;
974 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
975 (STFDUX $rS, $ptrreg, $ptroff)>;
977 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
981 //===----------------------------------------------------------------------===//
982 // PPC32 Arithmetic Instructions.
985 let PPC970_Unit = 1 in { // FXU Operations.
986 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm),
987 "addi $rD, $rA, $imm", IntSimple,
988 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>;
989 let Defs = [CARRY] in {
990 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
991 "addic $rD, $rA, $imm", IntGeneral,
992 [(set i32:$rD, (addc i32:$rA, immSExt16:$imm))]>,
993 PPC970_DGroup_Cracked;
994 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
995 "addic. $rD, $rA, $imm", IntGeneral,
998 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm),
999 "addis $rD, $rA, $imm", IntSimple,
1000 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1001 let isCodeGenOnly = 1 in
1002 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym),
1003 "la $rD, $sym($rA)", IntGeneral,
1004 [(set i32:$rD, (add i32:$rA,
1005 (PPClo tglobaladdr:$sym, 0)))]>;
1006 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1007 "mulli $rD, $rA, $imm", IntMulLI,
1008 [(set i32:$rD, (mul i32:$rA, immSExt16:$imm))]>;
1009 let Defs = [CARRY] in {
1010 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1011 "subfic $rD, $rA, $imm", IntGeneral,
1012 [(set i32:$rD, (subc immSExt16:$imm, i32:$rA))]>;
1015 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1016 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
1017 "li $rD, $imm", IntSimple,
1018 [(set i32:$rD, immSExt16:$imm)]>;
1019 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
1020 "lis $rD, $imm", IntSimple,
1021 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1025 let PPC970_Unit = 1 in { // FXU Operations.
1026 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1027 "andi. $dst, $src1, $src2", IntGeneral,
1028 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1030 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1031 "andis. $dst, $src1, $src2", IntGeneral,
1032 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1034 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1035 "ori $dst, $src1, $src2", IntSimple,
1036 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1037 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1038 "oris $dst, $src1, $src2", IntSimple,
1039 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1040 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1041 "xori $dst, $src1, $src2", IntSimple,
1042 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1043 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1044 "xoris $dst, $src1, $src2", IntSimple,
1045 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1046 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1048 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1049 "cmpwi $crD, $rA, $imm", IntCompare>;
1050 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1051 "cmplwi $dst, $src1, $src2", IntCompare>;
1055 let PPC970_Unit = 1 in { // FXU Operations.
1056 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1057 "nand $rA, $rS, $rB", IntSimple,
1058 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1059 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1060 "and $rA, $rS, $rB", IntSimple,
1061 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1062 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1063 "andc $rA, $rS, $rB", IntSimple,
1064 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1065 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1066 "or $rA, $rS, $rB", IntSimple,
1067 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1068 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1069 "nor $rA, $rS, $rB", IntSimple,
1070 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1071 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1072 "orc $rA, $rS, $rB", IntSimple,
1073 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1074 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1075 "eqv $rA, $rS, $rB", IntSimple,
1076 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1077 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1078 "xor $rA, $rS, $rB", IntSimple,
1079 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1080 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1081 "slw $rA, $rS, $rB", IntGeneral,
1082 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1083 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1084 "srw $rA, $rS, $rB", IntGeneral,
1085 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1086 let Defs = [CARRY] in {
1087 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1088 "sraw $rA, $rS, $rB", IntShift,
1089 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1093 let PPC970_Unit = 1 in { // FXU Operations.
1094 let Defs = [CARRY] in {
1095 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1096 "srawi $rA, $rS, $SH", IntShift,
1097 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1099 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1100 "cntlzw $rA, $rS", IntGeneral,
1101 [(set i32:$rA, (ctlz i32:$rS))]>;
1102 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1103 "extsb $rA, $rS", IntSimple,
1104 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1105 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1106 "extsh $rA, $rS", IntSimple,
1107 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1109 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1110 "cmpw $crD, $rA, $rB", IntCompare>;
1111 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1112 "cmplw $crD, $rA, $rB", IntCompare>;
1114 let PPC970_Unit = 3 in { // FPU Operations.
1115 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1116 // "fcmpo $crD, $fA, $fB", FPCompare>;
1117 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1118 "fcmpu $crD, $fA, $fB", FPCompare>;
1119 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1120 "fcmpu $crD, $fA, $fB", FPCompare>;
1122 let Uses = [RM] in {
1123 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1124 "fctiwz $frD, $frB", FPGeneral,
1125 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1126 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1127 "frsp $frD, $frB", FPGeneral,
1128 [(set f32:$frD, (fround f64:$frB))]>;
1129 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1130 "fsqrt $frD, $frB", FPSqrt,
1131 [(set f64:$frD, (fsqrt f64:$frB))]>;
1132 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1133 "fsqrts $frD, $frB", FPSqrt,
1134 [(set f32:$frD, (fsqrt f32:$frB))]>;
1138 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1139 /// often coalesced away and we don't want the dispatch group builder to think
1140 /// that they will fill slots (which could cause the load of a LSU reject to
1141 /// sneak into a d-group with a store).
1142 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1143 "fmr $frD, $frB", FPGeneral,
1144 []>, // (set f32:$frD, f32:$frB)
1147 let PPC970_Unit = 3 in { // FPU Operations.
1148 // These are artificially split into two different forms, for 4/8 byte FP.
1149 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1150 "fabs $frD, $frB", FPGeneral,
1151 [(set f32:$frD, (fabs f32:$frB))]>;
1152 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1153 "fabs $frD, $frB", FPGeneral,
1154 [(set f64:$frD, (fabs f64:$frB))]>;
1155 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1156 "fnabs $frD, $frB", FPGeneral,
1157 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1158 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1159 "fnabs $frD, $frB", FPGeneral,
1160 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1161 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1162 "fneg $frD, $frB", FPGeneral,
1163 [(set f32:$frD, (fneg f32:$frB))]>;
1164 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1165 "fneg $frD, $frB", FPGeneral,
1166 [(set f64:$frD, (fneg f64:$frB))]>;
1170 // XL-Form instructions. condition register logical ops.
1172 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1173 "mcrf $BF, $BFA", BrMCR>,
1174 PPC970_DGroup_First, PPC970_Unit_CRU;
1176 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1177 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1178 "creqv $CRD, $CRA, $CRB", BrCR,
1181 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1182 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1183 "cror $CRD, $CRA, $CRB", BrCR,
1186 let isCodeGenOnly = 1 in {
1187 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1188 "creqv $dst, $dst, $dst", BrCR,
1191 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1192 "crxor $dst, $dst, $dst", BrCR,
1195 let Defs = [CR1EQ], CRD = 6 in {
1196 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1197 "creqv 6, 6, 6", BrCR,
1200 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1201 "crxor 6, 6, 6", BrCR,
1206 // XFX-Form instructions. Instructions that deal with SPRs.
1208 let Uses = [CTR] in {
1209 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1210 "mfctr $rT", SprMFSPR>,
1211 PPC970_DGroup_First, PPC970_Unit_FXU;
1213 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1214 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1215 "mtctr $rS", SprMTSPR>,
1216 PPC970_DGroup_First, PPC970_Unit_FXU;
1219 let Defs = [LR] in {
1220 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1221 "mtlr $rS", SprMTSPR>,
1222 PPC970_DGroup_First, PPC970_Unit_FXU;
1224 let Uses = [LR] in {
1225 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1226 "mflr $rT", SprMFSPR>,
1227 PPC970_DGroup_First, PPC970_Unit_FXU;
1230 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1231 // a GPR on the PPC970. As such, copies in and out have the same performance
1232 // characteristics as an OR instruction.
1233 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1234 "mtspr 256, $rS", IntGeneral>,
1235 PPC970_DGroup_Single, PPC970_Unit_FXU;
1236 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1237 "mfspr $rT, 256", IntGeneral>,
1238 PPC970_DGroup_First, PPC970_Unit_FXU;
1240 let isCodeGenOnly = 1 in {
1241 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1242 (outs VRSAVERC:$reg), (ins GPRC:$rS),
1243 "mtspr 256, $rS", IntGeneral>,
1244 PPC970_DGroup_Single, PPC970_Unit_FXU;
1245 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT),
1246 (ins VRSAVERC:$reg),
1247 "mfspr $rT, 256", IntGeneral>,
1248 PPC970_DGroup_First, PPC970_Unit_FXU;
1251 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1252 // so we'll need to scavenge a register for it.
1254 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1255 "#SPILL_VRSAVE", []>;
1257 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1258 // spilled), so we'll need to scavenge a register for it.
1260 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1261 "#RESTORE_VRSAVE", []>;
1263 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1264 "mtcrf $FXM, $rS", BrMCRX>,
1265 PPC970_MicroCode, PPC970_Unit_CRU;
1267 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1268 // declaring that here gives the local register allocator problems with this:
1270 // MFCR <kill of whatever preg got assigned to vreg>
1271 // while not declaring it breaks DeadMachineInstructionElimination.
1272 // As it turns out, in all cases where we currently use this,
1273 // we're only interested in one subregister of it. Represent this in the
1274 // instruction to keep the register allocator from becoming confused.
1276 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1277 let isCodeGenOnly = 1 in
1278 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1279 "#MFCRpseud", SprMFCR>,
1280 PPC970_MicroCode, PPC970_Unit_CRU;
1282 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1283 "mfcr $rT", SprMFCR>,
1284 PPC970_MicroCode, PPC970_Unit_CRU;
1286 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1287 "mfocrf $rT, $FXM", SprMFCR>,
1288 PPC970_DGroup_First, PPC970_Unit_CRU;
1290 // Pseudo instruction to perform FADD in round-to-zero mode.
1291 let usesCustomInserter = 1, Uses = [RM] in {
1292 def FADDrtz: Pseudo<(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "",
1293 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1296 // The above pseudo gets expanded to make use of the following instructions
1297 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1298 let Uses = [RM], Defs = [RM] in {
1299 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1300 "mtfsb0 $FM", IntMTFSB0, []>,
1301 PPC970_DGroup_Single, PPC970_Unit_FPU;
1302 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1303 "mtfsb1 $FM", IntMTFSB0, []>,
1304 PPC970_DGroup_Single, PPC970_Unit_FPU;
1305 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, F8RC:$rT),
1306 "mtfsf $FM, $rT", IntMTFSB0, []>,
1307 PPC970_DGroup_Single, PPC970_Unit_FPU;
1309 let Uses = [RM] in {
1310 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1311 "mffs $rT", IntMFFS,
1312 [(set f64:$rT, (PPCmffs))]>,
1313 PPC970_DGroup_Single, PPC970_Unit_FPU;
1317 let PPC970_Unit = 1 in { // FXU Operations.
1319 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1321 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1322 "add $rT, $rA, $rB", IntSimple,
1323 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1324 let Defs = [CARRY] in {
1325 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1326 "addc $rT, $rA, $rB", IntGeneral,
1327 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1328 PPC970_DGroup_Cracked;
1330 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1331 "divw $rT, $rA, $rB", IntDivW,
1332 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1333 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1334 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1335 "divwu $rT, $rA, $rB", IntDivW,
1336 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1337 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1338 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1339 "mulhw $rT, $rA, $rB", IntMulHW,
1340 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1341 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1342 "mulhwu $rT, $rA, $rB", IntMulHWU,
1343 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1344 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1345 "mullw $rT, $rA, $rB", IntMulHW,
1346 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1347 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1348 "subf $rT, $rA, $rB", IntGeneral,
1349 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1350 let Defs = [CARRY] in {
1351 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1352 "subfc $rT, $rA, $rB", IntGeneral,
1353 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1354 PPC970_DGroup_Cracked;
1356 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1357 "neg $rT, $rA", IntSimple,
1358 [(set i32:$rT, (ineg i32:$rA))]>;
1359 let Uses = [CARRY], Defs = [CARRY] in {
1360 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1361 "adde $rT, $rA, $rB", IntGeneral,
1362 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1363 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1364 "addme $rT, $rA", IntGeneral,
1365 [(set i32:$rT, (adde i32:$rA, -1))]>;
1366 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1367 "addze $rT, $rA", IntGeneral,
1368 [(set i32:$rT, (adde i32:$rA, 0))]>;
1369 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1370 "subfe $rT, $rA, $rB", IntGeneral,
1371 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1372 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1373 "subfme $rT, $rA", IntGeneral,
1374 [(set i32:$rT, (sube -1, i32:$rA))]>;
1375 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1376 "subfze $rT, $rA", IntGeneral,
1377 [(set i32:$rT, (sube 0, i32:$rA))]>;
1381 // A-Form instructions. Most of the instructions executed in the FPU are of
1384 let PPC970_Unit = 3 in { // FPU Operations.
1385 let Uses = [RM] in {
1386 def FMADD : AForm_1<63, 29,
1387 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1388 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1389 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1390 def FMADDS : AForm_1<59, 29,
1391 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1392 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1393 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1394 def FMSUB : AForm_1<63, 28,
1395 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1396 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1398 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1399 def FMSUBS : AForm_1<59, 28,
1400 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1401 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1403 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1404 def FNMADD : AForm_1<63, 31,
1405 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1406 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1408 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
1409 def FNMADDS : AForm_1<59, 31,
1410 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1411 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1413 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
1414 def FNMSUB : AForm_1<63, 30,
1415 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1416 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1417 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
1418 (fneg f64:$FRB))))]>;
1419 def FNMSUBS : AForm_1<59, 30,
1420 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1421 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1422 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
1423 (fneg f32:$FRB))))]>;
1425 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1426 // having 4 of these, force the comparison to always be an 8-byte double (code
1427 // should use an FMRSD if the input comparison value really wants to be a float)
1428 // and 4/8 byte forms for the result and operand type..
1429 def FSELD : AForm_1<63, 23,
1430 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1431 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1432 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
1433 def FSELS : AForm_1<63, 23,
1434 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1435 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1436 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
1437 let Uses = [RM] in {
1438 def FADD : AForm_2<63, 21,
1439 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1440 "fadd $FRT, $FRA, $FRB", FPAddSub,
1441 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
1442 def FADDS : AForm_2<59, 21,
1443 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1444 "fadds $FRT, $FRA, $FRB", FPGeneral,
1445 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
1446 def FDIV : AForm_2<63, 18,
1447 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1448 "fdiv $FRT, $FRA, $FRB", FPDivD,
1449 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
1450 def FDIVS : AForm_2<59, 18,
1451 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1452 "fdivs $FRT, $FRA, $FRB", FPDivS,
1453 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
1454 def FMUL : AForm_3<63, 25,
1455 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1456 "fmul $FRT, $FRA, $FRC", FPFused,
1457 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
1458 def FMULS : AForm_3<59, 25,
1459 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1460 "fmuls $FRT, $FRA, $FRC", FPGeneral,
1461 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
1462 def FSUB : AForm_2<63, 20,
1463 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1464 "fsub $FRT, $FRA, $FRB", FPAddSub,
1465 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
1466 def FSUBS : AForm_2<59, 20,
1467 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1468 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1469 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
1473 let PPC970_Unit = 1 in { // FXU Operations.
1474 def ISEL : AForm_4<31, 15,
1475 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, CRBITRC:$cond),
1476 "isel $rT, $rA, $rB, $cond", IntGeneral,
1480 let PPC970_Unit = 1 in { // FXU Operations.
1481 // M-Form instructions. rotate and mask instructions.
1483 let isCommutable = 1 in {
1484 // RLWIMI can be commuted if the rotate amount is zero.
1485 def RLWIMI : MForm_2<20,
1486 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1487 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1488 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1491 def RLWINM : MForm_2<21,
1492 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1493 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1495 def RLWINMo : MForm_2<21,
1496 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1497 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1498 []>, isDOT, PPC970_DGroup_Cracked;
1499 def RLWNM : MForm_2<23,
1500 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1501 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1506 //===----------------------------------------------------------------------===//
1507 // PowerPC Instruction Patterns
1510 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1511 def : Pat<(i32 imm:$imm),
1512 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1514 // Implement the 'not' operation with the NOR instruction.
1515 def NOT : Pat<(not i32:$in),
1518 // ADD an arbitrary immediate.
1519 def : Pat<(add i32:$in, imm:$imm),
1520 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1521 // OR an arbitrary immediate.
1522 def : Pat<(or i32:$in, imm:$imm),
1523 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1524 // XOR an arbitrary immediate.
1525 def : Pat<(xor i32:$in, imm:$imm),
1526 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1528 def : Pat<(sub immSExt16:$imm, i32:$in),
1529 (SUBFIC $in, imm:$imm)>;
1532 def : Pat<(shl i32:$in, (i32 imm:$imm)),
1533 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
1534 def : Pat<(srl i32:$in, (i32 imm:$imm)),
1535 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
1538 def : Pat<(rotl i32:$in, i32:$sh),
1539 (RLWNM $in, $sh, 0, 31)>;
1540 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
1541 (RLWINM $in, imm:$imm, 0, 31)>;
1544 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
1545 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1548 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1549 (BL tglobaladdr:$dst)>;
1550 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1551 (BL texternalsym:$dst)>;
1554 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1555 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1557 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1558 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1560 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1561 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1565 // Hi and Lo for Darwin Global Addresses.
1566 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1567 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1568 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1569 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1570 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1571 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1572 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1573 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1574 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
1575 (ADDIS $in, tglobaltlsaddr:$g)>;
1576 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
1577 (ADDI $in, tglobaltlsaddr:$g)>;
1578 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
1579 (ADDIS $in, tglobaladdr:$g)>;
1580 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
1581 (ADDIS $in, tconstpool:$g)>;
1582 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
1583 (ADDIS $in, tjumptable:$g)>;
1584 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
1585 (ADDIS $in, tblockaddress:$g)>;
1587 // Standard shifts. These are represented separately from the real shifts above
1588 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1590 def : Pat<(sra i32:$rS, i32:$rB),
1592 def : Pat<(srl i32:$rS, i32:$rB),
1594 def : Pat<(shl i32:$rS, i32:$rB),
1597 def : Pat<(zextloadi1 iaddr:$src),
1599 def : Pat<(zextloadi1 xaddr:$src),
1601 def : Pat<(extloadi1 iaddr:$src),
1603 def : Pat<(extloadi1 xaddr:$src),
1605 def : Pat<(extloadi8 iaddr:$src),
1607 def : Pat<(extloadi8 xaddr:$src),
1609 def : Pat<(extloadi16 iaddr:$src),
1611 def : Pat<(extloadi16 xaddr:$src),
1613 def : Pat<(f64 (extloadf32 iaddr:$src)),
1614 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1615 def : Pat<(f64 (extloadf32 xaddr:$src)),
1616 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1618 def : Pat<(f64 (fextend f32:$src)),
1619 (COPY_TO_REGCLASS $src, F8RC)>;
1622 def : Pat<(membarrier (i32 imm /*ll*/),
1626 (i32 imm /*device*/)),
1629 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1631 include "PPCInstrAltivec.td"
1632 include "PPCInstr64Bit.td"