1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
19 def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
20 return getI32Imm(PPC::getVSPLTImmediate(N, 1));
22 def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
23 return PPC::isSplatShuffleMask(N, 1);
25 def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
26 return getI32Imm(PPC::getVSPLTImmediate(N, 2));
28 def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
29 return PPC::isSplatShuffleMask(N, 2);
31 def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
32 return getI32Imm(PPC::getVSPLTImmediate(N, 4));
34 def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
35 return PPC::isSplatShuffleMask(N, 4);
39 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
40 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
42 PPC::isVecSplatImm(N, 1, &Val);
43 return getI32Imm(Val);
45 def vecspltisb : PatLeaf<(build_vector), [{
46 return PPC::isVecSplatImm(N, 1);
47 }], VSPLTISB_get_imm>;
49 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
50 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
52 PPC::isVecSplatImm(N, 2, &Val);
53 return getI32Imm(Val);
55 def vecspltish : PatLeaf<(build_vector), [{
56 return PPC::isVecSplatImm(N, 2);
57 }], VSPLTISH_get_imm>;
59 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
60 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
62 PPC::isVecSplatImm(N, 4, &Val);
63 return getI32Imm(Val);
65 def vecspltisw : PatLeaf<(build_vector), [{
66 return PPC::isVecSplatImm(N, 4);
67 }], VSPLTISW_get_imm>;
69 //===----------------------------------------------------------------------===//
70 // Helpers for defining instructions that directly correspond to intrinsics.
72 // VA1a_Int - A VAForm_1a intrinsic definition.
73 class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
74 : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
75 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
76 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
78 // VX1_Int - A VXForm_1 intrinsic definition.
79 class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
80 : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
81 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
82 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
84 // VX2_Int - A VXForm_2 intrinsic definition.
85 class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
86 : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
87 !strconcat(opc, " $vD, $vB"), VecFP,
88 [(set VRRC:$vD, (IntID VRRC:$vB))]>;
90 //===----------------------------------------------------------------------===//
91 // Instruction Definitions.
93 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
94 [(set VRRC:$rD, (v4f32 (undef)))]>;
96 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
97 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
98 "lvebx $vD, $src", LdStGeneral,
99 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
100 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
101 "lvehx $vD, $src", LdStGeneral,
102 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
103 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
104 "lvewx $vD, $src", LdStGeneral,
105 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
106 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
107 "lvx $vD, $src", LdStGeneral,
108 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
109 def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
110 "lvxl $vD, $src", LdStGeneral,
111 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
114 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src),
115 "lvsl $vD, $src", LdStGeneral,
116 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
118 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src),
119 "lvsl $vD, $src", LdStGeneral,
120 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
123 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
124 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
125 "stvebx $rS, $dst", LdStGeneral,
126 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
127 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
128 "stvehx $rS, $dst", LdStGeneral,
129 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
130 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
131 "stvewx $rS, $dst", LdStGeneral,
132 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
133 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
134 "stvx $rS, $dst", LdStGeneral,
135 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
136 def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
137 "stvxl $rS, $dst", LdStGeneral,
138 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
141 let PPC970_Unit = 5 in { // VALU Operations.
142 // VA-Form instructions. 3-input AltiVec ops.
143 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
144 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
145 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
147 Requires<[FPContractions]>;
148 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
149 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
150 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
152 Requires<[FPContractions]>;
153 def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
154 def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
155 def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
156 def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
158 def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
159 "vsldoi $vD, $vA, $vB, $SH", VecFP,
161 (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
164 // VX-Form instructions. AltiVec arithmetic ops.
165 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
166 "vaddfp $vD, $vA, $vB", VecFP,
167 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
169 def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
170 "vaddubm $vD, $vA, $vB", VecGeneral,
171 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
172 def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
173 "vadduhm $vD, $vA, $vB", VecGeneral,
174 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
175 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
176 "vadduwm $vD, $vA, $vB", VecGeneral,
177 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
179 def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
180 def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
181 def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
182 def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
183 def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
184 def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
185 def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
188 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
189 "vand $vD, $vA, $vB", VecFP,
190 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
191 def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
192 "vandc $vD, $vA, $vB", VecFP,
193 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
195 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
196 "vcfsx $vD, $vB, $UIMM", VecFP,
198 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
199 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
200 "vcfux $vD, $vB, $UIMM", VecFP,
202 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
203 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
204 "vctsxs $vD, $vB, $UIMM", VecFP,
206 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
207 "vctuxs $vD, $vB, $UIMM", VecFP,
209 def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
210 def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>;
212 def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>;
213 def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>;
214 def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>;
215 def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>;
216 def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>;
217 def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>;
219 def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>;
220 def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>;
221 def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>;
222 def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>;
223 def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>;
224 def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>;
225 def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>;
226 def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>;
227 def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>;
228 def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>;
229 def VMINSW : VX1_Int< 896, "vminsw", int_ppc_altivec_vminsw>;
230 def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>;
231 def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
232 def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
234 def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>;
235 def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>;
236 def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>;
237 def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>;
239 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
240 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
241 def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
242 def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
243 def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
244 def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
246 def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
247 def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
248 def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
249 def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
250 def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
251 def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
252 def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
253 def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
255 def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
256 def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
257 def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
258 def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
259 def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
260 def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
262 def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
264 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
265 "vsubfp $vD, $vA, $vB", VecGeneral,
266 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
267 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
268 "vsububm $vD, $vA, $vB", VecGeneral,
269 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
270 def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
271 "vsubuhm $vD, $vA, $vB", VecGeneral,
272 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
273 def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
274 "vsubuwm $vD, $vA, $vB", VecGeneral,
275 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
277 def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
278 def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
279 def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
280 def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
281 def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
282 def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
283 def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
284 def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
285 def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
286 def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
287 def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
289 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
290 "vnor $vD, $vA, $vB", VecFP,
291 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
292 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
293 "vor $vD, $vA, $vB", VecFP,
294 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
295 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
296 "vxor $vD, $vA, $vB", VecFP,
297 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
299 def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
300 def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
301 def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
302 def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
303 def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
304 def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
305 def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
307 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
308 "vspltb $vD, $vB, $UIMM", VecPerm,
309 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
310 VSPLTB_shuffle_mask:$UIMM))]>;
311 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
312 "vsplth $vD, $vB, $UIMM", VecPerm,
313 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
314 VSPLTH_shuffle_mask:$UIMM))]>;
315 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
316 "vspltw $vD, $vB, $UIMM", VecPerm,
317 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
318 VSPLTW_shuffle_mask:$UIMM))]>;
320 def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
321 def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
322 def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
323 def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
324 def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
325 def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
326 def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
327 def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
330 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
331 "vspltisb $vD, $SIMM", VecPerm,
332 [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
333 def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
334 "vspltish $vD, $SIMM", VecPerm,
335 [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
336 def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
337 "vspltisw $vD, $SIMM", VecPerm,
338 [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
341 def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
342 def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
343 def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
344 def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
345 def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
346 def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
347 "vpkuhum $vD, $vA, $vB", VecFP,
349 def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
350 def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
351 "vpkuwum $vD, $vA, $vB", VecFP,
353 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
356 def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
357 def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
358 def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
359 def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
360 def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
361 def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
364 // Altivec Comparisons.
366 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
367 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
368 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
369 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
370 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
371 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> {
376 // f32 element comparisons.0
377 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
378 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
379 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
380 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
381 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
382 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
383 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
384 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
386 // i8 element comparisons.
387 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
388 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
389 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
390 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
391 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
392 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
394 // i16 element comparisons.
395 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
396 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
397 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
398 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
399 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
400 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
402 // i32 element comparisons.
403 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
404 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
405 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
406 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
407 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
408 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
410 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
411 "vxor $vD, $vD, $vD", VecFP,
412 [(set VRRC:$vD, (v4f32 immAllZerosV))]>;
415 //===----------------------------------------------------------------------===//
416 // Additional Altivec Patterns
420 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
421 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
422 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
423 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
424 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
425 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
428 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
429 def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
430 def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
431 def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
434 def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
435 (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
436 def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
437 (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
438 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
439 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
440 def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
441 (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
444 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
445 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
446 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
448 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
449 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
450 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
452 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
453 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
454 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
456 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
457 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
458 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
460 // Immediate vector formation with vsplti*.
461 def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
462 def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
463 def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
465 def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
466 def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
467 def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
469 def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
470 def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
471 def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
473 // Logical Operations
474 def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>;
475 def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>;
476 def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>;
478 def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
479 def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
480 def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
481 def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
482 def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
483 def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
484 def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
485 def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
486 def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
487 (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
488 def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
489 (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
491 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
492 (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
494 // Fused multiply add and multiply sub for packed float. These are represented
495 // separately from the real instructions above, for operations that must have
496 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
497 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
498 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
499 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
500 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
502 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
503 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
504 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
505 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
507 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
508 (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;