1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to.
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// VPERM - The PPC VPERM Instruction.
55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
56 /// address respectively. These nodes have two operands, the first of
57 /// which must be a TargetGlobalAddress, and the second of which must be a
58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
59 /// though these are usually folded into other nodes.
64 /// The following three target-specific nodes are used for calls through
65 /// function pointers in the 64-bit SVR4 ABI.
67 /// Restore the TOC from the TOC save area of the current stack frame.
68 /// This is basically a hard coded load instruction which additionally
69 /// takes/produces a flag.
72 /// Like a regular LOAD but additionally taking/producing a flag.
75 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
76 /// a hard coded load instruction.
79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
81 /// compute an allocation on the stack.
84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
85 /// at function entry, used for PIC code.
88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
89 /// shift amounts. These nodes are generated by the multi-precision shift
93 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
97 /// CALL - A direct function call.
98 /// CALL_NOP_SVR4 is a call with the special NOP which follows 64-bit
100 CALL_Darwin, CALL_SVR4, CALL_NOP_SVR4,
102 /// NOP - Special NOP which follows 64-bit SVR4 calls.
105 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
106 /// MTCTR instruction.
109 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
110 /// BCTRL instruction.
111 BCTRL_Darwin, BCTRL_SVR4,
113 /// Return with a flag operand, matched by 'blr'
116 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
117 /// instructions. This copies the bits corresponding to the specified
118 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
122 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
123 /// instructions. For lack of better number, we use the opcode number
124 /// encoding for the OPC field to identify the compare. For example, 838
128 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
129 /// altivec VCMP*o instructions. For lack of better number, we use the
130 /// opcode number encoding for the OPC field to identify the compare. For
131 /// example, 838 is VCMPGTSH.
134 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
135 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
136 /// condition register to branch on, OPC is the branch opcode to use (e.g.
137 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
138 /// an optional input flag argument.
141 // The following 5 instructions are used only as part of the
142 // long double-to-int conversion sequence.
144 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
148 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
151 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
154 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
155 /// rounding towards zero. It has flags added so it won't move past the
156 /// FPSCR-setting instructions.
159 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
162 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
163 /// reserve indexed. This is used to implement atomic operations.
166 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
167 /// indexed. This is used to implement atomic operations.
170 /// TC_RETURN - A tail call return.
172 /// operand #1 callee (register or absolute)
173 /// operand #2 stack adjustment
174 /// operand #3 optional in flag
177 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
181 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
182 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
184 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
185 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
186 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
190 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
191 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
192 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
196 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium code model, produces
197 /// an ADDIS8 instruction that adds the TOC base register to sym@toc@ha.
200 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium code model, produces a
201 /// LD instruction with base register G8RReg and offset sym@toc@l.
202 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
205 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
206 /// an ADDI8 instruction that adds G8RReg to sym@toc@l.
207 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
212 /// Define some predicates that are used for node matching.
214 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
215 /// VPKUHUM instruction.
216 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
218 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
219 /// VPKUWUM instruction.
220 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
222 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
223 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
224 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
227 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
228 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
229 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
232 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
233 /// amount, otherwise return -1.
234 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
236 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
237 /// specifies a splat of a single element that is suitable for input to
238 /// VSPLTB/VSPLTH/VSPLTW.
239 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
241 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
243 bool isAllNegativeZeroVector(SDNode *N);
245 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
246 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
247 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
249 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
250 /// formed by using a vspltis[bhw] instruction of the specified element
251 /// size, return the constant being splatted. The ByteSize field indicates
252 /// the number of bytes of each element [124] -> [bhw].
253 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
256 class PPCTargetLowering : public TargetLowering {
257 const PPCSubtarget &PPCSubTarget;
260 explicit PPCTargetLowering(PPCTargetMachine &TM);
262 /// getTargetNodeName() - This method returns the name of a target specific
264 virtual const char *getTargetNodeName(unsigned Opcode) const;
266 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
268 /// getSetCCResultType - Return the ISD::SETCC ValueType
269 virtual EVT getSetCCResultType(EVT VT) const;
271 /// getPreIndexedAddressParts - returns true by value, base pointer and
272 /// offset pointer and addressing mode by reference if the node's address
273 /// can be legally represented as pre-indexed load / store address.
274 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
276 ISD::MemIndexedMode &AM,
277 SelectionDAG &DAG) const;
279 /// SelectAddressRegReg - Given the specified addressed, check to see if it
280 /// can be represented as an indexed [r+r] operation. Returns false if it
281 /// can be more efficiently represented with [r+imm].
282 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
283 SelectionDAG &DAG) const;
285 /// SelectAddressRegImm - Returns true if the address N can be represented
286 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
287 /// is not better represented as reg+reg.
288 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
289 SelectionDAG &DAG) const;
291 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
292 /// represented as an indexed [r+r] operation.
293 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
294 SelectionDAG &DAG) const;
296 /// SelectAddressRegImmShift - Returns true if the address N can be
297 /// represented by a base register plus a signed 14-bit displacement
298 /// [r+imm*4]. Suitable for use by STD and friends.
299 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
300 SelectionDAG &DAG) const;
302 Sched::Preference getSchedulingPreference(SDNode *N) const;
304 /// LowerOperation - Provide custom lowering hooks for some operations.
306 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
308 /// ReplaceNodeResults - Replace the results of node with an illegal result
309 /// type with new values built out of custom code.
311 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
312 SelectionDAG &DAG) const;
314 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
316 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
319 const SelectionDAG &DAG,
320 unsigned Depth = 0) const;
322 virtual MachineBasicBlock *
323 EmitInstrWithCustomInserter(MachineInstr *MI,
324 MachineBasicBlock *MBB) const;
325 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
326 MachineBasicBlock *MBB, bool is64Bit,
327 unsigned BinOpcode) const;
328 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
329 MachineBasicBlock *MBB,
330 bool is8bit, unsigned Opcode) const;
332 ConstraintType getConstraintType(const std::string &Constraint) const;
334 /// Examine constraint string and operand type and determine a weight value.
335 /// The operand object must already have been set up with the operand type.
336 ConstraintWeight getSingleConstraintMatchWeight(
337 AsmOperandInfo &info, const char *constraint) const;
339 std::pair<unsigned, const TargetRegisterClass*>
340 getRegForInlineAsmConstraint(const std::string &Constraint,
343 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
344 /// function arguments in the caller parameter area. This is the actual
345 /// alignment, not its logarithm.
346 unsigned getByValTypeAlignment(Type *Ty) const;
348 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
349 /// vector. If it is invalid, don't add anything to Ops.
350 virtual void LowerAsmOperandForConstraint(SDValue Op,
351 std::string &Constraint,
352 std::vector<SDValue> &Ops,
353 SelectionDAG &DAG) const;
355 /// isLegalAddressingMode - Return true if the addressing mode represented
356 /// by AM is legal for this target, for a load/store of the specified type.
357 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
359 /// isLegalAddressImmediate - Return true if the integer value can be used
360 /// as the offset of the target addressing mode for load / store of the
362 virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
364 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
365 /// the offset of the target addressing mode.
366 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
368 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
370 /// getOptimalMemOpType - Returns the target specific optimal type for load
371 /// and store operations as a result of memset, memcpy, and memmove
372 /// lowering. If DstAlign is zero that means it's safe to destination
373 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
374 /// means there isn't a need to check it against alignment requirement,
375 /// probably because the source does not need to be loaded. If
376 /// 'IsZeroVal' is true, that means it's safe to return a
377 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
378 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
379 /// constant so it does not need to be loaded.
380 /// It returns EVT::Other if the type should be determined using generic
381 /// target-independent logic.
383 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
384 bool IsZeroVal, bool MemcpyStrSrc,
385 MachineFunction &MF) const;
387 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
388 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
389 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
390 /// is expanded to mul + add.
391 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
394 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
395 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
398 IsEligibleForTailCallOptimization(SDValue Callee,
399 CallingConv::ID CalleeCC,
401 const SmallVectorImpl<ISD::InputArg> &Ins,
402 SelectionDAG& DAG) const;
404 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
412 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
413 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
414 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
415 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
416 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
417 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
418 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
419 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
420 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
421 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
423 const PPCSubtarget &Subtarget) const;
424 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
425 const PPCSubtarget &Subtarget) const;
426 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
427 const PPCSubtarget &Subtarget) const;
428 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
429 const PPCSubtarget &Subtarget) const;
430 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
431 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
432 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
433 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
434 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
435 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
441 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
443 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
444 CallingConv::ID CallConv, bool isVarArg,
445 const SmallVectorImpl<ISD::InputArg> &Ins,
446 DebugLoc dl, SelectionDAG &DAG,
447 SmallVectorImpl<SDValue> &InVals) const;
448 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
451 SmallVector<std::pair<unsigned, SDValue>, 8>
453 SDValue InFlag, SDValue Chain,
455 int SPDiff, unsigned NumBytes,
456 const SmallVectorImpl<ISD::InputArg> &Ins,
457 SmallVectorImpl<SDValue> &InVals) const;
460 LowerFormalArguments(SDValue Chain,
461 CallingConv::ID CallConv, bool isVarArg,
462 const SmallVectorImpl<ISD::InputArg> &Ins,
463 DebugLoc dl, SelectionDAG &DAG,
464 SmallVectorImpl<SDValue> &InVals) const;
467 LowerCall(TargetLowering::CallLoweringInfo &CLI,
468 SmallVectorImpl<SDValue> &InVals) const;
471 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
473 const SmallVectorImpl<ISD::OutputArg> &Outs,
474 LLVMContext &Context) const;
477 LowerReturn(SDValue Chain,
478 CallingConv::ID CallConv, bool isVarArg,
479 const SmallVectorImpl<ISD::OutputArg> &Outs,
480 const SmallVectorImpl<SDValue> &OutVals,
481 DebugLoc dl, SelectionDAG &DAG) const;
484 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
485 SDValue ArgVal, DebugLoc dl) const;
488 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
489 unsigned nAltivecParamsAtEnd,
490 unsigned MinReservedArea, bool isPPC64) const;
493 LowerFormalArguments_Darwin(SDValue Chain,
494 CallingConv::ID CallConv, bool isVarArg,
495 const SmallVectorImpl<ISD::InputArg> &Ins,
496 DebugLoc dl, SelectionDAG &DAG,
497 SmallVectorImpl<SDValue> &InVals) const;
499 LowerFormalArguments_64SVR4(SDValue Chain,
500 CallingConv::ID CallConv, bool isVarArg,
501 const SmallVectorImpl<ISD::InputArg> &Ins,
502 DebugLoc dl, SelectionDAG &DAG,
503 SmallVectorImpl<SDValue> &InVals) const;
505 LowerFormalArguments_32SVR4(SDValue Chain,
506 CallingConv::ID CallConv, bool isVarArg,
507 const SmallVectorImpl<ISD::InputArg> &Ins,
508 DebugLoc dl, SelectionDAG &DAG,
509 SmallVectorImpl<SDValue> &InVals) const;
512 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
513 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
514 SelectionDAG &DAG, DebugLoc dl) const;
517 LowerCall_Darwin(SDValue Chain, SDValue Callee,
518 CallingConv::ID CallConv,
519 bool isVarArg, bool isTailCall,
520 const SmallVectorImpl<ISD::OutputArg> &Outs,
521 const SmallVectorImpl<SDValue> &OutVals,
522 const SmallVectorImpl<ISD::InputArg> &Ins,
523 DebugLoc dl, SelectionDAG &DAG,
524 SmallVectorImpl<SDValue> &InVals) const;
526 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
527 CallingConv::ID CallConv,
528 bool isVarArg, bool isTailCall,
529 const SmallVectorImpl<ISD::OutputArg> &Outs,
530 const SmallVectorImpl<SDValue> &OutVals,
531 const SmallVectorImpl<ISD::InputArg> &Ins,
532 DebugLoc dl, SelectionDAG &DAG,
533 SmallVectorImpl<SDValue> &InVals) const;
535 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
536 bool isVarArg, bool isTailCall,
537 const SmallVectorImpl<ISD::OutputArg> &Outs,
538 const SmallVectorImpl<SDValue> &OutVals,
539 const SmallVectorImpl<ISD::InputArg> &Ins,
540 DebugLoc dl, SelectionDAG &DAG,
541 SmallVectorImpl<SDValue> &InVals) const;
545 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H